From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: Question about the CAT and CMT in Xen
Date: Tue, 1 Sep 2015 14:04:35 +0100
Message-ID: <55E5A263.5050708@citrix.com>
References: <CAENZ-+=oYehOkDQi8F5TwLWo5rpJCa=iV1o-POQxe0zf9GW9Uw@mail.gmail.com>
	<55E49C11.40303@citrix.com>
	<CAENZ-+mO7D6tqOctYmzbYkeUAZQ2anhY8mxyw5PCRqKOuyYLwA@mail.gmail.com>
	<20150901054716.GA19417@pengc-linux.bj.intel.com>
	<CAENZ-+kx3tDahHDetXBq7-oxjWBCc70R_1wchdZZbeUsvwWyMg@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
In-Reply-To: <CAENZ-+kx3tDahHDetXBq7-oxjWBCc70R_1wchdZZbeUsvwWyMg@mail.gmail.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Meng Xu <xumengpanda@gmail.com>, Chao Peng <chao.p.peng@linux.intel.com>
Cc: "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
List-Id: xen-devel@lists.xenproject.org

On 01/09/15 13:55, Meng Xu wrote:
> 2015-09-01 1:47 GMT-04:00 Chao Peng <chao.p.peng@linux.intel.com>:
>> On Mon, Aug 31, 2015 at 04:09:31PM -0400, Meng Xu wrote:
>>> I looked into the xen/arch/x86/psr.c and found that the function
>>> cat_cpu_init() just returned without initializing the variable
>>> "cat_socket_enable".
>>>
>>> Both  !cpu_has(c, X86_FEATURE_CAT) and c->cpuid_level <
>>> PSR_CPUID_LEVEL_CAT are evaluated as 1 inside the function
>>> cat_cpu_init().
>>>
>>> OK. I understand that  the cpuid info shows that the CPU does not
>>> support CAT. However, according to the table at
>>> http://www.intel.com/content/www/us/en/communications/cache-monitoring-cache-allocation-technologies.html,
>>>  Intel(R) Xeon(R) CPU E5-2618L v3 should support CAT.
>>>
>>> I'm not sure which part is incorrect: the hardware or the software?
>>> (Hope Chao could give some insight about this.)
>>>
>> Hmmm, from cpuid info it looks like this model does not support CAT. I'm
>> not sure which microarchitecture it is.
> According to http://www.cpu-world.com/CPUs/Xeon/Intel-Xeon%20E5-2618L%20v3.html,
> 2618L v3 is Haswell. :-(

Wikipedia agrees.

Haswell only has plain L3 cache usage information.

It is Broadwell which adds memory bandwidth monitoring, and Cache
Allocation.

~Andrew