From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EB4CC47082 for ; Tue, 8 Jun 2021 13:25:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 552E561009 for ; Tue, 8 Jun 2021 13:25:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232736AbhFHN1C (ORCPT ); Tue, 8 Jun 2021 09:27:02 -0400 Received: from out28-99.mail.aliyun.com ([115.124.28.99]:52602 "EHLO out28-99.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233011AbhFHN05 (ORCPT ); Tue, 8 Jun 2021 09:26:57 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.06712966|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.0523574-0.000283678-0.947359;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047190;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=21;RT=21;SR=0;TI=SMTPD_---.KPRhPnH_1623158698; Received: from 192.168.0.103(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KPRhPnH_1623158698) by smtp.aliyun-inc.com(10.147.41.143); Tue, 08 Jun 2021 21:24:59 +0800 Subject: Re: [PATCH 2/2] net: stmmac: Add Ingenic SoCs MAC support. To: Paul Cercueil , =?UTF-8?B?5ZGo55Cw5p2w?= Cc: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com References: <1623086867-119039-1-git-send-email-zhouyanjie@wanyeetech.com> <1623086867-119039-3-git-send-email-zhouyanjie@wanyeetech.com> From: Zhou Yanjie Message-ID: <55d2488a-d536-6541-6104-abfeb8a75c0b@wanyeetech.com> Date: Tue, 8 Jun 2021 21:24:58 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, On 2021/6/8 下午4:46, Paul Cercueil wrote: > Hi Zhou, > > Le mar., juin 8 2021 at 01:27:47 +0800, 周琰杰 (Zhou Yanjie) > a écrit : >> Add support for Ingenic SoC MAC glue layer support for the stmmac >> device driver. This driver is used on for the MAC ethernet controller >> found in the JZ4775 SoC, the X1000 SoC, the X1600 SoC, the X1830 SoC, >> and the X2000 SoC. >> >> Signed-off-by: 周琰杰 (Zhou Yanjie) >> --- >>  drivers/net/ethernet/stmicro/stmmac/Kconfig        |  16 +- >>  drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 + >>  .../net/ethernet/stmicro/stmmac/dwmac-ingenic.c    | 367 >> +++++++++++++++++++++ >>  3 files changed, 382 insertions(+), 2 deletions(-) >>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c >> >> diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig >> b/drivers/net/ethernet/stmicro/stmmac/Kconfig >> index 7737e4d0..fb58537 100644 >> --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig >> +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig >> @@ -66,6 +66,18 @@ config DWMAC_ANARION >> >>        This selects the Anarion SoC glue layer support for the stmmac >> driver. >> >> +config DWMAC_INGENIC >> +    tristate "Ingenic MAC support" >> +    default MACH_INGENIC >> +    depends on OF && HAS_IOMEM && (MACH_INGENIC || COMPILE_TEST) >> +    select MFD_SYSCON >> +    help >> +      Support for ethernet controller on Ingenic SoCs. >> + >> +      This selects Ingenic SoCs glue layer support for the stmmac >> +      device driver. This driver is used on for the Ingenic SoCs >> +      MAC ethernet controller. >> + >>  config DWMAC_IPQ806X >>      tristate "QCA IPQ806x DWMAC support" >>      default ARCH_QCOM >> @@ -129,7 +141,7 @@ config DWMAC_QCOM_ETHQOS >> >>  config DWMAC_ROCKCHIP >>      tristate "Rockchip dwmac support" >> -    default ARCH_ROCKCHIP >> +    default MACH_ROCKCHIP >>      depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) >>      select MFD_SYSCON >>      help >> @@ -164,7 +176,7 @@ config DWMAC_STI >> >>  config DWMAC_STM32 >>      tristate "STM32 DWMAC support" >> -    default ARCH_STM32 >> +    default MACH_STM32 >>      depends on OF && HAS_IOMEM && (ARCH_STM32 || COMPILE_TEST) >>      select MFD_SYSCON >>      help >> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile >> b/drivers/net/ethernet/stmicro/stmmac/Makefile >> index f2e478b..6471f93 100644 >> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile >> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile >> @@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += >> stmmac_selftests.o >>  # Ordering matters. Generic driver must be last. >>  obj-$(CONFIG_STMMAC_PLATFORM)    += stmmac-platform.o >>  obj-$(CONFIG_DWMAC_ANARION)    += dwmac-anarion.o >> +obj-$(CONFIG_DWMAC_INGENIC)    += dwmac-ingenic.o >>  obj-$(CONFIG_DWMAC_IPQ806X)    += dwmac-ipq806x.o >>  obj-$(CONFIG_DWMAC_LPC18XX)    += dwmac-lpc18xx.o >>  obj-$(CONFIG_DWMAC_MEDIATEK)    += dwmac-mediatek.o >> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c >> b/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c >> new file mode 100644 >> index 00000000..8be8caa >> --- /dev/null >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c >> @@ -0,0 +1,367 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer >> + * >> + * Copyright (c) 2020 周琰杰 (Zhou Yanjie) > > 2021? Sure, I will change it. > >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "stmmac_platform.h" >> + >> +#define MACPHYC_TXCLK_SEL_MASK        GENMASK(31, 31) >> +#define MACPHYC_TXCLK_SEL_OUTPUT    0x1 >> +#define MACPHYC_TXCLK_SEL_INPUT        0x0 >> +#define MACPHYC_MODE_SEL_MASK        GENMASK(31, 31) >> +#define MACPHYC_MODE_SEL_RMII        0x0 >> +#define MACPHYC_TX_SEL_MASK            GENMASK(19, 19) >> +#define MACPHYC_TX_SEL_ORIGIN        0x0 >> +#define MACPHYC_TX_SEL_DELAY        0x1 >> +#define MACPHYC_TX_DELAY_MASK        GENMASK(18, 12) >> +#define MACPHYC_TX_DELAY_63_UNIT    0x3e >> +#define MACPHYC_RX_SEL_MASK            GENMASK(11, 11) >> +#define MACPHYC_RX_SEL_ORIGIN        0x0 >> +#define MACPHYC_RX_SEL_DELAY        0x1 >> +#define MACPHYC_RX_DELAY_MASK        GENMASK(10, 4) >> +#define MACPHYC_SOFT_RST_MASK        GENMASK(3, 3) >> +#define MACPHYC_PHY_INFT_MASK        GENMASK(2, 0) >> +#define MACPHYC_PHY_INFT_RMII        0x4 >> +#define MACPHYC_PHY_INFT_RGMII        0x1 >> +#define MACPHYC_PHY_INFT_GMII        0x0 >> +#define MACPHYC_PHY_INFT_MII        0x0 >> + >> +enum ingenic_mac_version { >> +    ID_JZ4775, >> +    ID_X1000, >> +    ID_X1600, >> +    ID_X1830, >> +    ID_X2000, > > You could test it on all these? I never heard about the X1600 before. > Yes, X1600 is a new model for industrial control applications that has just been launched. It has two CAN interfaces and one CDBUS interface. >> +}; >> + >> +struct ingenic_mac { >> +    const struct ingenic_soc_info *soc_info; >> +    struct device *dev; >> +    struct regmap *regmap; >> +}; >> + >> +struct ingenic_soc_info { >> +    enum ingenic_mac_version version; >> +    u32 mask; >> + >> +    int (*set_mode)(struct plat_stmmacenet_data *plat_dat); >> +    int (*suspend)(struct ingenic_mac *mac); >> +    void (*resume)(struct ingenic_mac *mac); > > These suspend/resume callbacks are not used anywhere - just drop them. > Sure. >> +}; >> + >> +static int ingenic_mac_init(struct plat_stmmacenet_data *plat_dat) >> +{ >> +    struct ingenic_mac *mac = plat_dat->bsp_priv; >> +    int ret; >> + >> +    if (mac->soc_info->set_mode) { >> +        ret = mac->soc_info->set_mode(plat_dat); >> +        if (ret) >> +            return ret; >> +    } >> + >> +    return ret; > > You are returning an uninitialized variable. > Sure, I'll change it in the next version. >> +} >> + >> +static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat) >> +{ >> +    struct ingenic_mac *mac = plat_dat->bsp_priv; >> +    int val; > > unsigned int val; > Sure. >> + >> +    switch (plat_dat->interface) { >> +    case PHY_INTERFACE_MODE_MII: >> +        val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, >> MACPHYC_TXCLK_SEL_INPUT) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII); >> +        pr_debug("MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n"); > > Use dev_dbg() with mac->dev, instead of pr_debug(). > > (Same for all pr_debug() calls below) > Sure. >> +        break; >> + >> +    case PHY_INTERFACE_MODE_GMII: >> +        val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, >> MACPHYC_TXCLK_SEL_INPUT) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_GMII\n"); >> +        break; >> + >> +    case PHY_INTERFACE_MODE_RMII: >> +        val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, >> MACPHYC_TXCLK_SEL_INPUT) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RMII\n"); >> +        break; >> + >> +    case PHY_INTERFACE_MODE_RGMII: >> +        val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, >> MACPHYC_TXCLK_SEL_INPUT) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, >> MACPHYC_PHY_INFT_RGMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RGMII\n"); >> +        break; >> + >> +    default: >> +        dev_err(mac->dev, "unsupported interface %d", >> plat_dat->interface); >> +        return -EINVAL; >> +    } >> + >> +    /* Update MAC PHY control register */ >> +    return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, >> val); >> +} >> + >> +static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat) >> +{ >> +    struct ingenic_mac *mac = plat_dat->bsp_priv; >> +    int val; >> + >> +    switch (plat_dat->interface) { >> +    case PHY_INTERFACE_MODE_RMII: >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RMII\n"); >> +        break; >> + >> +    default: >> +        dev_err(mac->dev, "unsupported interface %d", >> plat_dat->interface); >> +        return -EINVAL; >> +    } >> + >> +    /* Update MAC PHY control register */ >> +    return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, >> val); > > You're passing 'val', which is an uninitialized variable. > I will fix this int the next version. >> +} >> + >> +static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat) >> +{ >> +    struct ingenic_mac *mac = plat_dat->bsp_priv; >> +    int val; > > unsigned int val; > Sure. >> + >> +    switch (plat_dat->interface) { >> +    case PHY_INTERFACE_MODE_RMII: >> +        val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RMII\n"); >> +        break; >> + >> +    default: >> +        dev_err(mac->dev, "unsupported interface %d", >> plat_dat->interface); >> +        return -EINVAL; >> +    } >> + >> +    /* Update MAC PHY control register */ >> +    return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, >> val); >> +} >> + >> +static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat) >> +{ >> +    struct ingenic_mac *mac = plat_dat->bsp_priv; >> +    int val; > > Same here, > Sure. >> + >> +    switch (plat_dat->interface) { >> +    case PHY_INTERFACE_MODE_RMII: >> +        val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, >> MACPHYC_MODE_SEL_RMII) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RMII\n"); >> +        break; >> + >> +    default: >> +        dev_err(mac->dev, "unsupported interface %d", >> plat_dat->interface); >> +        return -EINVAL; >> +    } >> + >> +    /* Update MAC PHY control register */ >> +    return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, >> val); >> +} >> + >> +static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat) >> +{ >> +    struct ingenic_mac *mac = plat_dat->bsp_priv; >> +    int val; > > Same here. > Sure. >> + >> +    switch (plat_dat->interface) { >> +    case PHY_INTERFACE_MODE_RMII: >> +        val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) | >> +              FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RMII\n"); >> +        break; >> + >> +    case PHY_INTERFACE_MODE_RGMII: >> +        val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_DELAY) | >> +              FIELD_PREP(MACPHYC_TX_DELAY_MASK, >> MACPHYC_TX_DELAY_63_UNIT) | >> +              FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) | >> +              FIELD_PREP(MACPHYC_PHY_INFT_MASK, >> MACPHYC_PHY_INFT_RGMII); >> +        pr_debug("MAC PHY Control Register: >> PHY_INTERFACE_MODE_RGMII\n"); >> +        break; >> + >> +    default: >> +        dev_err(mac->dev, "unsupported interface %d", >> plat_dat->interface); >> +        return -EINVAL; >> +    } >> + >> +    /* Update MAC PHY control register */ >> +    return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, >> val); >> +} >> + >> +static int ingenic_mac_probe(struct platform_device *pdev) >> +{ >> +    struct plat_stmmacenet_data *plat_dat; >> +    struct stmmac_resources stmmac_res; >> +    struct ingenic_mac *mac; >> +    const struct ingenic_soc_info *data; >> +    int ret; >> + >> +    ret = stmmac_get_platform_resources(pdev, &stmmac_res); >> +    if (ret) >> +        return ret; >> + >> +    plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); >> +    if (IS_ERR(plat_dat)) >> +        return PTR_ERR(plat_dat); >> + >> +    mac = devm_kzalloc(&pdev->dev, sizeof(*mac), GFP_KERNEL); >> +    if (!mac) { >> +        ret = -ENOMEM; >> +        goto err_remove_config_dt; >> +    } >> + >> +    data = of_device_get_match_data(&pdev->dev); >> +    if (!data) { >> +        dev_err(&pdev->dev, "no of match data provided\n"); >> +        ret = -EINVAL; >> +        goto err_remove_config_dt; >> +    } >> + >> +    /* Get MAC PHY control register */ >> +    mac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, >> "mode-reg"); >> +    if (IS_ERR(mac->regmap)) { >> +        pr_err("%s: failed to get syscon regmap\n", __func__); > > dev_err? > Sure, I will change this in v2. >> +        goto err_remove_config_dt; >> +    } >> + >> +    mac->soc_info = data; >> +    mac->dev = &pdev->dev; >> + >> +    plat_dat->bsp_priv = mac; >> + >> +    ret = ingenic_mac_init(plat_dat); >> +    if (ret) >> +        goto err_remove_config_dt; >> + >> +    ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); >> +    if (ret) >> +        goto err_remove_config_dt; >> + >> +    return 0; >> + >> +err_remove_config_dt: >> +    stmmac_remove_config_dt(pdev, plat_dat); >> + >> +    return ret; >> +} >> + >> +#ifdef CONFIG_PM_SLEEP > > Remove this #ifdef. > Sure. >> +static int ingenic_mac_suspend(struct device *dev) >> +{ >> +    struct net_device *ndev = dev_get_drvdata(dev); >> +    struct stmmac_priv *priv = netdev_priv(ndev); >> +    struct ingenic_mac *mac = priv->plat->bsp_priv; >> + >> +    int ret; >> + >> +    ret = stmmac_suspend(dev); >> + >> +    if (mac->soc_info->suspend) >> +        ret = mac->soc_info->suspend(mac); >> + >> +    return ret; >> +} >> + >> +static int ingenic_mac_resume(struct device *dev) >> +{ >> +    struct net_device *ndev = dev_get_drvdata(dev); >> +    struct stmmac_priv *priv = netdev_priv(ndev); >> +    struct ingenic_mac *mac = priv->plat->bsp_priv; >> +    int ret; >> + >> +    if (mac->soc_info->resume) >> +        mac->soc_info->resume(mac); >> + >> +    ret = ingenic_mac_init(priv->plat); >> +    if (ret) >> +        return ret; >> + >> +    ret = stmmac_resume(dev); >> + >> +    return ret; >> +} >> +#endif /* CONFIG_PM_SLEEP */ >> + >> +static SIMPLE_DEV_PM_OPS(ingenic_mac_pm_ops, >> +    ingenic_mac_suspend, ingenic_mac_resume); >> + >> +static struct ingenic_soc_info jz4775_soc_info = { >> +    .version = ID_JZ4775, >> +    .mask = MACPHYC_TXCLK_SEL_MASK | MACPHYC_SOFT_RST_MASK | >> MACPHYC_PHY_INFT_MASK, >> + >> +    .set_mode = jz4775_mac_set_mode, >> +}; >> + >> +static struct ingenic_soc_info x1000_soc_info = { >> +    .version = ID_X1000, >> +    .mask = MACPHYC_SOFT_RST_MASK, >> + >> +    .set_mode = x1000_mac_set_mode, >> +}; >> + >> +static struct ingenic_soc_info x1600_soc_info = { >> +    .version = ID_X1600, >> +    .mask = MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK, >> + >> +    .set_mode = x1600_mac_set_mode, >> +}; >> + >> +static struct ingenic_soc_info x1830_soc_info = { >> +    .version = ID_X1830, >> +    .mask = MACPHYC_MODE_SEL_MASK | MACPHYC_SOFT_RST_MASK | >> MACPHYC_PHY_INFT_MASK, >> + >> +    .set_mode = x1830_mac_set_mode, >> +}; >> + >> +static struct ingenic_soc_info x2000_soc_info = { >> +    .version = ID_X2000, >> +    .mask = MACPHYC_TX_SEL_MASK | MACPHYC_TX_DELAY_MASK | >> MACPHYC_RX_SEL_MASK | >> +            MACPHYC_RX_DELAY_MASK | MACPHYC_SOFT_RST_MASK | >> MACPHYC_PHY_INFT_MASK, >> + >> +    .set_mode = x2000_mac_set_mode, >> +}; >> + >> +static const struct of_device_id ingenic_mac_of_matches[] = { >> +    { .compatible = "ingenic,jz4775-mac", .data = &jz4775_soc_info }, >> +    { .compatible = "ingenic,x1000-mac", .data = &x1000_soc_info }, >> +    { .compatible = "ingenic,x1600-mac", .data = &x1600_soc_info }, >> +    { .compatible = "ingenic,x1830-mac", .data = &x1830_soc_info }, >> +    { .compatible = "ingenic,x2000-mac", .data = &x2000_soc_info }, >> +    { } >> +}; >> +MODULE_DEVICE_TABLE(of, ingenic_mac_of_matches); >> + >> +static struct platform_driver ingenic_mac_driver = { >> +    .probe        = ingenic_mac_probe, >> +    .remove        = stmmac_pltfr_remove, >> +    .driver        = { >> +        .name    = "ingenic-mac", >> +        .pm        = &ingenic_mac_pm_ops, > > .pm = pm_ptr(&ingenic_mac_pm_ops), > Sure. Thanks and best regards! >> +        .of_match_table = ingenic_mac_of_matches, >> +    }, >> +}; >> +module_platform_driver(ingenic_mac_driver); >> + >> +MODULE_AUTHOR("周琰杰 (Zhou Yanjie) "); >> +MODULE_DESCRIPTION("Ingenic SoCs DWMAC specific glue layer"); >> +MODULE_LICENSE("GPL v2"); >> -- >> 2.7.4 >> > > Cheers, > -Paul > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD850C47082 for ; Tue, 8 Jun 2021 13:27:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6B8B661009 for ; Tue, 8 Jun 2021 13:27:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6B8B661009 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=wanyeetech.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:Cc:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=z0p3+uytW7UqAi6Im5qr87yf8nvFdjHQJ/VVkgn8Kw0=; b=DMQuzbOE333KeyVzkzmYc3aq1c iHorJcRA1htDg1QPGqSsXJrnzVFYDMsSaFRo53xkG9saVD6fj5DQjme9StP+8mBQS3K3IbvTilOxG g50WFA2h3Pqf+leHlrseqVAeY7TqbYphB82a6lSpE3cABOVJKYOfLlISwo5Z2ZHZ067R2O3OIPtpB WnT+dNT8uCp3mVuB/FIUmW+djTP/bnQS4Vi8wU8bMIIDxHLrer4AACDywU9OaYArWDGD/rqILPqkm CIkbvbM0VMR9sukh3hwohuIPDu2ZBms7wiKTE3bKuqGroY98YEY+BojwbmvaV4WI39qGUdbNafcMU getchReA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqbjG-008cjP-6P; Tue, 08 Jun 2021 13:25:14 +0000 Received: from out28-122.mail.aliyun.com ([115.124.28.122]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqbj8-008cdE-Pg for linux-arm-kernel@lists.infradead.org; Tue, 08 Jun 2021 13:25:10 +0000 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.06712966|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0523574-0.000283678-0.947359; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047190; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=21; RT=21; SR=0; TI=SMTPD_---.KPRhPnH_1623158698; Received: from 192.168.0.103(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KPRhPnH_1623158698) by smtp.aliyun-inc.com(10.147.41.143); Tue, 08 Jun 2021 21:24:59 +0800 Subject: Re: [PATCH 2/2] net: stmmac: Add Ingenic SoCs MAC support. To: Paul Cercueil , =?UTF-8?B?5ZGo55Cw5p2w?= Cc: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com References: <1623086867-119039-1-git-send-email-zhouyanjie@wanyeetech.com> <1623086867-119039-3-git-send-email-zhouyanjie@wanyeetech.com> From: Zhou Yanjie Message-ID: <55d2488a-d536-6541-6104-abfeb8a75c0b@wanyeetech.com> Date: Tue, 8 Jun 2021 21:24:58 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210608_062507_383437_D2129AE4 X-CRM114-Status: GOOD ( 27.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgUGF1bCwKCk9uIDIwMjEvNi84IOS4i+WNiDQ6NDYsIFBhdWwgQ2VyY3VlaWwgd3JvdGU6Cj4g SGkgWmhvdSwKPgo+IExlIG1hci4sIGp1aW4gOCAyMDIxIGF0IDAxOjI3OjQ3ICswODAwLCDlkajn kLDmnbAgKFpob3UgWWFuamllKSAKPiA8emhvdXlhbmppZUB3YW55ZWV0ZWNoLmNvbT4gYSDDqWNy aXQgOgo+PiBBZGQgc3VwcG9ydCBmb3IgSW5nZW5pYyBTb0MgTUFDIGdsdWUgbGF5ZXIgc3VwcG9y dCBmb3IgdGhlIHN0bW1hYwo+PiBkZXZpY2UgZHJpdmVyLiBUaGlzIGRyaXZlciBpcyB1c2VkIG9u IGZvciB0aGUgTUFDIGV0aGVybmV0IGNvbnRyb2xsZXIKPj4gZm91bmQgaW4gdGhlIEpaNDc3NSBT b0MsIHRoZSBYMTAwMCBTb0MsIHRoZSBYMTYwMCBTb0MsIHRoZSBYMTgzMCBTb0MsCj4+IGFuZCB0 aGUgWDIwMDAgU29DLgo+Pgo+PiBTaWduZWQtb2ZmLWJ5OiDlkajnkLDmnbAgKFpob3UgWWFuamll KSA8emhvdXlhbmppZUB3YW55ZWV0ZWNoLmNvbT4KPj4gLS0tCj4+IMKgZHJpdmVycy9uZXQvZXRo ZXJuZXQvc3RtaWNyby9zdG1tYWMvS2NvbmZpZ8KgwqDCoMKgwqDCoMKgIHzCoCAxNiArLQo+PiDC oGRyaXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL01ha2VmaWxlwqDCoMKgwqDCoMKg IHzCoMKgIDEgKwo+PiDCoC4uLi9uZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvZHdtYWMtaW5n ZW5pYy5jwqDCoMKgIHwgMzY3IAo+PiArKysrKysrKysrKysrKysrKysrKysKPj4gwqAzIGZpbGVz IGNoYW5nZWQsIDM4MiBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQo+PiDCoGNyZWF0ZSBt b2RlIDEwMDY0NCBkcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd21hYy1pbmdl bmljLmMKPj4KPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3Rt bWFjL0tjb25maWcgCj4+IGIvZHJpdmVycy9uZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvS2Nv bmZpZwo+PiBpbmRleCA3NzM3ZTRkMC4uZmI1ODUzNyAxMDA2NDQKPj4gLS0tIGEvZHJpdmVycy9u ZXQvZXRoZXJuZXQvc3RtaWNyby9zdG1tYWMvS2NvbmZpZwo+PiArKysgYi9kcml2ZXJzL25ldC9l dGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9LY29uZmlnCj4+IEBAIC02Niw2ICs2NiwxOCBAQCBjb25m aWcgRFdNQUNfQU5BUklPTgo+Pgo+PiDCoMKgwqDCoMKgwqAgVGhpcyBzZWxlY3RzIHRoZSBBbmFy aW9uIFNvQyBnbHVlIGxheWVyIHN1cHBvcnQgZm9yIHRoZSBzdG1tYWMgCj4+IGRyaXZlci4KPj4K Pj4gK2NvbmZpZyBEV01BQ19JTkdFTklDCj4+ICvCoMKgwqAgdHJpc3RhdGUgIkluZ2VuaWMgTUFD IHN1cHBvcnQiCj4+ICvCoMKgwqAgZGVmYXVsdCBNQUNIX0lOR0VOSUMKPj4gK8KgwqDCoCBkZXBl bmRzIG9uIE9GICYmIEhBU19JT01FTSAmJiAoTUFDSF9JTkdFTklDIHx8IENPTVBJTEVfVEVTVCkK Pj4gK8KgwqDCoCBzZWxlY3QgTUZEX1NZU0NPTgo+PiArwqDCoMKgIGhlbHAKPj4gK8KgwqDCoMKg wqAgU3VwcG9ydCBmb3IgZXRoZXJuZXQgY29udHJvbGxlciBvbiBJbmdlbmljIFNvQ3MuCj4+ICsK Pj4gK8KgwqDCoMKgwqAgVGhpcyBzZWxlY3RzIEluZ2VuaWMgU29DcyBnbHVlIGxheWVyIHN1cHBv cnQgZm9yIHRoZSBzdG1tYWMKPj4gK8KgwqDCoMKgwqAgZGV2aWNlIGRyaXZlci4gVGhpcyBkcml2 ZXIgaXMgdXNlZCBvbiBmb3IgdGhlIEluZ2VuaWMgU29Dcwo+PiArwqDCoMKgwqDCoCBNQUMgZXRo ZXJuZXQgY29udHJvbGxlci4KPj4gKwo+PiDCoGNvbmZpZyBEV01BQ19JUFE4MDZYCj4+IMKgwqDC oMKgIHRyaXN0YXRlICJRQ0EgSVBRODA2eCBEV01BQyBzdXBwb3J0Igo+PiDCoMKgwqDCoCBkZWZh dWx0IEFSQ0hfUUNPTQo+PiBAQCAtMTI5LDcgKzE0MSw3IEBAIGNvbmZpZyBEV01BQ19RQ09NX0VU SFFPUwo+Pgo+PiDCoGNvbmZpZyBEV01BQ19ST0NLQ0hJUAo+PiDCoMKgwqDCoCB0cmlzdGF0ZSAi Um9ja2NoaXAgZHdtYWMgc3VwcG9ydCIKPj4gLcKgwqDCoCBkZWZhdWx0IEFSQ0hfUk9DS0NISVAK Pj4gK8KgwqDCoCBkZWZhdWx0IE1BQ0hfUk9DS0NISVAKPj4gwqDCoMKgwqAgZGVwZW5kcyBvbiBP RiAmJiAoQVJDSF9ST0NLQ0hJUCB8fCBDT01QSUxFX1RFU1QpCj4+IMKgwqDCoMKgIHNlbGVjdCBN RkRfU1lTQ09OCj4+IMKgwqDCoMKgIGhlbHAKPj4gQEAgLTE2NCw3ICsxNzYsNyBAQCBjb25maWcg RFdNQUNfU1RJCj4+Cj4+IMKgY29uZmlnIERXTUFDX1NUTTMyCj4+IMKgwqDCoMKgIHRyaXN0YXRl ICJTVE0zMiBEV01BQyBzdXBwb3J0Igo+PiAtwqDCoMKgIGRlZmF1bHQgQVJDSF9TVE0zMgo+PiAr wqDCoMKgIGRlZmF1bHQgTUFDSF9TVE0zMgo+PiDCoMKgwqDCoCBkZXBlbmRzIG9uIE9GICYmIEhB U19JT01FTSAmJiAoQVJDSF9TVE0zMiB8fCBDT01QSUxFX1RFU1QpCj4+IMKgwqDCoMKgIHNlbGVj dCBNRkRfU1lTQ09OCj4+IMKgwqDCoMKgIGhlbHAKPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbmV0 L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL01ha2VmaWxlIAo+PiBiL2RyaXZlcnMvbmV0L2V0aGVy bmV0L3N0bWljcm8vc3RtbWFjL01ha2VmaWxlCj4+IGluZGV4IGYyZTQ3OGIuLjY0NzFmOTMgMTAw NjQ0Cj4+IC0tLSBhL2RyaXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL01ha2VmaWxl Cj4+ICsrKyBiL2RyaXZlcnMvbmV0L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL01ha2VmaWxlCj4+ IEBAIC0xNCw2ICsxNCw3IEBAIHN0bW1hYy0kKENPTkZJR19TVE1NQUNfU0VMRlRFU1RTKSArPSAK Pj4gc3RtbWFjX3NlbGZ0ZXN0cy5vCj4+IMKgIyBPcmRlcmluZyBtYXR0ZXJzLiBHZW5lcmljIGRy aXZlciBtdXN0IGJlIGxhc3QuCj4+IMKgb2JqLSQoQ09ORklHX1NUTU1BQ19QTEFURk9STSnCoMKg wqAgKz0gc3RtbWFjLXBsYXRmb3JtLm8KPj4gwqBvYmotJChDT05GSUdfRFdNQUNfQU5BUklPTinC oMKgwqAgKz0gZHdtYWMtYW5hcmlvbi5vCj4+ICtvYmotJChDT05GSUdfRFdNQUNfSU5HRU5JQynC oMKgwqAgKz0gZHdtYWMtaW5nZW5pYy5vCj4+IMKgb2JqLSQoQ09ORklHX0RXTUFDX0lQUTgwNlgp wqDCoMKgICs9IGR3bWFjLWlwcTgwNngubwo+PiDCoG9iai0kKENPTkZJR19EV01BQ19MUEMxOFhY KcKgwqDCoCArPSBkd21hYy1scGMxOHh4Lm8KPj4gwqBvYmotJChDT05GSUdfRFdNQUNfTUVESUFU RUspwqDCoMKgICs9IGR3bWFjLW1lZGlhdGVrLm8KPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbmV0 L2V0aGVybmV0L3N0bWljcm8vc3RtbWFjL2R3bWFjLWluZ2VuaWMuYyAKPj4gYi9kcml2ZXJzL25l dC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd21hYy1pbmdlbmljLmMKPj4gbmV3IGZpbGUgbW9k ZSAxMDA2NDQKPj4gaW5kZXggMDAwMDAwMDAuLjhiZThjYWEKPj4gLS0tIC9kZXYvbnVsbAo+PiAr KysgYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9zdG1pY3JvL3N0bW1hYy9kd21hYy1pbmdlbmljLmMK Pj4gQEAgLTAsMCArMSwzNjcgQEAKPj4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwt Mi4wCj4+ICsvKgo+PiArICogZHdtYWMtaW5nZW5pYy5jIC0gSW5nZW5pYyBTb0NzIERXTUFDIHNw ZWNpZmljIGdsdWUgbGF5ZXIKPj4gKyAqCj4+ICsgKiBDb3B5cmlnaHQgKGMpIDIwMjAg5ZGo55Cw 5p2wIChaaG91IFlhbmppZSkgPHpob3V5YW5qaWVAd2FueWVldGVjaC5jb20+Cj4KPiAyMDIxPwoK ClN1cmUsIEkgd2lsbCBjaGFuZ2UgaXQuCgoKPgo+PiArICovCj4+ICsKPj4gKyNpbmNsdWRlIDxs aW51eC9iaXRmaWVsZC5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L2Nsay5oPgo+PiArI2luY2x1ZGUg PGxpbnV4L2tlcm5lbC5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L21mZC9zeXNjb24uaD4KPj4gKyNp bmNsdWRlIDxsaW51eC9tb2R1bGUuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9vZi5oPgo+PiArI2lu Y2x1ZGUgPGxpbnV4L29mX2RldmljZS5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L29mX25ldC5oPgo+ PiArI2luY2x1ZGUgPGxpbnV4L3BoeS5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2Rl dmljZS5oPgo+PiArI2luY2x1ZGUgPGxpbnV4L3JlZ21hcC5oPgo+PiArI2luY2x1ZGUgPGxpbnV4 L3NsYWIuaD4KPj4gKyNpbmNsdWRlIDxsaW51eC9zdG1tYWMuaD4KPj4gKwo+PiArI2luY2x1ZGUg InN0bW1hY19wbGF0Zm9ybS5oIgo+PiArCj4+ICsjZGVmaW5lIE1BQ1BIWUNfVFhDTEtfU0VMX01B U0vCoMKgwqDCoMKgwqDCoCBHRU5NQVNLKDMxLCAzMSkKPj4gKyNkZWZpbmUgTUFDUEhZQ19UWENM S19TRUxfT1VUUFVUwqDCoMKgIDB4MQo+PiArI2RlZmluZSBNQUNQSFlDX1RYQ0xLX1NFTF9JTlBV VMKgwqDCoMKgwqDCoMKgIDB4MAo+PiArI2RlZmluZSBNQUNQSFlDX01PREVfU0VMX01BU0vCoMKg wqDCoMKgwqDCoCBHRU5NQVNLKDMxLCAzMSkKPj4gKyNkZWZpbmUgTUFDUEhZQ19NT0RFX1NFTF9S TUlJwqDCoMKgwqDCoMKgwqAgMHgwCj4+ICsjZGVmaW5lIE1BQ1BIWUNfVFhfU0VMX01BU0vCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIEdFTk1BU0soMTksIDE5KQo+PiArI2RlZmluZSBNQUNQSFlDX1RY X1NFTF9PUklHSU7CoMKgwqDCoMKgwqDCoCAweDAKPj4gKyNkZWZpbmUgTUFDUEhZQ19UWF9TRUxf REVMQVnCoMKgwqDCoMKgwqDCoCAweDEKPj4gKyNkZWZpbmUgTUFDUEhZQ19UWF9ERUxBWV9NQVNL wqDCoMKgwqDCoMKgwqAgR0VOTUFTSygxOCwgMTIpCj4+ICsjZGVmaW5lIE1BQ1BIWUNfVFhfREVM QVlfNjNfVU5JVMKgwqDCoCAweDNlCj4+ICsjZGVmaW5lIE1BQ1BIWUNfUlhfU0VMX01BU0vCoMKg wqDCoMKgwqDCoMKgwqDCoMKgIEdFTk1BU0soMTEsIDExKQo+PiArI2RlZmluZSBNQUNQSFlDX1JY X1NFTF9PUklHSU7CoMKgwqDCoMKgwqDCoCAweDAKPj4gKyNkZWZpbmUgTUFDUEhZQ19SWF9TRUxf REVMQVnCoMKgwqDCoMKgwqDCoCAweDEKPj4gKyNkZWZpbmUgTUFDUEhZQ19SWF9ERUxBWV9NQVNL wqDCoMKgwqDCoMKgwqAgR0VOTUFTSygxMCwgNCkKPj4gKyNkZWZpbmUgTUFDUEhZQ19TT0ZUX1JT VF9NQVNLwqDCoMKgwqDCoMKgwqAgR0VOTUFTSygzLCAzKQo+PiArI2RlZmluZSBNQUNQSFlDX1BI WV9JTkZUX01BU0vCoMKgwqDCoMKgwqDCoCBHRU5NQVNLKDIsIDApCj4+ICsjZGVmaW5lIE1BQ1BI WUNfUEhZX0lORlRfUk1JScKgwqDCoMKgwqDCoMKgIDB4NAo+PiArI2RlZmluZSBNQUNQSFlDX1BI WV9JTkZUX1JHTUlJwqDCoMKgwqDCoMKgwqAgMHgxCj4+ICsjZGVmaW5lIE1BQ1BIWUNfUEhZX0lO RlRfR01JScKgwqDCoMKgwqDCoMKgIDB4MAo+PiArI2RlZmluZSBNQUNQSFlDX1BIWV9JTkZUX01J ScKgwqDCoMKgwqDCoMKgIDB4MAo+PiArCj4+ICtlbnVtIGluZ2VuaWNfbWFjX3ZlcnNpb24gewo+ PiArwqDCoMKgIElEX0paNDc3NSwKPj4gK8KgwqDCoCBJRF9YMTAwMCwKPj4gK8KgwqDCoCBJRF9Y MTYwMCwKPj4gK8KgwqDCoCBJRF9YMTgzMCwKPj4gK8KgwqDCoCBJRF9YMjAwMCwKPgo+IFlvdSBj b3VsZCB0ZXN0IGl0IG9uIGFsbCB0aGVzZT8gSSBuZXZlciBoZWFyZCBhYm91dCB0aGUgWDE2MDAg YmVmb3JlLgo+CgpZZXMsIFgxNjAwIGlzIGEgbmV3IG1vZGVsIGZvciBpbmR1c3RyaWFsIGNvbnRy b2wgYXBwbGljYXRpb25zIHRoYXQgaGFzCgpqdXN0IGJlZW4gbGF1bmNoZWQuIEl0IGhhcyB0d28g Q0FOIGludGVyZmFjZXMgYW5kIG9uZSBDREJVUyBpbnRlcmZhY2UuCgoKPj4gK307Cj4+ICsKPj4g K3N0cnVjdCBpbmdlbmljX21hYyB7Cj4+ICvCoMKgwqAgY29uc3Qgc3RydWN0IGluZ2VuaWNfc29j X2luZm8gKnNvY19pbmZvOwo+PiArwqDCoMKgIHN0cnVjdCBkZXZpY2UgKmRldjsKPj4gK8KgwqDC oCBzdHJ1Y3QgcmVnbWFwICpyZWdtYXA7Cj4+ICt9Owo+PiArCj4+ICtzdHJ1Y3QgaW5nZW5pY19z b2NfaW5mbyB7Cj4+ICvCoMKgwqAgZW51bSBpbmdlbmljX21hY192ZXJzaW9uIHZlcnNpb247Cj4+ ICvCoMKgwqAgdTMyIG1hc2s7Cj4+ICsKPj4gK8KgwqDCoCBpbnQgKCpzZXRfbW9kZSkoc3RydWN0 IHBsYXRfc3RtbWFjZW5ldF9kYXRhICpwbGF0X2RhdCk7Cj4+ICvCoMKgwqAgaW50ICgqc3VzcGVu ZCkoc3RydWN0IGluZ2VuaWNfbWFjICptYWMpOwo+PiArwqDCoMKgIHZvaWQgKCpyZXN1bWUpKHN0 cnVjdCBpbmdlbmljX21hYyAqbWFjKTsKPgo+IFRoZXNlIHN1c3BlbmQvcmVzdW1lIGNhbGxiYWNr cyBhcmUgbm90IHVzZWQgYW55d2hlcmUgLSBqdXN0IGRyb3AgdGhlbS4KPgoKU3VyZS4KCgo+PiAr fTsKPj4gKwo+PiArc3RhdGljIGludCBpbmdlbmljX21hY19pbml0KHN0cnVjdCBwbGF0X3N0bW1h Y2VuZXRfZGF0YSAqcGxhdF9kYXQpCj4+ICt7Cj4+ICvCoMKgwqAgc3RydWN0IGluZ2VuaWNfbWFj ICptYWMgPSBwbGF0X2RhdC0+YnNwX3ByaXY7Cj4+ICvCoMKgwqAgaW50IHJldDsKPj4gKwo+PiAr wqDCoMKgIGlmIChtYWMtPnNvY19pbmZvLT5zZXRfbW9kZSkgewo+PiArwqDCoMKgwqDCoMKgwqAg cmV0ID0gbWFjLT5zb2NfaW5mby0+c2V0X21vZGUocGxhdF9kYXQpOwo+PiArwqDCoMKgwqDCoMKg wqAgaWYgKHJldCkKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJldDsKPj4gK8Kg wqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCByZXR1cm4gcmV0Owo+Cj4gWW91IGFyZSByZXR1cm5pbmcg YW4gdW5pbml0aWFsaXplZCB2YXJpYWJsZS4KPgoKU3VyZSwgSSdsbCBjaGFuZ2UgaXQgaW4gdGhl IG5leHQgdmVyc2lvbi4KCgo+PiArfQo+PiArCj4+ICtzdGF0aWMgaW50IGp6NDc3NV9tYWNfc2V0 X21vZGUoc3RydWN0IHBsYXRfc3RtbWFjZW5ldF9kYXRhICpwbGF0X2RhdCkKPj4gK3sKPj4gK8Kg wqDCoCBzdHJ1Y3QgaW5nZW5pY19tYWMgKm1hYyA9IHBsYXRfZGF0LT5ic3BfcHJpdjsKPj4gK8Kg wqDCoCBpbnQgdmFsOwo+Cj4gdW5zaWduZWQgaW50IHZhbDsKPgoKU3VyZS4KCgo+PiArCj4+ICvC oMKgwqAgc3dpdGNoIChwbGF0X2RhdC0+aW50ZXJmYWNlKSB7Cj4+ICvCoMKgwqAgY2FzZSBQSFlf SU5URVJGQUNFX01PREVfTUlJOgo+PiArwqDCoMKgwqDCoMKgwqAgdmFsID0gRklFTERfUFJFUChN QUNQSFlDX1RYQ0xLX1NFTF9NQVNLLCAKPj4gTUFDUEhZQ19UWENMS19TRUxfSU5QVVQpIHwKPj4g K8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIEZJRUxEX1BSRVAoTUFDUEhZQ19QSFlfSU5GVF9N QVNLLCBNQUNQSFlDX1BIWV9JTkZUX01JSSk7Cj4+ICvCoMKgwqDCoMKgwqDCoCBwcl9kZWJ1Zygi TUFDIFBIWSBDb250cm9sIFJlZ2lzdGVyOiBQSFlfSU5URVJGQUNFX01PREVfTUlJXG4iKTsKPgo+ IFVzZSBkZXZfZGJnKCkgd2l0aCBtYWMtPmRldiwgaW5zdGVhZCBvZiBwcl9kZWJ1ZygpLgo+Cj4g KFNhbWUgZm9yIGFsbCBwcl9kZWJ1ZygpIGNhbGxzIGJlbG93KQo+CgpTdXJlLgoKCj4+ICvCoMKg wqDCoMKgwqDCoCBicmVhazsKPj4gKwo+PiArwqDCoMKgIGNhc2UgUEhZX0lOVEVSRkFDRV9NT0RF X0dNSUk6Cj4+ICvCoMKgwqDCoMKgwqDCoCB2YWwgPSBGSUVMRF9QUkVQKE1BQ1BIWUNfVFhDTEtf U0VMX01BU0ssIAo+PiBNQUNQSFlDX1RYQ0xLX1NFTF9JTlBVVCkgfAo+PiArwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqAgRklFTERfUFJFUChNQUNQSFlDX1BIWV9JTkZUX01BU0ssIE1BQ1BIWUNf UEhZX0lORlRfR01JSSk7Cj4+ICvCoMKgwqDCoMKgwqDCoCBwcl9kZWJ1ZygiTUFDIFBIWSBDb250 cm9sIFJlZ2lzdGVyOiAKPj4gUEhZX0lOVEVSRkFDRV9NT0RFX0dNSUlcbiIpOwo+PiArwqDCoMKg wqDCoMKgwqAgYnJlYWs7Cj4+ICsKPj4gK8KgwqDCoCBjYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9S TUlJOgo+PiArwqDCoMKgwqDCoMKgwqAgdmFsID0gRklFTERfUFJFUChNQUNQSFlDX1RYQ0xLX1NF TF9NQVNLLCAKPj4gTUFDUEhZQ19UWENMS19TRUxfSU5QVVQpIHwKPj4gK8KgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgIEZJRUxEX1BSRVAoTUFDUEhZQ19QSFlfSU5GVF9NQVNLLCBNQUNQSFlDX1BI WV9JTkZUX1JNSUkpOwo+PiArwqDCoMKgwqDCoMKgwqAgcHJfZGVidWcoIk1BQyBQSFkgQ29udHJv bCBSZWdpc3RlcjogCj4+IFBIWV9JTlRFUkZBQ0VfTU9ERV9STUlJXG4iKTsKPj4gK8KgwqDCoMKg wqDCoMKgIGJyZWFrOwo+PiArCj4+ICvCoMKgwqAgY2FzZSBQSFlfSU5URVJGQUNFX01PREVfUkdN SUk6Cj4+ICvCoMKgwqDCoMKgwqDCoCB2YWwgPSBGSUVMRF9QUkVQKE1BQ1BIWUNfVFhDTEtfU0VM X01BU0ssIAo+PiBNQUNQSFlDX1RYQ0xLX1NFTF9JTlBVVCkgfAo+PiArwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgRklFTERfUFJFUChNQUNQSFlDX1BIWV9JTkZUX01BU0ssIAo+PiBNQUNQSFlD X1BIWV9JTkZUX1JHTUlJKTsKPj4gK8KgwqDCoMKgwqDCoMKgIHByX2RlYnVnKCJNQUMgUEhZIENv bnRyb2wgUmVnaXN0ZXI6IAo+PiBQSFlfSU5URVJGQUNFX01PREVfUkdNSUlcbiIpOwo+PiArwqDC oMKgwqDCoMKgwqAgYnJlYWs7Cj4+ICsKPj4gK8KgwqDCoCBkZWZhdWx0Ogo+PiArwqDCoMKgwqDC oMKgwqAgZGV2X2VycihtYWMtPmRldiwgInVuc3VwcG9ydGVkIGludGVyZmFjZSAlZCIsIAo+PiBw bGF0X2RhdC0+aW50ZXJmYWNlKTsKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAtRUlOVkFMOwo+ PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIC8qIFVwZGF0ZSBNQUMgUEhZIGNvbnRyb2wgcmVn aXN0ZXIgKi8KPj4gK8KgwqDCoCByZXR1cm4gcmVnbWFwX3VwZGF0ZV9iaXRzKG1hYy0+cmVnbWFw LCAwLCBtYWMtPnNvY19pbmZvLT5tYXNrLCAKPj4gdmFsKTsKPj4gK30KPj4gKwo+PiArc3RhdGlj IGludCB4MTAwMF9tYWNfc2V0X21vZGUoc3RydWN0IHBsYXRfc3RtbWFjZW5ldF9kYXRhICpwbGF0 X2RhdCkKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaW5nZW5pY19tYWMgKm1hYyA9IHBsYXRfZGF0 LT5ic3BfcHJpdjsKPj4gK8KgwqDCoCBpbnQgdmFsOwo+PiArCj4+ICvCoMKgwqAgc3dpdGNoIChw bGF0X2RhdC0+aW50ZXJmYWNlKSB7Cj4+ICvCoMKgwqAgY2FzZSBQSFlfSU5URVJGQUNFX01PREVf Uk1JSToKPj4gK8KgwqDCoMKgwqDCoMKgIHByX2RlYnVnKCJNQUMgUEhZIENvbnRyb2wgUmVnaXN0 ZXI6IAo+PiBQSFlfSU5URVJGQUNFX01PREVfUk1JSVxuIik7Cj4+ICvCoMKgwqDCoMKgwqDCoCBi cmVhazsKPj4gKwo+PiArwqDCoMKgIGRlZmF1bHQ6Cj4+ICvCoMKgwqDCoMKgwqDCoCBkZXZfZXJy KG1hYy0+ZGV2LCAidW5zdXBwb3J0ZWQgaW50ZXJmYWNlICVkIiwgCj4+IHBsYXRfZGF0LT5pbnRl cmZhY2UpOwo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIC1FSU5WQUw7Cj4+ICvCoMKgwqAgfQo+ PiArCj4+ICvCoMKgwqAgLyogVXBkYXRlIE1BQyBQSFkgY29udHJvbCByZWdpc3RlciAqLwo+PiAr wqDCoMKgIHJldHVybiByZWdtYXBfdXBkYXRlX2JpdHMobWFjLT5yZWdtYXAsIDAsIG1hYy0+c29j X2luZm8tPm1hc2ssIAo+PiB2YWwpOwo+Cj4gWW91J3JlIHBhc3NpbmcgJ3ZhbCcsIHdoaWNoIGlz IGFuIHVuaW5pdGlhbGl6ZWQgdmFyaWFibGUuCj4KCkkgd2lsbCBmaXggdGhpcyBpbnQgdGhlIG5l eHQgdmVyc2lvbi4KCgo+PiArfQo+PiArCj4+ICtzdGF0aWMgaW50IHgxNjAwX21hY19zZXRfbW9k ZShzdHJ1Y3QgcGxhdF9zdG1tYWNlbmV0X2RhdGEgKnBsYXRfZGF0KQo+PiArewo+PiArwqDCoMKg IHN0cnVjdCBpbmdlbmljX21hYyAqbWFjID0gcGxhdF9kYXQtPmJzcF9wcml2Owo+PiArwqDCoMKg IGludCB2YWw7Cj4KPiB1bnNpZ25lZCBpbnQgdmFsOwo+CgpTdXJlLgoKCj4+ICsKPj4gK8KgwqDC oCBzd2l0Y2ggKHBsYXRfZGF0LT5pbnRlcmZhY2UpIHsKPj4gK8KgwqDCoCBjYXNlIFBIWV9JTlRF UkZBQ0VfTU9ERV9STUlJOgo+PiArwqDCoMKgwqDCoMKgwqAgdmFsID0gRklFTERfUFJFUChNQUNQ SFlDX1BIWV9JTkZUX01BU0ssIE1BQ1BIWUNfUEhZX0lORlRfUk1JSSk7Cj4+ICvCoMKgwqDCoMKg wqDCoCBwcl9kZWJ1ZygiTUFDIFBIWSBDb250cm9sIFJlZ2lzdGVyOiAKPj4gUEhZX0lOVEVSRkFD RV9NT0RFX1JNSUlcbiIpOwo+PiArwqDCoMKgwqDCoMKgwqAgYnJlYWs7Cj4+ICsKPj4gK8KgwqDC oCBkZWZhdWx0Ogo+PiArwqDCoMKgwqDCoMKgwqAgZGV2X2VycihtYWMtPmRldiwgInVuc3VwcG9y dGVkIGludGVyZmFjZSAlZCIsIAo+PiBwbGF0X2RhdC0+aW50ZXJmYWNlKTsKPj4gK8KgwqDCoMKg wqDCoMKgIHJldHVybiAtRUlOVkFMOwo+PiArwqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIC8qIFVw ZGF0ZSBNQUMgUEhZIGNvbnRyb2wgcmVnaXN0ZXIgKi8KPj4gK8KgwqDCoCByZXR1cm4gcmVnbWFw X3VwZGF0ZV9iaXRzKG1hYy0+cmVnbWFwLCAwLCBtYWMtPnNvY19pbmZvLT5tYXNrLCAKPj4gdmFs KTsKPj4gK30KPj4gKwo+PiArc3RhdGljIGludCB4MTgzMF9tYWNfc2V0X21vZGUoc3RydWN0IHBs YXRfc3RtbWFjZW5ldF9kYXRhICpwbGF0X2RhdCkKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgaW5n ZW5pY19tYWMgKm1hYyA9IHBsYXRfZGF0LT5ic3BfcHJpdjsKPj4gK8KgwqDCoCBpbnQgdmFsOwo+ Cj4gU2FtZSBoZXJlLAo+CgpTdXJlLgoKCj4+ICsKPj4gK8KgwqDCoCBzd2l0Y2ggKHBsYXRfZGF0 LT5pbnRlcmZhY2UpIHsKPj4gK8KgwqDCoCBjYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9STUlJOgo+ PiArwqDCoMKgwqDCoMKgwqAgdmFsID0gRklFTERfUFJFUChNQUNQSFlDX01PREVfU0VMX01BU0ss IAo+PiBNQUNQSFlDX01PREVfU0VMX1JNSUkpIHwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIEZJRUxEX1BSRVAoTUFDUEhZQ19QSFlfSU5GVF9NQVNLLCBNQUNQSFlDX1BIWV9JTkZUX1JN SUkpOwo+PiArwqDCoMKgwqDCoMKgwqAgcHJfZGVidWcoIk1BQyBQSFkgQ29udHJvbCBSZWdpc3Rl cjogCj4+IFBIWV9JTlRFUkZBQ0VfTU9ERV9STUlJXG4iKTsKPj4gK8KgwqDCoMKgwqDCoMKgIGJy ZWFrOwo+PiArCj4+ICvCoMKgwqAgZGVmYXVsdDoKPj4gK8KgwqDCoMKgwqDCoMKgIGRldl9lcnIo bWFjLT5kZXYsICJ1bnN1cHBvcnRlZCBpbnRlcmZhY2UgJWQiLCAKPj4gcGxhdF9kYXQtPmludGVy ZmFjZSk7Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXR1cm4gLUVJTlZBTDsKPj4gK8KgwqDCoCB9Cj4+ ICsKPj4gK8KgwqDCoCAvKiBVcGRhdGUgTUFDIFBIWSBjb250cm9sIHJlZ2lzdGVyICovCj4+ICvC oMKgwqAgcmV0dXJuIHJlZ21hcF91cGRhdGVfYml0cyhtYWMtPnJlZ21hcCwgMCwgbWFjLT5zb2Nf aW5mby0+bWFzaywgCj4+IHZhbCk7Cj4+ICt9Cj4+ICsKPj4gK3N0YXRpYyBpbnQgeDIwMDBfbWFj X3NldF9tb2RlKHN0cnVjdCBwbGF0X3N0bW1hY2VuZXRfZGF0YSAqcGxhdF9kYXQpCj4+ICt7Cj4+ ICvCoMKgwqAgc3RydWN0IGluZ2VuaWNfbWFjICptYWMgPSBwbGF0X2RhdC0+YnNwX3ByaXY7Cj4+ ICvCoMKgwqAgaW50IHZhbDsKPgo+IFNhbWUgaGVyZS4KPgoKU3VyZS4KCgo+PiArCj4+ICvCoMKg wqAgc3dpdGNoIChwbGF0X2RhdC0+aW50ZXJmYWNlKSB7Cj4+ICvCoMKgwqAgY2FzZSBQSFlfSU5U RVJGQUNFX01PREVfUk1JSToKPj4gK8KgwqDCoMKgwqDCoMKgIHZhbCA9IEZJRUxEX1BSRVAoTUFD UEhZQ19UWF9TRUxfTUFTSywgTUFDUEhZQ19UWF9TRUxfT1JJR0lOKSB8Cj4+ICvCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqDCoCBGSUVMRF9QUkVQKE1BQ1BIWUNfUlhfU0VMX01BU0ssIE1BQ1BIWUNf UlhfU0VMX09SSUdJTikgfAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgRklFTERfUFJF UChNQUNQSFlDX1BIWV9JTkZUX01BU0ssIE1BQ1BIWUNfUEhZX0lORlRfUk1JSSk7Cj4+ICvCoMKg wqDCoMKgwqDCoCBwcl9kZWJ1ZygiTUFDIFBIWSBDb250cm9sIFJlZ2lzdGVyOiAKPj4gUEhZX0lO VEVSRkFDRV9NT0RFX1JNSUlcbiIpOwo+PiArwqDCoMKgwqDCoMKgwqAgYnJlYWs7Cj4+ICsKPj4g K8KgwqDCoCBjYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9SR01JSToKPj4gK8KgwqDCoMKgwqDCoMKg IHZhbCA9IEZJRUxEX1BSRVAoTUFDUEhZQ19UWF9TRUxfTUFTSywgTUFDUEhZQ19UWF9TRUxfREVM QVkpIHwKPj4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIEZJRUxEX1BSRVAoTUFDUEhZQ19U WF9ERUxBWV9NQVNLLCAKPj4gTUFDUEhZQ19UWF9ERUxBWV82M19VTklUKSB8Cj4+ICvCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoCBGSUVMRF9QUkVQKE1BQ1BIWUNfUlhfU0VMX01BU0ssIE1BQ1BI WUNfUlhfU0VMX09SSUdJTikgfAo+PiArwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgRklFTERf UFJFUChNQUNQSFlDX1BIWV9JTkZUX01BU0ssIAo+PiBNQUNQSFlDX1BIWV9JTkZUX1JHTUlJKTsK Pj4gK8KgwqDCoMKgwqDCoMKgIHByX2RlYnVnKCJNQUMgUEhZIENvbnRyb2wgUmVnaXN0ZXI6IAo+ PiBQSFlfSU5URVJGQUNFX01PREVfUkdNSUlcbiIpOwo+PiArwqDCoMKgwqDCoMKgwqAgYnJlYWs7 Cj4+ICsKPj4gK8KgwqDCoCBkZWZhdWx0Ogo+PiArwqDCoMKgwqDCoMKgwqAgZGV2X2VycihtYWMt PmRldiwgInVuc3VwcG9ydGVkIGludGVyZmFjZSAlZCIsIAo+PiBwbGF0X2RhdC0+aW50ZXJmYWNl KTsKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiAtRUlOVkFMOwo+PiArwqDCoMKgIH0KPj4gKwo+ PiArwqDCoMKgIC8qIFVwZGF0ZSBNQUMgUEhZIGNvbnRyb2wgcmVnaXN0ZXIgKi8KPj4gK8KgwqDC oCByZXR1cm4gcmVnbWFwX3VwZGF0ZV9iaXRzKG1hYy0+cmVnbWFwLCAwLCBtYWMtPnNvY19pbmZv LT5tYXNrLCAKPj4gdmFsKTsKPj4gK30KPj4gKwo+PiArc3RhdGljIGludCBpbmdlbmljX21hY19w cm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+PiArewo+PiArwqDCoMKgIHN0cnVj dCBwbGF0X3N0bW1hY2VuZXRfZGF0YSAqcGxhdF9kYXQ7Cj4+ICvCoMKgwqAgc3RydWN0IHN0bW1h Y19yZXNvdXJjZXMgc3RtbWFjX3JlczsKPj4gK8KgwqDCoCBzdHJ1Y3QgaW5nZW5pY19tYWMgKm1h YzsKPj4gK8KgwqDCoCBjb25zdCBzdHJ1Y3QgaW5nZW5pY19zb2NfaW5mbyAqZGF0YTsKPj4gK8Kg wqDCoCBpbnQgcmV0Owo+PiArCj4+ICvCoMKgwqAgcmV0ID0gc3RtbWFjX2dldF9wbGF0Zm9ybV9y ZXNvdXJjZXMocGRldiwgJnN0bW1hY19yZXMpOwo+PiArwqDCoMKgIGlmIChyZXQpCj4+ICvCoMKg wqDCoMKgwqDCoCByZXR1cm4gcmV0Owo+PiArCj4+ICvCoMKgwqAgcGxhdF9kYXQgPSBzdG1tYWNf cHJvYmVfY29uZmlnX2R0KHBkZXYsIHN0bW1hY19yZXMubWFjKTsKPj4gK8KgwqDCoCBpZiAoSVNf RVJSKHBsYXRfZGF0KSkKPj4gK8KgwqDCoMKgwqDCoMKgIHJldHVybiBQVFJfRVJSKHBsYXRfZGF0 KTsKPj4gKwo+PiArwqDCoMKgIG1hYyA9IGRldm1fa3phbGxvYygmcGRldi0+ZGV2LCBzaXplb2Yo Km1hYyksIEdGUF9LRVJORUwpOwo+PiArwqDCoMKgIGlmICghbWFjKSB7Cj4+ICvCoMKgwqDCoMKg wqDCoCByZXQgPSAtRU5PTUVNOwo+PiArwqDCoMKgwqDCoMKgwqAgZ290byBlcnJfcmVtb3ZlX2Nv bmZpZ19kdDsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDCoCBkYXRhID0gb2ZfZGV2aWNlX2dl dF9tYXRjaF9kYXRhKCZwZGV2LT5kZXYpOwo+PiArwqDCoMKgIGlmICghZGF0YSkgewo+PiArwqDC oMKgwqDCoMKgwqAgZGV2X2VycigmcGRldi0+ZGV2LCAibm8gb2YgbWF0Y2ggZGF0YSBwcm92aWRl ZFxuIik7Cj4+ICvCoMKgwqDCoMKgwqDCoCByZXQgPSAtRUlOVkFMOwo+PiArwqDCoMKgwqDCoMKg wqAgZ290byBlcnJfcmVtb3ZlX2NvbmZpZ19kdDsKPj4gK8KgwqDCoCB9Cj4+ICsKPj4gK8KgwqDC oCAvKiBHZXQgTUFDIFBIWSBjb250cm9sIHJlZ2lzdGVyICovCj4+ICvCoMKgwqAgbWFjLT5yZWdt YXAgPSBzeXNjb25fcmVnbWFwX2xvb2t1cF9ieV9waGFuZGxlKHBkZXYtPmRldi5vZl9ub2RlLCAK Pj4gIm1vZGUtcmVnIik7Cj4+ICvCoMKgwqAgaWYgKElTX0VSUihtYWMtPnJlZ21hcCkpIHsKPj4g K8KgwqDCoMKgwqDCoMKgIHByX2VycigiJXM6IGZhaWxlZCB0byBnZXQgc3lzY29uIHJlZ21hcFxu IiwgX19mdW5jX18pOwo+Cj4gZGV2X2Vycj8KPgoKU3VyZSwgSSB3aWxsIGNoYW5nZSB0aGlzIGlu IHYyLgoKCj4+ICvCoMKgwqDCoMKgwqDCoCBnb3RvIGVycl9yZW1vdmVfY29uZmlnX2R0Owo+PiAr wqDCoMKgIH0KPj4gKwo+PiArwqDCoMKgIG1hYy0+c29jX2luZm8gPSBkYXRhOwo+PiArwqDCoMKg IG1hYy0+ZGV2ID0gJnBkZXYtPmRldjsKPj4gKwo+PiArwqDCoMKgIHBsYXRfZGF0LT5ic3BfcHJp diA9IG1hYzsKPj4gKwo+PiArwqDCoMKgIHJldCA9IGluZ2VuaWNfbWFjX2luaXQocGxhdF9kYXQp Owo+PiArwqDCoMKgIGlmIChyZXQpCj4+ICvCoMKgwqDCoMKgwqDCoCBnb3RvIGVycl9yZW1vdmVf Y29uZmlnX2R0Owo+PiArCj4+ICvCoMKgwqAgcmV0ID0gc3RtbWFjX2R2cl9wcm9iZSgmcGRldi0+ ZGV2LCBwbGF0X2RhdCwgJnN0bW1hY19yZXMpOwo+PiArwqDCoMKgIGlmIChyZXQpCj4+ICvCoMKg wqDCoMKgwqDCoCBnb3RvIGVycl9yZW1vdmVfY29uZmlnX2R0Owo+PiArCj4+ICvCoMKgwqAgcmV0 dXJuIDA7Cj4+ICsKPj4gK2Vycl9yZW1vdmVfY29uZmlnX2R0Ogo+PiArwqDCoMKgIHN0bW1hY19y ZW1vdmVfY29uZmlnX2R0KHBkZXYsIHBsYXRfZGF0KTsKPj4gKwo+PiArwqDCoMKgIHJldHVybiBy ZXQ7Cj4+ICt9Cj4+ICsKPj4gKyNpZmRlZiBDT05GSUdfUE1fU0xFRVAKPgo+IFJlbW92ZSB0aGlz ICNpZmRlZi4KPgoKU3VyZS4KCgo+PiArc3RhdGljIGludCBpbmdlbmljX21hY19zdXNwZW5kKHN0 cnVjdCBkZXZpY2UgKmRldikKPj4gK3sKPj4gK8KgwqDCoCBzdHJ1Y3QgbmV0X2RldmljZSAqbmRl diA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwo+PiArwqDCoMKgIHN0cnVjdCBzdG1tYWNfcHJpdiAq cHJpdiA9IG5ldGRldl9wcml2KG5kZXYpOwo+PiArwqDCoMKgIHN0cnVjdCBpbmdlbmljX21hYyAq bWFjID0gcHJpdi0+cGxhdC0+YnNwX3ByaXY7Cj4+ICsKPj4gK8KgwqDCoCBpbnQgcmV0Owo+PiAr Cj4+ICvCoMKgwqAgcmV0ID0gc3RtbWFjX3N1c3BlbmQoZGV2KTsKPj4gKwo+PiArwqDCoMKgIGlm IChtYWMtPnNvY19pbmZvLT5zdXNwZW5kKQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0ID0gbWFjLT5z b2NfaW5mby0+c3VzcGVuZChtYWMpOwo+PiArCj4+ICvCoMKgwqAgcmV0dXJuIHJldDsKPj4gK30K Pj4gKwo+PiArc3RhdGljIGludCBpbmdlbmljX21hY19yZXN1bWUoc3RydWN0IGRldmljZSAqZGV2 KQo+PiArewo+PiArwqDCoMKgIHN0cnVjdCBuZXRfZGV2aWNlICpuZGV2ID0gZGV2X2dldF9kcnZk YXRhKGRldik7Cj4+ICvCoMKgwqAgc3RydWN0IHN0bW1hY19wcml2ICpwcml2ID0gbmV0ZGV2X3By aXYobmRldik7Cj4+ICvCoMKgwqAgc3RydWN0IGluZ2VuaWNfbWFjICptYWMgPSBwcml2LT5wbGF0 LT5ic3BfcHJpdjsKPj4gK8KgwqDCoCBpbnQgcmV0Owo+PiArCj4+ICvCoMKgwqAgaWYgKG1hYy0+ c29jX2luZm8tPnJlc3VtZSkKPj4gK8KgwqDCoMKgwqDCoMKgIG1hYy0+c29jX2luZm8tPnJlc3Vt ZShtYWMpOwo+PiArCj4+ICvCoMKgwqAgcmV0ID0gaW5nZW5pY19tYWNfaW5pdChwcml2LT5wbGF0 KTsKPj4gK8KgwqDCoCBpZiAocmV0KQo+PiArwqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJldDsKPj4g Kwo+PiArwqDCoMKgIHJldCA9IHN0bW1hY19yZXN1bWUoZGV2KTsKPj4gKwo+PiArwqDCoMKgIHJl dHVybiByZXQ7Cj4+ICt9Cj4+ICsjZW5kaWYgLyogQ09ORklHX1BNX1NMRUVQICovCj4+ICsKPj4g K3N0YXRpYyBTSU1QTEVfREVWX1BNX09QUyhpbmdlbmljX21hY19wbV9vcHMsCj4+ICvCoMKgwqAg aW5nZW5pY19tYWNfc3VzcGVuZCwgaW5nZW5pY19tYWNfcmVzdW1lKTsKPj4gKwo+PiArc3RhdGlj IHN0cnVjdCBpbmdlbmljX3NvY19pbmZvIGp6NDc3NV9zb2NfaW5mbyA9IHsKPj4gK8KgwqDCoCAu dmVyc2lvbiA9IElEX0paNDc3NSwKPj4gK8KgwqDCoCAubWFzayA9IE1BQ1BIWUNfVFhDTEtfU0VM X01BU0sgfCBNQUNQSFlDX1NPRlRfUlNUX01BU0sgfCAKPj4gTUFDUEhZQ19QSFlfSU5GVF9NQVNL LAo+PiArCj4+ICvCoMKgwqAgLnNldF9tb2RlID0gano0Nzc1X21hY19zZXRfbW9kZSwKPj4gK307 Cj4+ICsKPj4gK3N0YXRpYyBzdHJ1Y3QgaW5nZW5pY19zb2NfaW5mbyB4MTAwMF9zb2NfaW5mbyA9 IHsKPj4gK8KgwqDCoCAudmVyc2lvbiA9IElEX1gxMDAwLAo+PiArwqDCoMKgIC5tYXNrID0gTUFD UEhZQ19TT0ZUX1JTVF9NQVNLLAo+PiArCj4+ICvCoMKgwqAgLnNldF9tb2RlID0geDEwMDBfbWFj X3NldF9tb2RlLAo+PiArfTsKPj4gKwo+PiArc3RhdGljIHN0cnVjdCBpbmdlbmljX3NvY19pbmZv IHgxNjAwX3NvY19pbmZvID0gewo+PiArwqDCoMKgIC52ZXJzaW9uID0gSURfWDE2MDAsCj4+ICvC oMKgwqAgLm1hc2sgPSBNQUNQSFlDX1NPRlRfUlNUX01BU0sgfCBNQUNQSFlDX1BIWV9JTkZUX01B U0ssCj4+ICsKPj4gK8KgwqDCoCAuc2V0X21vZGUgPSB4MTYwMF9tYWNfc2V0X21vZGUsCj4+ICt9 Owo+PiArCj4+ICtzdGF0aWMgc3RydWN0IGluZ2VuaWNfc29jX2luZm8geDE4MzBfc29jX2luZm8g PSB7Cj4+ICvCoMKgwqAgLnZlcnNpb24gPSBJRF9YMTgzMCwKPj4gK8KgwqDCoCAubWFzayA9IE1B Q1BIWUNfTU9ERV9TRUxfTUFTSyB8IE1BQ1BIWUNfU09GVF9SU1RfTUFTSyB8IAo+PiBNQUNQSFlD X1BIWV9JTkZUX01BU0ssCj4+ICsKPj4gK8KgwqDCoCAuc2V0X21vZGUgPSB4MTgzMF9tYWNfc2V0 X21vZGUsCj4+ICt9Owo+PiArCj4+ICtzdGF0aWMgc3RydWN0IGluZ2VuaWNfc29jX2luZm8geDIw MDBfc29jX2luZm8gPSB7Cj4+ICvCoMKgwqAgLnZlcnNpb24gPSBJRF9YMjAwMCwKPj4gK8KgwqDC oCAubWFzayA9IE1BQ1BIWUNfVFhfU0VMX01BU0sgfCBNQUNQSFlDX1RYX0RFTEFZX01BU0sgfCAK Pj4gTUFDUEhZQ19SWF9TRUxfTUFTSyB8Cj4+ICvCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIE1BQ1BI WUNfUlhfREVMQVlfTUFTSyB8IE1BQ1BIWUNfU09GVF9SU1RfTUFTSyB8IAo+PiBNQUNQSFlDX1BI WV9JTkZUX01BU0ssCj4+ICsKPj4gK8KgwqDCoCAuc2V0X21vZGUgPSB4MjAwMF9tYWNfc2V0X21v ZGUsCj4+ICt9Owo+PiArCj4+ICtzdGF0aWMgY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCBpbmdl bmljX21hY19vZl9tYXRjaGVzW10gPSB7Cj4+ICvCoMKgwqAgeyAuY29tcGF0aWJsZSA9ICJpbmdl bmljLGp6NDc3NS1tYWMiLCAuZGF0YSA9ICZqejQ3NzVfc29jX2luZm8gfSwKPj4gK8KgwqDCoCB7 IC5jb21wYXRpYmxlID0gImluZ2VuaWMseDEwMDAtbWFjIiwgLmRhdGEgPSAmeDEwMDBfc29jX2lu Zm8gfSwKPj4gK8KgwqDCoCB7IC5jb21wYXRpYmxlID0gImluZ2VuaWMseDE2MDAtbWFjIiwgLmRh dGEgPSAmeDE2MDBfc29jX2luZm8gfSwKPj4gK8KgwqDCoCB7IC5jb21wYXRpYmxlID0gImluZ2Vu aWMseDE4MzAtbWFjIiwgLmRhdGEgPSAmeDE4MzBfc29jX2luZm8gfSwKPj4gK8KgwqDCoCB7IC5j b21wYXRpYmxlID0gImluZ2VuaWMseDIwMDAtbWFjIiwgLmRhdGEgPSAmeDIwMDBfc29jX2luZm8g fSwKPj4gK8KgwqDCoCB7IH0KPj4gK307Cj4+ICtNT0RVTEVfREVWSUNFX1RBQkxFKG9mLCBpbmdl bmljX21hY19vZl9tYXRjaGVzKTsKPj4gKwo+PiArc3RhdGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2 ZXIgaW5nZW5pY19tYWNfZHJpdmVyID0gewo+PiArwqDCoMKgIC5wcm9iZcKgwqDCoMKgwqDCoMKg ID0gaW5nZW5pY19tYWNfcHJvYmUsCj4+ICvCoMKgwqAgLnJlbW92ZcKgwqDCoMKgwqDCoMKgID0g c3RtbWFjX3BsdGZyX3JlbW92ZSwKPj4gK8KgwqDCoCAuZHJpdmVywqDCoMKgwqDCoMKgwqAgPSB7 Cj4+ICvCoMKgwqDCoMKgwqDCoCAubmFtZcKgwqDCoCA9ICJpbmdlbmljLW1hYyIsCj4+ICvCoMKg wqDCoMKgwqDCoCAucG3CoMKgwqDCoMKgwqDCoCA9ICZpbmdlbmljX21hY19wbV9vcHMsCj4KPiAu cG0gPSBwbV9wdHIoJmluZ2VuaWNfbWFjX3BtX29wcyksCj4KClN1cmUuCgoKVGhhbmtzIGFuZCBi ZXN0IHJlZ2FyZHMhCgoKPj4gK8KgwqDCoMKgwqDCoMKgIC5vZl9tYXRjaF90YWJsZSA9IGluZ2Vu aWNfbWFjX29mX21hdGNoZXMsCj4+ICvCoMKgwqAgfSwKPj4gK307Cj4+ICttb2R1bGVfcGxhdGZv cm1fZHJpdmVyKGluZ2VuaWNfbWFjX2RyaXZlcik7Cj4+ICsKPj4gK01PRFVMRV9BVVRIT1IoIuWR qOeQsOadsCAoWmhvdSBZYW5qaWUpIDx6aG91eWFuamllQHdhbnllZXRlY2guY29tPiIpOwo+PiAr TU9EVUxFX0RFU0NSSVBUSU9OKCJJbmdlbmljIFNvQ3MgRFdNQUMgc3BlY2lmaWMgZ2x1ZSBsYXll ciIpOwo+PiArTU9EVUxFX0xJQ0VOU0UoIkdQTCB2MiIpOwo+PiAtLSAKPj4gMi43LjQKPj4KPgo+ IENoZWVycywKPiAtUGF1bAo+CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVs QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9s aXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==