From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932177AbbJMBWC (ORCPT ); Mon, 12 Oct 2015 21:22:02 -0400 Received: from lucky1.263xmail.com ([211.157.147.132]:40533 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752009AbbJMBV7 (ORCPT ); Mon, 12 Oct 2015 21:21:59 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: linux-arm-kernel@lists.infradead.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <8c197d8ef73088fd89c08012b3b17c9e> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <561C5CA5.1030403@rock-chips.com> Date: Tue, 13 Oct 2015 09:21:41 +0800 From: Yakir Yang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Kishon Vijay Abraham I , Inki Dae , Andrzej Hajda , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Jingoo Han , Thierry Reding , Krzysztof Kozlowski , Rob Herring , joe@perches.com, Heiko Stuebner , Mark Yao CC: Russell King , djkurtz@chromium.org, dianders@chromium.org, Sean Paul , Kukjin Kim , Kumar Gala , emil.l.velikov@gmail.com, Ian Campbell , Gustavo Padovan , Pawel Moll , ajaynumb@gmail.com, robherring2@gmail.com, javier@osg.samsung.com, Andy Yan , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy References: <1444491357-26095-1-git-send-email-ykk@rock-chips.com> <1444492695-27241-1-git-send-email-ykk@rock-chips.com> <561C3410.8090600@ti.com> In-Reply-To: <561C3410.8090600@ti.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Kishon, On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote: > Hi, > > On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote: >> This phy driver is binded with the Rockchip DisplayPort >> driver, here are the brief properties: >> edp_phy: edp-phy@ff770274 { >> compatible = "rockchip,rk3288-dp-phy"; >> rockchip,grf = <&grf>; >> clocks = <&cru SCLK_EDP_24M>; >> clock-names = "24m"; >> #phy-cells = <0>; >> }; > The commit message can simply be "Add dt binding documentation for > rockchip display port PHY". Okay, thanks. - Yakir > > Thanks > Kishon > >> Signed-off-by: Yakir Yang >> --- >> Changes in v6: None >> Changes in v5: >> - Split binding doc's from driver changes. (Rob) >> - Update the rockchip,grf explain in document, and correct the clock required >> elemets in document. (Rob & Heiko) >> >> Changes in v4: None >> Changes in v3: None >> Changes in v2: None >> >> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> new file mode 100644 >> index 0000000..505194e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> @@ -0,0 +1,22 @@ >> +Rockchip Soc Seroes Display Port PHY >> +------------------------------------ >> + >> +Required properties: >> +- compatible : should be one of the following supported values: >> + - "rockchip.rk3288-dp-phy" >> +- clocks: from common clock binding: handle to dp clock. >> + of memory mapped region. >> +- clock-names: from common clock binding: >> + Required elements: "24m" >> +- rockchip,grf: phandle to the syscon managing the "general register files" >> +- #phy-cells : from the generic PHY bindings, must be 0; >> + >> +Example: >> + >> +edp_phy: edp-phy@ff770274 { >> + compatible = "rockchip,rk3288-dp-phy"; >> + rockchip,grf = <&grf>; >> + clocks = <&cru SCLK_EDP_24M>; >> + clock-names = "24m"; >> + #phy-cells = <0>; >> +}; >> > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: ykk@rock-chips.com (Yakir Yang) Date: Tue, 13 Oct 2015 09:21:41 +0800 Subject: [PATCH v6 11/17] Documentation: phy: add document for rockchip dp phy In-Reply-To: <561C3410.8090600@ti.com> References: <1444491357-26095-1-git-send-email-ykk@rock-chips.com> <1444492695-27241-1-git-send-email-ykk@rock-chips.com> <561C3410.8090600@ti.com> Message-ID: <561C5CA5.1030403@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Kishon, On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote: > Hi, > > On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote: >> This phy driver is binded with the Rockchip DisplayPort >> driver, here are the brief properties: >> edp_phy: edp-phy at ff770274 { >> compatible = "rockchip,rk3288-dp-phy"; >> rockchip,grf = <&grf>; >> clocks = <&cru SCLK_EDP_24M>; >> clock-names = "24m"; >> #phy-cells = <0>; >> }; > The commit message can simply be "Add dt binding documentation for > rockchip display port PHY". Okay, thanks. - Yakir > > Thanks > Kishon > >> Signed-off-by: Yakir Yang >> --- >> Changes in v6: None >> Changes in v5: >> - Split binding doc's from driver changes. (Rob) >> - Update the rockchip,grf explain in document, and correct the clock required >> elemets in document. (Rob & Heiko) >> >> Changes in v4: None >> Changes in v3: None >> Changes in v2: None >> >> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> new file mode 100644 >> index 0000000..505194e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt >> @@ -0,0 +1,22 @@ >> +Rockchip Soc Seroes Display Port PHY >> +------------------------------------ >> + >> +Required properties: >> +- compatible : should be one of the following supported values: >> + - "rockchip.rk3288-dp-phy" >> +- clocks: from common clock binding: handle to dp clock. >> + of memory mapped region. >> +- clock-names: from common clock binding: >> + Required elements: "24m" >> +- rockchip,grf: phandle to the syscon managing the "general register files" >> +- #phy-cells : from the generic PHY bindings, must be 0; >> + >> +Example: >> + >> +edp_phy: edp-phy at ff770274 { >> + compatible = "rockchip,rk3288-dp-phy"; >> + rockchip,grf = <&grf>; >> + clocks = <&cru SCLK_EDP_24M>; >> + clock-names = "24m"; >> + #phy-cells = <0>; >> +}; >> > >