From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932287AbbJMC2r (ORCPT ); Mon, 12 Oct 2015 22:28:47 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:41633 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751039AbbJMC2o (ORCPT ); Mon, 12 Oct 2015 22:28:44 -0400 X-AuditID: cbfee691-f79d66d000001509-a4-561c6c5a4b8b Message-id: <561C6C5A.7090806@samsung.com> Date: Tue, 13 Oct 2015 11:28:42 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-version: 1.0 To: Krzysztof Kozlowski , Anand Moon Cc: k.kozlowski.k@gmail.com, Kukjin Kim , Javier Martinez Canillas , Lukasz Majewski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-samsung-soc@vger.kernel.org" , Linux Kernel Subject: Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> <561BAAB1.4020203@samsung.com> <561BAFDF.2090501@samsung.com> <561BB29E.6090109@samsung.com> In-reply-to: <561BB29E.6090109@samsung.com> Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEIsWRmVeSWpSXmKPExsWyRsSkUDcqRybM4G2/usX8I+dYLd68XcNk 8fzfD3aL1y8MLfofv2a2ePNwM6PFpsfXWC0u75rDZjHj/D4mi3Ubb7E7cHnsnHWX3WPTqk42 j81L6j229AN5fVtWMXp83iQXwBbFZZOSmpNZllqkb5fAlXHj5Se2gvN6Fe8ObmRrYFyu2sXI wSEhYCLROKW+i5ETyBSTuHBvPVsXIxeHkMAKRom/iz8zQiRMJOb+vsAIkVjKKPF6bQuU84BR omVGP1gVr4CWRNeyeawgNouAqsSjBRPBbDYBHYnt344zgdiiAmESD9btZYWoF5T4MfkeC4gt IhAu8WHSVVaQocwCN5kknvU+ZwU5T1ggQuLEVSOQGiGBE0wS7VsFQGxOAW2JRRPWMoOUMAuo S0yZkgsSZhaQl9i85i0zxNEf2SUmvdGHOEdA4tvkQywQD8tKbDoAVSIpcXDFDZYJjGKzkBw0 C2HoLCRDFzAyr2IUTS1ILihOSi8y1StOzC0uzUvXS87P3cQIjMrT/55N3MF4/4D1IUYBDkYl Ht4XkTJhQqyJZcWVuYcYTYGOmMgsJZqcD4z9vJJ4Q2MzIwtTE1NjI3NLMyVxXh3pn8FCAumJ JanZqakFqUXxRaU5qcWHGJk4OKUaGJ3LrCyVOQ+ZXG7qrPfRn/QlwP/kh3QZ3iMF3LI/Nx9a NelJ4OINFxnkpDOW29l/2cZYpRX6tuXmtShjzpKL0nPC2aZOiA50eec+7UOThG387HvT984/ YLi8wO1Kzk7h0McHrxqte9ltt7w4//fnF/nfmIq/L3xS46Qhcp/9v+8+Zcc4MYUvCUosxRmJ hlrMRcWJAH5L9OvFAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpkleLIzCtJLcpLzFFi42I5/e+xgG5UjkyYwYxeRYv5R86xWrx5u4bJ 4vm/H+wWr18YWvQ/fs1s8ebhZkaLTY+vsVpc3jWHzWLG+X1MFus23mJ34PLYOesuu8emVZ1s HpuX1Hts6Qfy+rasYvT4vEkugC2qgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLC XEkhLzE31VbJxSdA1y0zB+gyJYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBh DWPGjZef2ArO61W8O7iRrYFxuWoXIyeHhICJxNzfFxghbDGJC/fWs3UxcnEICSxllHi9toUR wnnAKNEyox+sildAS6Jr2TxWEJtFQFXi0YKJYDabgI7E9m/HmUBsUYEwiQfr9rJC1AtK/Jh8 jwXEFhEIl/gw6SoryFBmgZtMEs96nwM5HBzCAhESJ64agdQICZxgkmjfKgBicwpoSyyasJYZ pIRZQF1iypRckDCzgLzE5jVvmScwCsxCsmEWQtUsJFULGJlXMUqkFiQXFCel5xrmpZbrFSfm Fpfmpesl5+duYgRH/zOpHYwHd7kfYhTgYFTi4X0RKRMmxJpYVlyZe4hRgoNZSYT3XBZQiDcl sbIqtSg/vqg0J7X4EKMpMAgmMkuJJucDE1NeSbyhsYmZkaWRuaGFkbG5kjjvjUMMYUIC6Ykl qdmpqQWpRTB9TBycUg2MXBrCWfxrV7+M9tLuerit/pjXO4scpYp/B+5MenLlFG+eTZok594t 01JPOB9trYxfkGBadqBd02tfG8e7w60+9y5Fzpn8YVrBCb+IJ40n3ihtzHSe75S8k6sg1Wa6 6VQ/ntfndp/c+7jt9OtDtbHqn9cHzL18wIvlsrzsx3A36dkvQlyf8ycHKbEUZyQaajEXFScC AMkvRI8UAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/12/2015 10:16 PM, Krzysztof Kozlowski wrote: > W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze: >> On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote: >>> W dniu 12.10.2015 o 19:46, Anand Moon pisze: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>> Looks like I missed it, I will add this in the next patch, >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>> >>> That part was not answered... >> >> In my experiment, it needs two requirements. >> One is that Host controller supported UHS-I mode or others, other is SD-card. >> In Anand's commit message, there is no information for this. >> >> And 50MB/s or 104MB/s is not real performance. (Just theoretical values) >> It seems that can get those performances. > > Right. But do you know if the host actually supports these? Actually, it needs to check the User Manual for SoC. If i can't check the User manual, i can't also know whether it supports or not. Especially, there is no register that can be known which SD specification version at dw-mmc controller. Well, if i miss something, let me know. I will also check more. Best Regards, Jaehoon Chung > >> >>> >>>>> >>>> >>>>>> >>>>>> Signed-off-by: Anand Moon >>>>>> >>>>>> --- >>>>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>>>> >>>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>>>> >>>>> I don't get what is exactly fixed here. What was the error? What is the >>>>> outcome of this fix? The log below is before or after? >>>>> >>>>> Best regards, >>>>> Krzysztof >>>>> >>>>>> >>>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>>> [ 2.461743] mmcblk0: p1 p2 >>>>> >>>>>> --- >>>>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>>>> 1 file changed, 4 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> index 58c06d3..ba4a87b 100644 >>>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> @@ -364,6 +364,10 @@ >>>>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>>>> bus-width = <4>; >>>>>> cap-sd-highspeed; >>>>>> + sd-uhs-sdr12; >>>>>> + sd-uhs-sdr25; >>>>>> + sd-uhs-sdr50; >>>>>> + sd-uhs-sdr104; >>>>>> }; >>>>>> >>>>>> &pinctrl_0 { >>>>>> >>>>> >>>> >>>> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >>>> OdroidXU3/XU4 board would not boot up using this card. >>>> >>>> Depending on the capability of the UHS-I card, the speed of the card >>>> is selected. >>>> I have just added the enhance capability feature to support them. >>> >>> So without these capabilities mentioned microSD card cannot be used? So >>> I have a UHS-I card, that one exactly: >>> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC >>> >>> It works: >>> [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req >>> 50000000Hz, actual 50000000HZ div = 0) >>> [ 2.693296] mmc1: new high speed SDHC card at address 0001 >>> [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB >>> [ 2.708406] mmcblk0: p1 p2 >>> >>> This is just HS mode. >>> >>> In the same time isn't UHS-I backward compatible? Your report seems >>> surprising. >> >> Right. it's not issue. just working as lower mode than its capability. > > Anand's report mentions "board would not boot up" which seems quite > drastic. :) > > Thanks Jaehoon for help in reviewing this patch. > > > Dear Anand, > > Could you describe in more details observable issues, what is fixed or > what feature is added? > > Best regards, > Krzysztof > >> >> Best Regards, >> Jaehoon Chung >> >>> >>> Best regards, >>> Krzysztof >>> >>>> >>>> On warm boot: i.e reboot of the board. >>>> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >>>> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.669206] mmcblk0: p1 p2 >>>> >>>> On cold boot:: ie: power on the board. >>>> >>>> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>>> req 100000000Hz, actual 100000000HZ div = 0) >>>> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.650293] IRQ56 no longer affine to CPU7 >>>> [ 4.650581] CPU7: shutdown >>>> [ 4.658293] mmcblk0: p1 p2 >>>> >>>> Note: Their is need to reset the PMIC >>>> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >>>> to support this feature consistently on every reboot. >>>> >>>> -Anand Moon >>>> -- >>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >>>> the body of a message to majordomo@vger.kernel.org >>>> More majordomo info at http://vger.kernel.org/majordomo-info.html >>>> Please read the FAQ at http://www.tux.org/lkml/ >>>> >>> >>> >> > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Subject: Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support Date: Tue, 13 Oct 2015 11:28:42 +0900 Message-ID: <561C6C5A.7090806@samsung.com> References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> <561BAAB1.4020203@samsung.com> <561BAFDF.2090501@samsung.com> <561BB29E.6090109@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-reply-to: <561BB29E.6090109@samsung.com> Sender: linux-kernel-owner@vger.kernel.org To: Krzysztof Kozlowski , Anand Moon Cc: k.kozlowski.k@gmail.com, Kukjin Kim , Javier Martinez Canillas , Lukasz Majewski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-samsung-soc@vger.kernel.org" , Linux Kernel List-Id: devicetree@vger.kernel.org On 10/12/2015 10:16 PM, Krzysztof Kozlowski wrote: > W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze: >> On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote: >>> W dniu 12.10.2015 o 19:46, Anand Moon pisze: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>> Looks like I missed it, I will add this in the next patch, >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>> >>> That part was not answered... >> >> In my experiment, it needs two requirements. >> One is that Host controller supported UHS-I mode or others, other is SD-card. >> In Anand's commit message, there is no information for this. >> >> And 50MB/s or 104MB/s is not real performance. (Just theoretical values) >> It seems that can get those performances. > > Right. But do you know if the host actually supports these? Actually, it needs to check the User Manual for SoC. If i can't check the User manual, i can't also know whether it supports or not. Especially, there is no register that can be known which SD specification version at dw-mmc controller. Well, if i miss something, let me know. I will also check more. Best Regards, Jaehoon Chung > >> >>> >>>>> >>>> >>>>>> >>>>>> Signed-off-by: Anand Moon >>>>>> >>>>>> --- >>>>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>>>> >>>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>>>> >>>>> I don't get what is exactly fixed here. What was the error? What is the >>>>> outcome of this fix? The log below is before or after? >>>>> >>>>> Best regards, >>>>> Krzysztof >>>>> >>>>>> >>>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>>> [ 2.461743] mmcblk0: p1 p2 >>>>> >>>>>> --- >>>>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>>>> 1 file changed, 4 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> index 58c06d3..ba4a87b 100644 >>>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> @@ -364,6 +364,10 @@ >>>>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>>>> bus-width = <4>; >>>>>> cap-sd-highspeed; >>>>>> + sd-uhs-sdr12; >>>>>> + sd-uhs-sdr25; >>>>>> + sd-uhs-sdr50; >>>>>> + sd-uhs-sdr104; >>>>>> }; >>>>>> >>>>>> &pinctrl_0 { >>>>>> >>>>> >>>> >>>> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >>>> OdroidXU3/XU4 board would not boot up using this card. >>>> >>>> Depending on the capability of the UHS-I card, the speed of the card >>>> is selected. >>>> I have just added the enhance capability feature to support them. >>> >>> So without these capabilities mentioned microSD card cannot be used? So >>> I have a UHS-I card, that one exactly: >>> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC >>> >>> It works: >>> [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req >>> 50000000Hz, actual 50000000HZ div = 0) >>> [ 2.693296] mmc1: new high speed SDHC card at address 0001 >>> [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB >>> [ 2.708406] mmcblk0: p1 p2 >>> >>> This is just HS mode. >>> >>> In the same time isn't UHS-I backward compatible? Your report seems >>> surprising. >> >> Right. it's not issue. just working as lower mode than its capability. > > Anand's report mentions "board would not boot up" which seems quite > drastic. :) > > Thanks Jaehoon for help in reviewing this patch. > > > Dear Anand, > > Could you describe in more details observable issues, what is fixed or > what feature is added? > > Best regards, > Krzysztof > >> >> Best Regards, >> Jaehoon Chung >> >>> >>> Best regards, >>> Krzysztof >>> >>>> >>>> On warm boot: i.e reboot of the board. >>>> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >>>> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.669206] mmcblk0: p1 p2 >>>> >>>> On cold boot:: ie: power on the board. >>>> >>>> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>>> req 100000000Hz, actual 100000000HZ div = 0) >>>> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.650293] IRQ56 no longer affine to CPU7 >>>> [ 4.650581] CPU7: shutdown >>>> [ 4.658293] mmcblk0: p1 p2 >>>> >>>> Note: Their is need to reset the PMIC >>>> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >>>> to support this feature consistently on every reboot. >>>> >>>> -Anand Moon >>>> -- >>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >>>> the body of a message to majordomo@vger.kernel.org >>>> More majordomo info at http://vger.kernel.org/majordomo-info.html >>>> Please read the FAQ at http://www.tux.org/lkml/ >>>> >>> >>> >> > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: jh80.chung@samsung.com (Jaehoon Chung) Date: Tue, 13 Oct 2015 11:28:42 +0900 Subject: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support In-Reply-To: <561BB29E.6090109@samsung.com> References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> <561BAAB1.4020203@samsung.com> <561BAFDF.2090501@samsung.com> <561BB29E.6090109@samsung.com> Message-ID: <561C6C5A.7090806@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 10/12/2015 10:16 PM, Krzysztof Kozlowski wrote: > W dniu 12.10.2015 o 22:04, Jaehoon Chung pisze: >> On 10/12/2015 09:42 PM, Krzysztof Kozlowski wrote: >>> W dniu 12.10.2015 o 19:46, Anand Moon pisze: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>> Looks like I missed it, I will add this in the next patch, >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>> >>> That part was not answered... >> >> In my experiment, it needs two requirements. >> One is that Host controller supported UHS-I mode or others, other is SD-card. >> In Anand's commit message, there is no information for this. >> >> And 50MB/s or 104MB/s is not real performance. (Just theoretical values) >> It seems that can get those performances. > > Right. But do you know if the host actually supports these? Actually, it needs to check the User Manual for SoC. If i can't check the User manual, i can't also know whether it supports or not. Especially, there is no register that can be known which SD specification version at dw-mmc controller. Well, if i miss something, let me know. I will also check more. Best Regards, Jaehoon Chung > >> >>> >>>>> >>>> >>>>>> >>>>>> Signed-off-by: Anand Moon >>>>>> >>>>>> --- >>>>>> Changes based on git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git v4.4-next/dt-samsung branch >>>>>> >>>>>> Changes Fixed the UHS-I bus speed detedtion on cold boot. >>>>> >>>>> I don't get what is exactly fixed here. What was the error? What is the >>>>> outcome of this fix? The log below is before or after? >>>>> >>>>> Best regards, >>>>> Krzysztof >>>>> >>>>>> >>>>>> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req 100000000Hz, actual 100000000HZ div = 0) >>>>>> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>>>> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>>>> [ 2.461743] mmcblk0: p1 p2 >>>>> >>>>>> --- >>>>>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ >>>>>> 1 file changed, 4 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> index 58c06d3..ba4a87b 100644 >>>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>>>>> @@ -364,6 +364,10 @@ >>>>>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; >>>>>> bus-width = <4>; >>>>>> cap-sd-highspeed; >>>>>> + sd-uhs-sdr12; >>>>>> + sd-uhs-sdr25; >>>>>> + sd-uhs-sdr50; >>>>>> + sd-uhs-sdr104; >>>>>> }; >>>>>> >>>>>> &pinctrl_0 { >>>>>> >>>>> >>>> >>>> Changes were made to support Sandisk Ultra UHS-I class 10 card support. >>>> OdroidXU3/XU4 board would not boot up using this card. >>>> >>>> Depending on the capability of the UHS-I card, the speed of the card >>>> is selected. >>>> I have just added the enhance capability feature to support them. >>> >>> So without these capabilities mentioned microSD card cannot be used? So >>> I have a UHS-I card, that one exactly: >>> http://www.samsung.com/us/support/owners/product/MB-MP32D/APC >>> >>> It works: >>> [ 2.628365] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req >>> 50000000Hz, actual 50000000HZ div = 0) >>> [ 2.693296] mmc1: new high speed SDHC card at address 0001 >>> [ 2.703867] mmcblk0: mmc1:0001 00000 29.8 GiB >>> [ 2.708406] mmcblk0: p1 p2 >>> >>> This is just HS mode. >>> >>> In the same time isn't UHS-I backward compatible? Your report seems >>> surprising. >> >> Right. it's not issue. just working as lower mode than its capability. > > Anand's report mentions "board would not boot up" which seems quite > drastic. :) > > Thanks Jaehoon for help in reviewing this patch. > > > Dear Anand, > > Could you describe in more details observable issues, what is fixed or > what feature is added? > > Best regards, > Krzysztof > >> >> Best Regards, >> Jaehoon Chung >> >>> >>> Best regards, >>> Krzysztof >>> >>>> >>>> On warm boot: i.e reboot of the board. >>>> [ 4.649073] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >>>> req 50000000Hz, actual 50000000HZ div = 0) >>>> [ 4.657555] mmc1: new high speed SDHC card at address aaaa >>>> [ 4.663787] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.669206] mmcblk0: p1 p2 >>>> >>>> On cold boot:: ie: power on the board. >>>> >>>> [ 4.630237] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot >>>> req 100000000Hz, actual 100000000HZ div = 0) >>>> [ 4.639820] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >>>> [ 4.646266] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >>>> [ 4.650293] IRQ56 no longer affine to CPU7 >>>> [ 4.650581] CPU7: shutdown >>>> [ 4.658293] mmcblk0: p1 p2 >>>> >>>> Note: Their is need to reset the PMIC >>>> S2MPS11_REG_L13CTRL/S2MPS11_REG_L19CTRL registers >>>> to support this feature consistently on every reboot. >>>> >>>> -Anand Moon >>>> -- >>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in >>>> the body of a message to majordomo at vger.kernel.org >>>> More majordomo info at http://vger.kernel.org/majordomo-info.html >>>> Please read the FAQ at http://www.tux.org/lkml/ >>>> >>> >>> >> > >