From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Wed, 15 Apr 2020 08:37:09 +0200 Subject: [PATCH u-boot-marvell 1/1] clk: armada-37xx-periph: fix DDR PHY clock divider values In-Reply-To: <20200414225918.12844-1-marek.behun@nic.cz> References: <20200414225918.12844-1-marek.behun@nic.cz> Message-ID: <5625034c-f057-b8d3-2161-fdeda506138d@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 15.04.20 00:59, Marek Beh?n wrote: > Register value table for DDR PHY clock divider are wrong. They should be > 0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current > values do not make sense, since 2 cannot be achieved, because the > register is only 1 bit long (mask is set to 1). > > This fixes clk dump reporting DDR PHY clock rate differently from Linux. > > Signed-off-by: Marek Beh?n Reviewed-by: Stefan Roese Thanks, Stefan > --- > drivers/clk/mvebu/armada-37xx-periph.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c > index 068e48ea04..855f979b4f 100644 > --- a/drivers/clk/mvebu/armada-37xx-periph.c > +++ b/drivers/clk/mvebu/armada-37xx-periph.c > @@ -89,8 +89,8 @@ static const struct clk_div_table div_table1[] = { > }; > > static const struct clk_div_table div_table2[] = { > - { 2, 1 }, > - { 4, 2 }, > + { 2, 0 }, > + { 4, 1 }, > { 0, 0 }, > }; > > Viele Gr??e, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de