From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zoq1K-0002FQ-VS for qemu-devel@nongnu.org; Wed, 21 Oct 2015 05:49:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zoq1H-0000ye-OI for qemu-devel@nongnu.org; Wed, 21 Oct 2015 05:49:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59470) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zoq1H-0000yY-Ia for qemu-devel@nongnu.org; Wed, 21 Oct 2015 05:49:19 -0400 References: <1445364840-7056-1-git-send-email-lersek@redhat.com> From: Paolo Bonzini Message-ID: <56275F99.6000008@redhat.com> Date: Wed, 21 Oct 2015 11:49:13 +0200 MIME-Version: 1.0 In-Reply-To: <1445364840-7056-1-git-send-email-lersek@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] hw/isa/lpc_ich9: inject the SMI on the VCPU that is writing to APM_CNT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laszlo Ersek , qemu-devel@nongnu.org Cc: Michael Kinney , Jordan Justen , Gerd Hoffmann , "Michael S. Tsirkin" On 20/10/2015 20:14, Laszlo Ersek wrote: > Commit 4d00636e97b7 ("ich9: Add the lpc chip", Nov 14 2012) added the > ich9_apm_ctrl_changed() ioport write callback function such that it would > inject the SMI, in response to a write to the APM_CNT register, on the > first CPU, invariably. > > Since this register is used by guest code to trigger an SMI synchronously, > the interrupt should be injected on the VCPU that is performing the write. > > apm_ioport_writeb() is the .write callback of the "apm_ops" > MemoryRegionOps [hw/isa/apm.c]; it is parametrized to call > ich9_apm_ctrl_changed() by ich9_lpc_init() [hw/isa/lpc_ich9.c], via > apm_init(). Therefore this change affects no other board. > > ich9_generate_smi() is an unrelated function that is called by the TCO > watchdog; a watchdog is likely in its right to (asynchronously) inject > interrupts on the first CPU only. > > This patch allows the combined edk2/OVMF SMM driver stack to work with > multiple VCPUs on TCG, using both qemu-system-i386 and qemu-system-x86_64. > > Cc: Paolo Bonzini > Cc: Gerd Hoffmann > Cc: Jordan Justen > Cc: Michael Kinney > Cc: "Michael S. Tsirkin" > Signed-off-by: Laszlo Ersek > --- > hw/isa/lpc_ich9.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c > index 360699f..1ffc803 100644 > --- a/hw/isa/lpc_ich9.c > +++ b/hw/isa/lpc_ich9.c > @@ -394,7 +394,7 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *arg) > > /* SMI_EN = PMBASE + 30. SMI control and enable register */ > if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { > - cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); > + cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); > } > } > > Reviewed-by: Paolo Bonzini The same issue happens on PIIX4. I can fix it as the change is a bit more involved (it goes through a qemu_irq). Paolo