From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrpmg-00009w-GE for qemu-devel@nongnu.org; Thu, 29 Oct 2015 12:10:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zrpmc-0003EV-5t for qemu-devel@nongnu.org; Thu, 29 Oct 2015 12:10:38 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:21800) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrpmb-0003DL-OM for qemu-devel@nongnu.org; Thu, 29 Oct 2015 12:10:34 -0400 References: <1445965957-37888-1-git-send-email-yongbok.kim@imgtec.com> <1445965957-37888-4-git-send-email-yongbok.kim@imgtec.com> From: Leon Alrae Message-ID: <563244E3.20802@imgtec.com> Date: Thu, 29 Oct 2015 16:10:11 +0000 MIME-Version: 1.0 In-Reply-To: <1445965957-37888-4-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH for-2.5 v2 3/4] mips: add Global Interrupt Controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, crosthwaitepeter@gmail.com, james.hogan@imgtec.com, aurelien@aurel32.net, pbonzini@redhat.com On 27/10/15 17:12, Yongbok Kim wrote: > +static uint64_t gic_read(void *opaque, hwaddr addr, unsigned size) > +{ > + MIPSGICState *gic =3D (MIPSGICState *) opaque; > + uint32_t vp_index =3D gic_get_current_vp(gic); > + uint64_t ret =3D 0; > + int i, base, irq_src; > + uint32_t other_index; > + > + switch (addr) { > + case GIC_SH_CONFIG_OFS: > + ret =3D gic->sh_config; > + break; > + case GIC_SH_COUNTERLO_OFS: > + ret =3D gic_get_sh_count(gic); > + break; > + case GIC_SH_COUNTERHI_OFS: > + ret =3D 0; > + break; > + case GIC_SH_PEND_31_0_OFS ... GIC_SH_PEND_255_224_OFS: > + base =3D (addr - GIC_SH_PEND_31_0_OFS) * 8; > + for (i =3D 0; i < size * 8; i++) { > + ret |=3D (gic->irq_state[base + i].pending & 1) << i; The "pending" field is bool and "i" can be up to 63, which means this may try to do the left-shifting above the width. > + } > + break; > + case GIC_SH_MASK_31_0_OFS ... GIC_SH_MASK_255_224_OFS: > + base =3D (addr - GIC_SH_MASK_31_0_OFS) * 8; > + for (i =3D 0; i < size * 8; i++) { > + ret |=3D (gic->irq_state[base + i].enabled & 1) << i; same > + } > + break; > + case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS: > + irq_src =3D (addr - GIC_SH_MAP0_PIN_OFS) / 4; > + ret =3D gic->irq_state[irq_src].map_pin; > + break; > + case GIC_SH_MAP0_VP31_0_OFS ... GIC_SH_MAP255_VP63_32_OFS: > + irq_src =3D (addr - GIC_SH_MAP0_VP31_0_OFS) / 32; > + if ((gic->irq_state[irq_src].map_vp) >=3D 0) { > + ret =3D 1 << (gic->irq_state[irq_src].map_vp); > + } else { > + ret =3D 0; > + } > + break; > + /* VP-Local Register */ > + case GIC_VPLOCAL_BASE_ADDR ... (GIC_VPLOCAL_BASE_ADDR + GIC_VL_BRK= _GROUP): > + ret =3D gic_read_vp(gic, vp_index, addr - GIC_VPLOCAL_BASE_ADD= R, size); > + break; > + /* VP-Other Register */ > + case GIC_VPOTHER_BASE_ADDR ... (GIC_VPOTHER_BASE_ADDR + GIC_VL_BRK= _GROUP): > + other_index =3D gic->vps[vp_index].other_addr; > + ret =3D gic_read_vp(gic, other_index, addr - GIC_VPOTHER_BASE_= ADDR, > + size); > + break; > + /* User-Mode Visible section */ > + case GIC_USERMODE_BASE_ADDR + GIC_USER_MODE_COUNTERLO: > + ret =3D gic_get_sh_count(gic); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset 0x%" PRI= x64 "\n", > + size, addr); > + break; > + } > + return ret; > +} > + > +/* GIC Write VP Local/Other Registers */ > +static void gic_write_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr = addr, > + uint64_t data, unsigned size) > +{ > + switch (addr) { > + case GIC_VP_CTL_OFS: > + gic->vps[vp_index].ctl &=3D ~GIC_VP_CTL_EIC_MODE_MSK; > + gic->vps[vp_index].ctl |=3D data & GIC_VP_CTL_EIC_MODE_MSK; > + break; > + case GIC_VP_RMASK_OFS: > + gic->vps[vp_index].mask &=3D ~(data & GIC_VP_SET_RESET_MSK) & > + GIC_VP_SET_RESET_MSK; > + break; > + case GIC_VP_SMASK_OFS: > + gic->vps[vp_index].mask |=3D (data & GIC_VP_SET_RESET_MSK); > + break; > + case GIC_VP_COMPARE_MAP_OFS: > + gic->vps[vp_index].compare_map =3D data & GIC_MAP_TO_PIN_REG_M= SK; > + break; > + case GIC_VP_OTHER_ADDR_OFS: > + if (data < gic->num_vps) { > + gic->vps[vp_index].other_addr =3D data; > + } > + break; > + case GIC_VP_COMPARE_LO_OFS: > + gic_store_vp_compare(gic, vp_index, data); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset LOCAL/O= THER " > + "0x%" PRIx64" 0x%08lx\n", size, addr, data); The "%lx" format for data needs to be corrected as this generates warnings on my mingw32 (I noticed the same in gcr): hw/intc/mips_gic.c:333:23: warning: format =91%lx=92 expects argument of type =91long unsigned int=92, but argument 5 has type =91uint64_t=92 [-Wf= ormat] > + break; > + } > +} > + > +static void gic_reset(void *opaque) > +{ > + int i; > + MIPSGICState *gic =3D (MIPSGICState *) opaque; > + int numintrs =3D (gic->num_irq / 8) - 1; > + > + numintrs =3D (numintrs < 0) ? 0 : numintrs; If I understand correctly numintrs < 0 indicates that the "num-irq" property has been set to an incorrect value. I believe this should do the same thing as when it exceeds the max value, i.e. die early and loudl= y. Thanks, Leon