From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754575AbbKGVka (ORCPT ); Sat, 7 Nov 2015 16:40:30 -0500 Received: from mail-oi0-f48.google.com ([209.85.218.48]:32780 "EHLO mail-oi0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752400AbbKGVk1 (ORCPT ); Sat, 7 Nov 2015 16:40:27 -0500 Subject: Re: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP To: Kapil Hali , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Ray Jui , Scott Branden , Jon Mason References: <1446844273-6460-1-git-send-email-kapilh@broadcom.com> <1446844273-6460-2-git-send-email-kapilh@broadcom.com> Cc: Gregory Fong , Lee Jones , Hauke Mehrtens , Heiko Stuebner , Kever Yang , Maxime Ripard , Olof Johansson , Paul Walmsley , Linus Walleij , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com From: Florian Fainelli Message-ID: <563E6FC7.6070700@gmail.com> Date: Sat, 7 Nov 2015 13:40:23 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1446844273-6460-2-git-send-email-kapilh@broadcom.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 06/11/2015 13:11, Kapil Hali a écrit : > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali > --- > .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 ++++++++++++++++++++++ > Documentation/devicetree/bindings/arm/cpus.txt | 1 + > 2 files changed, 37 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > > diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > new file mode 100644 > index 0000000..8506da7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > @@ -0,0 +1,36 @@ > +Broadcom Northstar Plus SoC CPU Enable Method > +--------------------------------------------- > +This binding defines the enable method used for starting secondary > +CPUs in the following Broadcom SoCs: > + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 > + > +The enable method is specified by defining the following required > +properties in the "cpus" device tree node: > + - enable-method = "brcm,bcm-nsp-smp"; > + - secondary-boot-reg = <...>; > + > +The secondary-boot-reg property is a u32 value that specifies the > +physical address of the register used to request the ROM holding pen > +code release a secondary CPU. Is it really how the ROM code is implemented, as a pen holding/release mechanism (which sounds like how this was implemented previously in the kernel actually) or should this be described in a more generic way as the physical address of the register where the secondary CPUs reset vector address must be written to? Or something along these lines. > + > +Example: > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "brcm,bcm-nsp-smp"; Just a nit, but if NSP and NS are sharing the same mechanism, would not a more "NS-centric" property be more appropriate because NS came before NSP? > + secondary-boot-reg = <0xffff042c>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + next-level-cache = <&L2>; > + reg = <0>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + next-level-cache = <&L2>; > + reg = <1>; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > index 91e6e5c..6abe3f3 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.txt > +++ b/Documentation/devicetree/bindings/arm/cpus.txt > @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below. > "allwinner,sun8i-a23" > "arm,psci" > "brcm,brahma-b15" > + "brcm,bcm-nsp-smp" > "marvell,armada-375-smp" > "marvell,armada-380-smp" > "marvell,armada-390-smp" > -- Florian From mboxrd@z Thu Jan 1 00:00:00 1970 From: f.fainelli@gmail.com (Florian Fainelli) Date: Sat, 7 Nov 2015 13:40:23 -0800 Subject: [PATCH v3 1/4] dt-bindings: add SMP enable-method for Broadcom NSP In-Reply-To: <1446844273-6460-2-git-send-email-kapilh@broadcom.com> References: <1446844273-6460-1-git-send-email-kapilh@broadcom.com> <1446844273-6460-2-git-send-email-kapilh@broadcom.com> Message-ID: <563E6FC7.6070700@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Le 06/11/2015 13:11, Kapil Hali a ?crit : > Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's > Northstar Plus CPU to the 32-bit ARM CPU device tree binding > documentation file and create a new binding documentation for > Northstar Plus CPU. > > Signed-off-by: Kapil Hali > --- > .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 36 ++++++++++++++++++++++ > Documentation/devicetree/bindings/arm/cpus.txt | 1 + > 2 files changed, 37 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > > diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > new file mode 100644 > index 0000000..8506da7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt > @@ -0,0 +1,36 @@ > +Broadcom Northstar Plus SoC CPU Enable Method > +--------------------------------------------- > +This binding defines the enable method used for starting secondary > +CPUs in the following Broadcom SoCs: > + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 > + > +The enable method is specified by defining the following required > +properties in the "cpus" device tree node: > + - enable-method = "brcm,bcm-nsp-smp"; > + - secondary-boot-reg = <...>; > + > +The secondary-boot-reg property is a u32 value that specifies the > +physical address of the register used to request the ROM holding pen > +code release a secondary CPU. Is it really how the ROM code is implemented, as a pen holding/release mechanism (which sounds like how this was implemented previously in the kernel actually) or should this be described in a more generic way as the physical address of the register where the secondary CPUs reset vector address must be written to? Or something along these lines. > + > +Example: > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "brcm,bcm-nsp-smp"; Just a nit, but if NSP and NS are sharing the same mechanism, would not a more "NS-centric" property be more appropriate because NS came before NSP? > + secondary-boot-reg = <0xffff042c>; > + > + cpu0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + next-level-cache = <&L2>; > + reg = <0>; > + }; > + > + cpu1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + next-level-cache = <&L2>; > + reg = <1>; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > index 91e6e5c..6abe3f3 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.txt > +++ b/Documentation/devicetree/bindings/arm/cpus.txt > @@ -191,6 +191,7 @@ nodes to be present and contain the properties described below. > "allwinner,sun8i-a23" > "arm,psci" > "brcm,brahma-b15" > + "brcm,bcm-nsp-smp" > "marvell,armada-375-smp" > "marvell,armada-380-smp" > "marvell,armada-390-smp" > -- Florian