[U-Boot] [PATCH v2 00/16] device model bring-up of ti-qspi on dra72, dra74 and am437x-sk evm

[U-Boot] [PATCH v2 00/16] device model bring-up of ti-qspi on dra72, dra74 and am437x-sk evm

[Mugunthan V N]

This patch series enables ti_qspi to adopt driver model. This has
been tested on dra72, dra74 and am437x-sk evms (logs [1]).
Also pushed a branch for testing [2]

[1]: http://pastebin.ubuntu.com/13099856/
[2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git qspi-v2

Changes from Initial version:
* Split "prepare driver for DM conversion" for easier review
* added memory map mode to the driver
* Fixed the cosmetic reviews from Simon
* Modified the dev_get_addr_index to adopt OF_TRANSULATE as well
  and also removed code duplicate.
* Added compatibles for spi flashed found in DRA7xx and AM437x SK

Mugunthan V N (16):
  drivers: spi: ti_qspi: do not hard code chip select for memory map
    configuration
  drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver
    model conversion
  drivers: spi: ti_qspi: prepare driver for DM conversion
  dm: core: Add a new api to get indexed device address
  spi: Add support for dual and quad mode
  dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl
  dts: dra7: add spi alias for qspi
  drivers: spi: ti_qspi: convert driver to adopt device driver model
  arm: dts: dra7: add qspi register maps for memory map and control
    module
  drivers: mtd: spi: sf_probe: add compatible for spansion spi flash
  drivers: mtd: spi: sf_probe: add compatible for Macronix spi flash
  defconfig: dra72_evm: enable spi driver model
  defconfig: dra74_evm: enable spi driver model
  am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl
  arm: dts: am4372: add qspi register maps for memory map
  defconfig: am437x_sk_evm: enable spi driver model

 arch/arm/dts/am4372.dtsi        |   4 +-
 arch/arm/dts/dra7.dtsi          |   5 +-
 configs/am437x_sk_evm_defconfig |   3 +
 configs/dra72_evm_defconfig     |   2 +
 configs/dra74_evm_defconfig     |   2 +
 drivers/core/device.c           |  16 +-
 drivers/mtd/spi/sf_probe.c      |   2 +
 drivers/spi/spi-uclass.c        |  33 +++
 drivers/spi/ti_qspi.c           | 515 ++++++++++++++++++++++++++++------------
 include/configs/am43xx_evm.h    |   2 +
 include/configs/dra7xx_evm.h    |   5 +
 include/dm/device.h             |  10 +
 include/spi.h                   |   4 +
 13 files changed, 442 insertions(+), 161 deletions(-)

-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 01/16] drivers: spi: ti_qspi: do not hard code chip select for memory map configuration

[Mugunthan V N]

To enable memory map in dra7xx, specific chip select must be
written to control module register. But this hard coded to chip
select 1, fixing it by writing the specific chip select value to
control module register.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/spi/ti_qspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index ecd9d78..36bf206 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -41,7 +41,7 @@
 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
 #define QSPI_XFER_DONE                  QSPI_WC
 #define MM_SWITCH                       0x01
-#define MEM_CS                          0x100
+#define MEM_CS(cs)                      ((cs + 1) << 8)
 #define MEM_CS_UNSELECT                 0xfffff0ff
 #define MMAP_START_ADDR_DRA		0x5c000000
 #define MMAP_START_ADDR_AM43x		0x30000000
@@ -265,7 +265,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		writel(MM_SWITCH, &qslave->base->memswitch);
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 		val = readl(CORE_CTRL_IO);
-		val |= MEM_CS;
+		val |= MEM_CS(slave->cs);
 		writel(val, CORE_CTRL_IO);
 #endif
 		return 0;
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 01/16] drivers: spi: ti_qspi: do not hard code chip select for memory map configuration

[Simon Glass]

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> To enable memory map in dra7xx, specific chip select must be
> written to control module register. But this hard coded to chip
> select 1, fixing it by writing the specific chip select value to
> control module register.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/spi/ti_qspi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

But maybe it would be better to just drop the MEM_CS macro.

>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index ecd9d78..36bf206 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -41,7 +41,7 @@
>  #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
>  #define QSPI_XFER_DONE                  QSPI_WC
>  #define MM_SWITCH                       0x01
> -#define MEM_CS                          0x100
> +#define MEM_CS(cs)                      ((cs + 1) << 8)
>  #define MEM_CS_UNSELECT                 0xfffff0ff
>  #define MMAP_START_ADDR_DRA            0x5c000000
>  #define MMAP_START_ADDR_AM43x          0x30000000
> @@ -265,7 +265,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
>                 writel(MM_SWITCH, &qslave->base->memswitch);
>  #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
>                 val = readl(CORE_CTRL_IO);
> -               val |= MEM_CS;
> +               val |= MEM_CS(slave->cs);
>                 writel(val, CORE_CTRL_IO);
>  #endif
>                 return 0;
> --
> 2.6.2.280.g74301d6
>

Regards,
Simon

[U-Boot] [PATCH v2 01/16] drivers: spi: ti_qspi: do not hard code chip select for memory map configuration

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:09PM +0530, Mugunthan V N wrote:

> To enable memory map in dra7xx, specific chip select must be
> written to control module register. But this hard coded to chip
> select 1, fixing it by writing the specific chip select value to
> control module register.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 01/16] drivers: spi: ti_qspi: do not hard code chip select for memory map configuration

[Jagan Teki]

On 8 November 2015 at 19:01, Tom Rini <trini@konsulko.com> wrote:
> On Wed, Nov 04, 2015 at 01:46:09PM +0530, Mugunthan V N wrote:
>
>> To enable memory map in dra7xx, specific chip select must be
>> written to control module register. But this hard coded to chip
>> select 1, fixing it by writing the specific chip select value to
>> control module register.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH v2 02/16] drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion

[Mugunthan V N]

Changing the ti_qspi_priv structure and its instance names from
to priv for driver mode conversion.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/spi/ti_qspi.c | 118 +++++++++++++++++++++++++-------------------------
 1 file changed, 59 insertions(+), 59 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 36bf206..44c5762 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -85,8 +85,8 @@ struct ti_qspi_regs {
 	u32 data3;
 };
 
-/* ti qspi slave */
-struct ti_qspi_slave {
+/* ti qspi priv */
+struct ti_qspi_priv {
 	struct spi_slave slave;
 	struct ti_qspi_regs *base;
 	unsigned int mode;
@@ -94,14 +94,14 @@ struct ti_qspi_slave {
 	u32 dc;
 };
 
-static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
 {
-	return container_of(slave, struct ti_qspi_slave, slave);
+	return container_of(slave, struct ti_qspi_priv, slave);
 }
 
-static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
 {
-	struct spi_slave *slave = &qslave->slave;
+	struct spi_slave *slave = &priv->slave;
 	u32 memval = 0;
 
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
@@ -123,12 +123,12 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
 			QSPI_NUM_DUMMY_BITS;
 #endif
 
-	writel(memval, &qslave->base->setup0);
+	writel(memval, &priv->base->setup0);
 }
 
 static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
 {
-	struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 	uint clk_div;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
@@ -139,8 +139,8 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
 		clk_div = (QSPI_FCLK / hz) - 1;
 
 	/* disable SCLK */
-	writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
-	       &qslave->base->clk_ctrl);
+	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
+	       &priv->base->clk_ctrl);
 
 	/* assign clk_div values */
 	if (clk_div < 0)
@@ -149,7 +149,7 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
 		clk_div = QSPI_CLK_DIV_MAX;
 
 	/* enable SCLK */
-	writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
+	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }
 
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -165,11 +165,11 @@ void spi_cs_activate(struct spi_slave *slave)
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 
 	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
 
-	writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 }
 
 void spi_init(void)
@@ -180,73 +180,73 @@ void spi_init(void)
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 				  unsigned int max_hz, unsigned int mode)
 {
-	struct ti_qspi_slave *qslave;
+	struct ti_qspi_priv *priv;
 
 #ifdef CONFIG_AM43XX
 	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
 	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
 #endif
 
-	qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
-	if (!qslave) {
-		printf("SPI_error: Fail to allocate ti_qspi_slave\n");
+	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
+	if (!priv) {
+		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
 		return NULL;
 	}
 
-	qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
-	qslave->mode = mode;
+	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
+	priv->mode = mode;
 
-	ti_spi_set_speed(&qslave->slave, max_hz);
+	ti_spi_set_speed(&priv->slave, max_hz);
 
 #ifdef CONFIG_TI_SPI_MMAP
-	ti_spi_setup_spi_register(qslave);
+	ti_spi_setup_spi_register(priv);
 #endif
 
-	return &qslave->slave;
+	return &priv->slave;
 }
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-	free(qslave);
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+	free(priv);
 }
 
 int spi_claim_bus(struct spi_slave *slave)
 {
-	struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 
 	debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
 
-	qslave->dc = 0;
-	if (qslave->mode & SPI_CPHA)
-		qslave->dc |= QSPI_CKPHA(slave->cs);
-	if (qslave->mode & SPI_CPOL)
-		qslave->dc |= QSPI_CKPOL(slave->cs);
-	if (qslave->mode & SPI_CS_HIGH)
-		qslave->dc |= QSPI_CSPOL(slave->cs);
+	priv->dc = 0;
+	if (priv->mode & SPI_CPHA)
+		priv->dc |= QSPI_CKPHA(slave->cs);
+	if (priv->mode & SPI_CPOL)
+		priv->dc |= QSPI_CKPOL(slave->cs);
+	if (priv->mode & SPI_CS_HIGH)
+		priv->dc |= QSPI_CSPOL(slave->cs);
 
-	writel(qslave->dc, &qslave->base->dc);
-	writel(0, &qslave->base->cmd);
-	writel(0, &qslave->base->data);
+	writel(priv->dc, &priv->base->dc);
+	writel(0, &priv->base->cmd);
+	writel(0, &priv->base->data);
 
 	return 0;
 }
 
 void spi_release_bus(struct spi_slave *slave)
 {
-	struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 
 	debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
 
-	writel(0, &qslave->base->dc);
-	writel(0, &qslave->base->cmd);
-	writel(0, &qslave->base->data);
+	writel(0, &priv->base->dc);
+	writel(0, &priv->base->cmd);
+	writel(0, &priv->base->data);
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	     void *din, unsigned long flags)
 {
-	struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 	uint words = bitlen >> 3; /* fixed 8-bit word length */
 	const uchar *txp = dout;
 	uchar *rxp = din;
@@ -262,7 +262,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	/* Setup mmap flags */
 	if (flags & SPI_XFER_MMAP) {
-		writel(MM_SWITCH, &qslave->base->memswitch);
+		writel(MM_SWITCH, &priv->base->memswitch);
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 		val = readl(CORE_CTRL_IO);
 		val |= MEM_CS(slave->cs);
@@ -270,7 +270,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 #endif
 		return 0;
 	} else if (flags & SPI_XFER_MMAP_END) {
-		writel(~MM_SWITCH, &qslave->base->memswitch);
+		writel(~MM_SWITCH, &priv->base->memswitch);
 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 		val = readl(CORE_CTRL_IO);
 		val &= MEM_CS_UNSELECT;
@@ -288,12 +288,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	}
 
 	/* Setup command reg */
-	qslave->cmd = 0;
-	qslave->cmd |= QSPI_WLEN(8);
-	qslave->cmd |= QSPI_EN_CS(slave->cs);
+	priv->cmd = 0;
+	priv->cmd |= QSPI_WLEN(8);
+	priv->cmd |= QSPI_EN_CS(slave->cs);
 	if (flags & SPI_3WIRE)
-		qslave->cmd |= QSPI_3_PIN;
-	qslave->cmd |= 0xfff;
+		priv->cmd |= QSPI_3_PIN;
+	priv->cmd |= 0xfff;
 
 /* FIXME: This delay is required for successfull
  * completion of read/write/erase. Once its root
@@ -305,39 +305,39 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	while (words--) {
 		if (txp) {
 			debug("tx cmd %08x dc %08x data %02x\n",
-			      qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
-			writel(*txp++, &qslave->base->data);
-			writel(qslave->cmd | QSPI_WR_SNGL,
-			       &qslave->base->cmd);
-			status = readl(&qslave->base->status);
+			      priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
+			writel(*txp++, &priv->base->data);
+			writel(priv->cmd | QSPI_WR_SNGL,
+			       &priv->base->cmd);
+			status = readl(&priv->base->status);
 			timeout = QSPI_TIMEOUT;
 			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 				if (--timeout < 0) {
 					printf("spi_xfer: TX timeout!\n");
 					return -1;
 				}
-				status = readl(&qslave->base->status);
+				status = readl(&priv->base->status);
 			}
 			debug("tx done, status %08x\n", status);
 		}
 		if (rxp) {
-			qslave->cmd |= QSPI_RD_SNGL;
+			priv->cmd |= QSPI_RD_SNGL;
 			debug("rx cmd %08x dc %08x\n",
-			      qslave->cmd, qslave->dc);
+			      priv->cmd, priv->dc);
 			#ifdef CONFIG_DRA7XX
 				udelay(500);
 			#endif
-			writel(qslave->cmd, &qslave->base->cmd);
-			status = readl(&qslave->base->status);
+			writel(priv->cmd, &priv->base->cmd);
+			status = readl(&priv->base->status);
 			timeout = QSPI_TIMEOUT;
 			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 				if (--timeout < 0) {
 					printf("spi_xfer: RX timeout!\n");
 					return -1;
 				}
-				status = readl(&qslave->base->status);
+				status = readl(&priv->base->status);
 			}
-			*rxp++ = readl(&qslave->base->data);
+			*rxp++ = readl(&priv->base->data);
 			debug("rx done, status %08x, read %02x\n",
 			      status, *(rxp-1));
 		}
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 02/16] drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion

[Simon Glass]

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Changing the ti_qspi_priv structure and its instance names from
> to priv for driver mode conversion.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/spi/ti_qspi.c | 118 +++++++++++++++++++++++++-------------------------
>  1 file changed, 59 insertions(+), 59 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 02/16] drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:10PM +0530, Mugunthan V N wrote:

> Changing the ti_qspi_priv structure and its instance names from
> to priv for driver mode conversion.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 02/16] drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion

[Jagan Teki]

On 8 November 2015 at 19:01, Tom Rini <trini@konsulko.com> wrote:
> On Wed, Nov 04, 2015 at 01:46:10PM +0530, Mugunthan V N wrote:
>
>> Changing the ti_qspi_priv structure and its instance names from
>> to priv for driver mode conversion.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Reviewed-by: Jagan Teki <jteki@openedev.com>

-- 
Jagan.

[U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Mugunthan V N]

Prepare driver for DM conversion.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++----------------------
 1 file changed, 161 insertions(+), 126 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 44c5762..003df80 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -28,6 +28,7 @@
 #define QSPI_3_PIN                      BIT(18)
 #define QSPI_RD_SNGL                    BIT(16)
 #define QSPI_WR_SNGL                    (2 << 16)
+#define QSPI_RD_DUAL                    (7 << 16)
 #define QSPI_INVAL                      (4 << 16)
 #define QSPI_RD_QUAD                    (7 << 16)
 /* device control */
@@ -89,46 +90,16 @@ struct ti_qspi_regs {
 struct ti_qspi_priv {
 	struct spi_slave slave;
 	struct ti_qspi_regs *base;
+	void *ctrl_mod_mmap;
 	unsigned int mode;
 	u32 cmd;
 	u32 dc;
+	u32 num_cs;
+	u32 rx_bus_width;
 };
 
-static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
-{
-	return container_of(slave, struct ti_qspi_priv, slave);
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
-{
-	struct spi_slave *slave = &priv->slave;
-	u32 memval = 0;
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-	slave->memory_map = (void *)MMAP_START_ADDR_DRA;
-#else
-	slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
-#endif
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
-	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
-			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
-			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
-			QSPI_NUM_DUMMY_BITS);
-	slave->op_mode_rx = SPI_OPM_RX_QOF;
-#else
-	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
-			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
-			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
-			QSPI_NUM_DUMMY_BITS;
-#endif
-
-	writel(memval, &priv->base->setup0);
-}
-
-static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
+static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 {
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 	uint clk_div;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
@@ -152,130 +123,80 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
 	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
+static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 {
-	/* CS handled in xfer */
-	return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
-	debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
-
 	writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 }
 
-void spi_init(void)
+static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
 {
-	/* nothing to do */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	struct ti_qspi_priv *priv;
-
-#ifdef CONFIG_AM43XX
-	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
-	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
-	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
-	if (!priv) {
-		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
-		return NULL;
-	}
-
-	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
-	priv->mode = mode;
-
-	ti_spi_set_speed(&priv->slave, max_hz);
-
-#ifdef CONFIG_TI_SPI_MMAP
-	ti_spi_setup_spi_register(priv);
-#endif
-
-	return &priv->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-	free(priv);
+	priv->dc = 0;
+	if (mode & SPI_CPHA)
+		priv->dc |= QSPI_CKPHA(0);
+	if (mode & SPI_CPOL)
+		priv->dc |= QSPI_CKPOL(0);
+	if (mode & SPI_CS_HIGH)
+		priv->dc |= QSPI_CSPOL(0);
+
+	if (mode & SPI_RX_QUAD)
+		priv->rx_bus_width = QSPI_RD_QUAD;
+	else if (mode & SPI_RX_QUAD)
+		priv->rx_bus_width = QSPI_RD_DUAL;
+	else
+		priv->rx_bus_width = QSPI_RD_SNGL;
+	return 0;
 }
 
-int spi_claim_bus(struct spi_slave *slave)
+static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
 {
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
-	debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
-
-	priv->dc = 0;
-	if (priv->mode & SPI_CPHA)
-		priv->dc |= QSPI_CKPHA(slave->cs);
-	if (priv->mode & SPI_CPOL)
-		priv->dc |= QSPI_CKPOL(slave->cs);
-	if (priv->mode & SPI_CS_HIGH)
-		priv->dc |= QSPI_CSPOL(slave->cs);
-
 	writel(priv->dc, &priv->base->dc);
 	writel(0, &priv->base->cmd);
 	writel(0, &priv->base->data);
 
+	priv->dc <<= cs * 8;
+	writel(priv->dc, &priv->base->dc);
 	return 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
+static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
 {
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
-
-	debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
-
 	writel(0, &priv->base->dc);
 	writel(0, &priv->base->cmd);
 	writel(0, &priv->base->data);
 }
 
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
+static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
+{
+	u32 val;
+
+	val = readl(ctrl_mod_mmap);
+	if (enable)
+		val |= MEM_CS(cs);
+	else
+		val &= MEM_CS_UNSELECT;
+	writel(val, ctrl_mod_mmap);
+}
+
+static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
+			const void *dout, void *din, unsigned long flags,
+			u32 cs)
 {
-	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 	uint words = bitlen >> 3; /* fixed 8-bit word length */
 	const uchar *txp = dout;
 	uchar *rxp = din;
 	uint status;
 	int timeout;
 
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-	int val;
-#endif
-
-	debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
-	      slave->bus, slave->cs, bitlen, words, flags);
-
 	/* Setup mmap flags */
 	if (flags & SPI_XFER_MMAP) {
 		writel(MM_SWITCH, &priv->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-		val = readl(CORE_CTRL_IO);
-		val |= MEM_CS(slave->cs);
-		writel(val, CORE_CTRL_IO);
-#endif
+		if (priv->ctrl_mod_mmap)
+			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
 		return 0;
 	} else if (flags & SPI_XFER_MMAP_END) {
 		writel(~MM_SWITCH, &priv->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-		val = readl(CORE_CTRL_IO);
-		val &= MEM_CS_UNSELECT;
-		writel(val, CORE_CTRL_IO);
-#endif
+		if (priv->ctrl_mod_mmap)
+			ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
 		return 0;
 	}
 
@@ -290,7 +211,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	/* Setup command reg */
 	priv->cmd = 0;
 	priv->cmd |= QSPI_WLEN(8);
-	priv->cmd |= QSPI_EN_CS(slave->cs);
+	priv->cmd |= QSPI_EN_CS(cs);
 	if (flags & SPI_3WIRE)
 		priv->cmd |= QSPI_3_PIN;
 	priv->cmd |= 0xfff;
@@ -345,7 +266,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	/* Terminate frame */
 	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
+		ti_qspi_cs_deactivate(priv);
 
 	return 0;
 }
@@ -372,3 +293,117 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 	*((unsigned int *)offset) += len;
 }
 #endif
+
+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
+{
+	return container_of(slave, struct ti_qspi_priv, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* CS handled in xfer */
+	return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+	ti_qspi_cs_deactivate(priv);
+}
+
+void spi_init(void)
+{
+	/* nothing to do */
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
+{
+	u32 memval = 0;
+
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+	struct spi_slave *slave = &priv->slave;
+	memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+			QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+			QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+			QSPI_NUM_DUMMY_BITS);
+	slave->op_mode_rx = SPI_OPM_RX_QOF;
+#else
+	memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+			QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+			QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+			QSPI_NUM_DUMMY_BITS;
+#endif
+
+	writel(memval, &priv->base->setup0);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	struct ti_qspi_priv *priv;
+
+#ifdef CONFIG_AM43XX
+	gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+	gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
+	priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
+	if (!priv) {
+		printf("SPI_error: Fail to allocate ti_qspi_priv\n");
+		return NULL;
+	}
+
+	priv->base = (struct ti_qspi_regs *)QSPI_BASE;
+	priv->mode = mode;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+	priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
+	priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+	priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
+
+	ti_spi_set_speed(priv, max_hz);
+
+#ifdef CONFIG_TI_SPI_MMAP
+	ti_spi_setup_spi_register(priv);
+#endif
+
+	return &priv->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+	free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+	__ti_qspi_set_mode(priv, priv->mode);
+	return __ti_qspi_claim_bus(priv, priv->slave.cs);
+}
+void spi_release_bus(struct spi_slave *slave)
+{
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+	debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+	__ti_qspi_release_bus(priv);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+	debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
+	      priv->slave.bus, priv->slave.cs, bitlen, flags);
+	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+}
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Simon Glass]

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Prepare driver for DM conversion.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++----------------------
>  1 file changed, 161 insertions(+), 126 deletions(-)

This looks OK except for the lack of a change log and one thing below.
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index 44c5762..003df80 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -28,6 +28,7 @@
>  #define QSPI_3_PIN                      BIT(18)
>  #define QSPI_RD_SNGL                    BIT(16)
>  #define QSPI_WR_SNGL                    (2 << 16)
> +#define QSPI_RD_DUAL                    (7 << 16)
>  #define QSPI_INVAL                      (4 << 16)
>  #define QSPI_RD_QUAD                    (7 << 16)
>  /* device control */
> @@ -89,46 +90,16 @@ struct ti_qspi_regs {
>  struct ti_qspi_priv {
>         struct spi_slave slave;

This should not be present when driver model is used. Can you put an
#ifdef around it and store anything else you need directly in the
structure, rather than using struct spi_slave?

>         struct ti_qspi_regs *base;
> +       void *ctrl_mod_mmap;
>         unsigned int mode;
>         u32 cmd;
>         u32 dc;
> +       u32 num_cs;
> +       u32 rx_bus_width;
>  };
>

[U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Mugunthan V N]

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
> Hi Mugunthan,
> 
> On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> Prepare driver for DM conversion.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> ---
>>  drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++----------------------
>>  1 file changed, 161 insertions(+), 126 deletions(-)
> 
> This looks OK except for the lack of a change log and one thing below.
>>
>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>> index 44c5762..003df80 100644
>> --- a/drivers/spi/ti_qspi.c
>> +++ b/drivers/spi/ti_qspi.c
>> @@ -28,6 +28,7 @@
>>  #define QSPI_3_PIN                      BIT(18)
>>  #define QSPI_RD_SNGL                    BIT(16)
>>  #define QSPI_WR_SNGL                    (2 << 16)
>> +#define QSPI_RD_DUAL                    (7 << 16)
>>  #define QSPI_INVAL                      (4 << 16)
>>  #define QSPI_RD_QUAD                    (7 << 16)
>>  /* device control */
>> @@ -89,46 +90,16 @@ struct ti_qspi_regs {
>>  struct ti_qspi_priv {
>>         struct spi_slave slave;
> 
> This should not be present when driver model is used. Can you put an
> #ifdef around it and store anything else you need directly in the
> structure, rather than using struct spi_slave?

Yeah, will do it in next version.

> 
>>         struct ti_qspi_regs *base;
>> +       void *ctrl_mod_mmap;
>>         unsigned int mode;
>>         u32 cmd;
>>         u32 dc;
>> +       u32 num_cs;
>> +       u32 rx_bus_width;
>>  };
>>

Regards
Mugunthan V N

[U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Jagan Teki]

On 4 November 2015 at 13:46, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Prepare driver for DM conversion.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++----------------------
>  1 file changed, 161 insertions(+), 126 deletions(-)
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index 44c5762..003df80 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -28,6 +28,7 @@
>  #define QSPI_3_PIN                      BIT(18)
>  #define QSPI_RD_SNGL                    BIT(16)
>  #define QSPI_WR_SNGL                    (2 << 16)
> +#define QSPI_RD_DUAL                    (7 << 16)
>  #define QSPI_INVAL                      (4 << 16)
>  #define QSPI_RD_QUAD                    (7 << 16)
>  /* device control */
> @@ -89,46 +90,16 @@ struct ti_qspi_regs {
>  struct ti_qspi_priv {
>         struct spi_slave slave;
>         struct ti_qspi_regs *base;
> +       void *ctrl_mod_mmap;

Looks like this patch manages to prepare for non-dm addition by using
dm functions is it? and other than that some new things got added like
RD_DUAL or ctrl_mod_mmap, please add them separately add do the dm
conversion only on existing code.

>         unsigned int mode;
>         u32 cmd;
>         u32 dc;
> +       u32 num_cs;
> +       u32 rx_bus_width;
>  };
>
> -static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
> -{
> -       return container_of(slave, struct ti_qspi_priv, slave);
> -}
> -
> -static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
> -{
> -       struct spi_slave *slave = &priv->slave;
> -       u32 memval = 0;
> -
> -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
> -       slave->memory_map = (void *)MMAP_START_ADDR_DRA;
> -#else
> -       slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
> -#endif
> -
> -#ifdef CONFIG_QSPI_QUAD_SUPPORT
> -       memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
> -                       QSPI_SETUP0_NUM_D_BYTES_8_BITS |
> -                       QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
> -                       QSPI_NUM_DUMMY_BITS);
> -       slave->op_mode_rx = SPI_OPM_RX_QOF;
> -#else
> -       memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
> -                       QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
> -                       QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
> -                       QSPI_NUM_DUMMY_BITS;
> -#endif
> -
> -       writel(memval, &priv->base->setup0);
> -}
> -
> -static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
> +static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
>  {
> -       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
>         uint clk_div;
>
>         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
> @@ -152,130 +123,80 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
>         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
>  }
>
> -int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> -{
> -       return 1;
> -}
> -
> -void spi_cs_activate(struct spi_slave *slave)
> +static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
>  {
> -       /* CS handled in xfer */
> -       return;
> -}
> -
> -void spi_cs_deactivate(struct spi_slave *slave)
> -{
> -       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> -
> -       debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
> -
>         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
>  }
>
> -void spi_init(void)
> +static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
>  {
> -       /* nothing to do */
> -}
> -
> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> -                                 unsigned int max_hz, unsigned int mode)
> -{
> -       struct ti_qspi_priv *priv;
> -
> -#ifdef CONFIG_AM43XX
> -       gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
> -       gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
> -#endif
> -
> -       priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
> -       if (!priv) {
> -               printf("SPI_error: Fail to allocate ti_qspi_priv\n");
> -               return NULL;
> -       }
> -
> -       priv->base = (struct ti_qspi_regs *)QSPI_BASE;
> -       priv->mode = mode;
> -
> -       ti_spi_set_speed(&priv->slave, max_hz);
> -
> -#ifdef CONFIG_TI_SPI_MMAP
> -       ti_spi_setup_spi_register(priv);
> -#endif
> -
> -       return &priv->slave;
> -}
> -
> -void spi_free_slave(struct spi_slave *slave)
> -{
> -       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> -       free(priv);
> +       priv->dc = 0;
> +       if (mode & SPI_CPHA)
> +               priv->dc |= QSPI_CKPHA(0);
> +       if (mode & SPI_CPOL)
> +               priv->dc |= QSPI_CKPOL(0);
> +       if (mode & SPI_CS_HIGH)
> +               priv->dc |= QSPI_CSPOL(0);
> +
> +       if (mode & SPI_RX_QUAD)
> +               priv->rx_bus_width = QSPI_RD_QUAD;
> +       else if (mode & SPI_RX_QUAD)
> +               priv->rx_bus_width = QSPI_RD_DUAL;
> +       else
> +               priv->rx_bus_width = QSPI_RD_SNGL;
> +       return 0;
>  }
>
> -int spi_claim_bus(struct spi_slave *slave)
> +static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
>  {
> -       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> -
> -       debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
> -
> -       priv->dc = 0;
> -       if (priv->mode & SPI_CPHA)
> -               priv->dc |= QSPI_CKPHA(slave->cs);
> -       if (priv->mode & SPI_CPOL)
> -               priv->dc |= QSPI_CKPOL(slave->cs);
> -       if (priv->mode & SPI_CS_HIGH)
> -               priv->dc |= QSPI_CSPOL(slave->cs);
> -
>         writel(priv->dc, &priv->base->dc);
>         writel(0, &priv->base->cmd);
>         writel(0, &priv->base->data);
>
> +       priv->dc <<= cs * 8;
> +       writel(priv->dc, &priv->base->dc);
>         return 0;
>  }
>
> -void spi_release_bus(struct spi_slave *slave)
> +static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
>  {
> -       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> -
> -       debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
> -
>         writel(0, &priv->base->dc);
>         writel(0, &priv->base->cmd);
>         writel(0, &priv->base->data);
>  }
>
> -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> -            void *din, unsigned long flags)
> +static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
> +{
> +       u32 val;
> +
> +       val = readl(ctrl_mod_mmap);
> +       if (enable)
> +               val |= MEM_CS(cs);
> +       else
> +               val &= MEM_CS_UNSELECT;
> +       writel(val, ctrl_mod_mmap);
> +}
> +
> +static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
> +                       const void *dout, void *din, unsigned long flags,
> +                       u32 cs)
>  {
> -       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
>         uint words = bitlen >> 3; /* fixed 8-bit word length */
>         const uchar *txp = dout;
>         uchar *rxp = din;
>         uint status;
>         int timeout;
>
> -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
> -       int val;
> -#endif
> -
> -       debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
> -             slave->bus, slave->cs, bitlen, words, flags);
> -
>         /* Setup mmap flags */
>         if (flags & SPI_XFER_MMAP) {
>                 writel(MM_SWITCH, &priv->base->memswitch);
> -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
> -               val = readl(CORE_CTRL_IO);
> -               val |= MEM_CS(slave->cs);
> -               writel(val, CORE_CTRL_IO);
> -#endif
> +               if (priv->ctrl_mod_mmap)
> +                       ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
>                 return 0;
>         } else if (flags & SPI_XFER_MMAP_END) {
>                 writel(~MM_SWITCH, &priv->base->memswitch);
> -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
> -               val = readl(CORE_CTRL_IO);
> -               val &= MEM_CS_UNSELECT;
> -               writel(val, CORE_CTRL_IO);
> -#endif
> +               if (priv->ctrl_mod_mmap)
> +                       ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
>                 return 0;
>         }
>
> @@ -290,7 +211,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
>         /* Setup command reg */
>         priv->cmd = 0;
>         priv->cmd |= QSPI_WLEN(8);
> -       priv->cmd |= QSPI_EN_CS(slave->cs);
> +       priv->cmd |= QSPI_EN_CS(cs);
>         if (flags & SPI_3WIRE)
>                 priv->cmd |= QSPI_3_PIN;
>         priv->cmd |= 0xfff;
> @@ -345,7 +266,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
>
>         /* Terminate frame */
>         if (flags & SPI_XFER_END)
> -               spi_cs_deactivate(slave);
> +               ti_qspi_cs_deactivate(priv);
>
>         return 0;
>  }
> @@ -372,3 +293,117 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
>         *((unsigned int *)offset) += len;
>  }
>  #endif
> +
> +static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
> +{
> +       return container_of(slave, struct ti_qspi_priv, slave);
> +}
> +
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> +       return 1;
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> +       /* CS handled in xfer */
> +       return;
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> +       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> +       ti_qspi_cs_deactivate(priv);
> +}
> +
> +void spi_init(void)
> +{
> +       /* nothing to do */
> +}
> +
> +static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
> +{
> +       u32 memval = 0;
> +
> +#ifdef CONFIG_QSPI_QUAD_SUPPORT
> +       struct spi_slave *slave = &priv->slave;
> +       memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
> +                       QSPI_SETUP0_NUM_D_BYTES_8_BITS |
> +                       QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
> +                       QSPI_NUM_DUMMY_BITS);
> +       slave->op_mode_rx = SPI_OPM_RX_QOF;
> +#else
> +       memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
> +                       QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
> +                       QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
> +                       QSPI_NUM_DUMMY_BITS;
> +#endif
> +
> +       writel(memval, &priv->base->setup0);
> +}
> +
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +                                 unsigned int max_hz, unsigned int mode)
> +{
> +       struct ti_qspi_priv *priv;
> +
> +#ifdef CONFIG_AM43XX
> +       gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
> +       gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
> +#endif
> +
> +       priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
> +       if (!priv) {
> +               printf("SPI_error: Fail to allocate ti_qspi_priv\n");
> +               return NULL;
> +       }
> +
> +       priv->base = (struct ti_qspi_regs *)QSPI_BASE;
> +       priv->mode = mode;
> +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
> +       priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
> +       priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
> +#else
> +       priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
> +#endif
> +
> +       ti_spi_set_speed(priv, max_hz);
> +
> +#ifdef CONFIG_TI_SPI_MMAP
> +       ti_spi_setup_spi_register(priv);
> +#endif
> +
> +       return &priv->slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
> +{
> +       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> +       free(priv);
> +}
> +
> +int spi_claim_bus(struct spi_slave *slave)
> +{
> +       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> +
> +       debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
> +       __ti_qspi_set_mode(priv, priv->mode);
> +       return __ti_qspi_claim_bus(priv, priv->slave.cs);
> +}
> +void spi_release_bus(struct spi_slave *slave)
> +{
> +       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> +
> +       debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
> +       __ti_qspi_release_bus(priv);
> +}
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> +            void *din, unsigned long flags)
> +{
> +       struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
> +
> +       debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
> +             priv->slave.bus, priv->slave.cs, bitlen, flags);
> +       return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
> +}
> --
> 2.6.2.280.g74301d6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
Jagan | openedev.

[U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Mugunthan V N]

On Tuesday 17 November 2015 11:51 AM, Jagan Teki wrote:
> On 4 November 2015 at 13:46, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> Prepare driver for DM conversion.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> ---
>>  drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++----------------------
>>  1 file changed, 161 insertions(+), 126 deletions(-)
>>
>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>> index 44c5762..003df80 100644
>> --- a/drivers/spi/ti_qspi.c
>> +++ b/drivers/spi/ti_qspi.c
>> @@ -28,6 +28,7 @@
>>  #define QSPI_3_PIN                      BIT(18)
>>  #define QSPI_RD_SNGL                    BIT(16)
>>  #define QSPI_WR_SNGL                    (2 << 16)
>> +#define QSPI_RD_DUAL                    (7 << 16)
>>  #define QSPI_INVAL                      (4 << 16)
>>  #define QSPI_RD_QUAD                    (7 << 16)
>>  /* device control */
>> @@ -89,46 +90,16 @@ struct ti_qspi_regs {
>>  struct ti_qspi_priv {
>>         struct spi_slave slave;
>>         struct ti_qspi_regs *base;
>> +       void *ctrl_mod_mmap;
> 
> Looks like this patch manages to prepare for non-dm addition by using
> dm functions is it? and other than that some new things got added like
> RD_DUAL or ctrl_mod_mmap, please add them separately add do the dm
> conversion only on existing code.
> 

Will move all DM variables under #ifdef.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 03/16] drivers: spi: ti_qspi: prepare driver for DM conversion

[Mugunthan V N]

Jagan

On Tuesday 17 November 2015 11:51 AM, Jagan Teki wrote:
>> +       void *ctrl_mod_mmap;
> Looks like this patch manages to prepare for non-dm addition by using
> dm functions is it? and other than that some new things got added like
> RD_DUAL or ctrl_mod_mmap, please add them separately add do the dm
> conversion only on existing code.
> 

ctrl_mod_map is used in non DM mode as well. Earlier there was a define,
I changed it to a variable while preparing driver for DM conversion.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 04/16] dm: core: Add a new api to get indexed device address

[Mugunthan V N]

Add new api to get device address based on index.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/core/device.c | 16 ++++++++++++----
 include/dm/device.h   | 10 ++++++++++
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 758f390..3cdcab5 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -581,18 +581,21 @@ const char *dev_get_uclass_name(struct udevice *dev)
 	return dev->uclass->uc_drv->name;
 }
 
-fdt_addr_t dev_get_addr(struct udevice *dev)
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 	fdt_addr_t addr;
 
 	if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
 		const fdt32_t *reg;
+		int len = 0;
 
-		reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
-		if (!reg)
+		reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+		if (!reg || (len <= (index * sizeof(fdt32_t) * 2)))
 			return FDT_ADDR_T_NONE;
 
+		reg += index * 2;
+
 		/*
 		 * Use the full-fledged translate function for complex
 		 * bus setups.
@@ -608,7 +611,7 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
 	addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
 						dev->parent->of_offset,
 						dev->of_offset, "reg",
-						0, NULL);
+						index, NULL);
 	if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
 		if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
 			addr = simple_bus_translate(dev->parent, addr);
@@ -620,6 +623,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
 #endif
 }
 
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+	return dev_get_addr_index(dev, 0);
+}
+
 bool device_has_children(struct udevice *dev)
 {
 	return !list_empty(&dev->child_head);
diff --git a/include/dm/device.h b/include/dm/device.h
index 28ba4ca..4de66d7 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -454,6 +454,16 @@ int device_find_next_child(struct udevice **devp);
 fdt_addr_t dev_get_addr(struct udevice *dev);
 
 /**
+ * dev_get_addr() - Get the reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: reg address array index
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
+
+/**
  * device_has_children() - check if a device has any children
  *
  * @dev:	Device to check
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 04/16] dm: core: Add a new api to get indexed device address

[Simon Glass]

+Stephen

Hi,

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Add new api to get device address based on index.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/core/device.c | 16 ++++++++++++----
>  include/dm/device.h   | 10 ++++++++++
>  2 files changed, 22 insertions(+), 4 deletions(-)

You are touching critical core code so I think we need to be careful here.

>
> diff --git a/drivers/core/device.c b/drivers/core/device.c
> index 758f390..3cdcab5 100644
> --- a/drivers/core/device.c
> +++ b/drivers/core/device.c
> @@ -581,18 +581,21 @@ const char *dev_get_uclass_name(struct udevice *dev)
>         return dev->uclass->uc_drv->name;
>  }
>
> -fdt_addr_t dev_get_addr(struct udevice *dev)
> +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
>  {
>  #if CONFIG_IS_ENABLED(OF_CONTROL)
>         fdt_addr_t addr;
>
>         if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
>                 const fdt32_t *reg;
> +               int len = 0;
>
> -               reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
> -               if (!reg)
> +               reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
> +               if (!reg || (len <= (index * sizeof(fdt32_t) * 2)))
>                         return FDT_ADDR_T_NONE;
>
> +               reg += index * 2;
> +

This seems to be assuming that the address and size each occupy a
single cell, but that is not the case in general (e.g. with 64-bit
machines).

I think you need to call fdt_addr_cells() and fdt_size_cells(). See
fdtdec_get_addr_size_auto_parent() as an example.

>                 /*
>                  * Use the full-fledged translate function for complex
>                  * bus setups.
> @@ -608,7 +611,7 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
>         addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
>                                                 dev->parent->of_offset,
>                                                 dev->of_offset, "reg",
> -                                               0, NULL);
> +                                               index, NULL);
>         if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
>                 if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
>                         addr = simple_bus_translate(dev->parent, addr);
> @@ -620,6 +623,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
>  #endif
>  }
>
> +fdt_addr_t dev_get_addr(struct udevice *dev)
> +{
> +       return dev_get_addr_index(dev, 0);
> +}
> +
>  bool device_has_children(struct udevice *dev)
>  {
>         return !list_empty(&dev->child_head);
> diff --git a/include/dm/device.h b/include/dm/device.h
> index 28ba4ca..4de66d7 100644
> --- a/include/dm/device.h
> +++ b/include/dm/device.h
> @@ -454,6 +454,16 @@ int device_find_next_child(struct udevice **devp);
>  fdt_addr_t dev_get_addr(struct udevice *dev);
>
>  /**
> + * dev_get_addr() - Get the reg property of a device

dev_get_addr_index

> + *
> + * @dev: Pointer to a device
> + * @index: reg address array index

I don't think this is sufficiently clear. Can you add a comment saying
that the 'reg' property can hold a list of <addr, size> pairs and
@index is used to select which one is used?

> + *
> + * @return addr
> + */
> +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
> +
> +/**
>   * device_has_children() - check if a device has any children
>   *
>   * @dev:       Device to check
> --
> 2.6.2.280.g74301d6
>

Regards,
Simon

[U-Boot] [PATCH v2 04/16] dm: core: Add a new api to get indexed device address

[Mugunthan V N]

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
> +Stephen
> 
> Hi,
> 
> On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> Add new api to get device address based on index.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> ---
>>  drivers/core/device.c | 16 ++++++++++++----
>>  include/dm/device.h   | 10 ++++++++++
>>  2 files changed, 22 insertions(+), 4 deletions(-)
> 
> You are touching critical core code so I think we need to be careful here.
> 

Okay

>>
>> diff --git a/drivers/core/device.c b/drivers/core/device.c
>> index 758f390..3cdcab5 100644
>> --- a/drivers/core/device.c
>> +++ b/drivers/core/device.c
>> @@ -581,18 +581,21 @@ const char *dev_get_uclass_name(struct udevice *dev)
>>         return dev->uclass->uc_drv->name;
>>  }
>>
>> -fdt_addr_t dev_get_addr(struct udevice *dev)
>> +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
>>  {
>>  #if CONFIG_IS_ENABLED(OF_CONTROL)
>>         fdt_addr_t addr;
>>
>>         if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
>>                 const fdt32_t *reg;
>> +               int len = 0;
>>
>> -               reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
>> -               if (!reg)
>> +               reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
>> +               if (!reg || (len <= (index * sizeof(fdt32_t) * 2)))
>>                         return FDT_ADDR_T_NONE;
>>
>> +               reg += index * 2;
>> +
> 
> This seems to be assuming that the address and size each occupy a
> single cell, but that is not the case in general (e.g. with 64-bit
> machines).
> 
> I think you need to call fdt_addr_cells() and fdt_size_cells(). See
> fdtdec_get_addr_size_auto_parent() as an example.
> 

Okay, will use these in next version.

>>                 /*
>>                  * Use the full-fledged translate function for complex
>>                  * bus setups.
>> @@ -608,7 +611,7 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
>>         addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
>>                                                 dev->parent->of_offset,
>>                                                 dev->of_offset, "reg",
>> -                                               0, NULL);
>> +                                               index, NULL);
>>         if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
>>                 if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
>>                         addr = simple_bus_translate(dev->parent, addr);
>> @@ -620,6 +623,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
>>  #endif
>>  }
>>
>> +fdt_addr_t dev_get_addr(struct udevice *dev)
>> +{
>> +       return dev_get_addr_index(dev, 0);
>> +}
>> +
>>  bool device_has_children(struct udevice *dev)
>>  {
>>         return !list_empty(&dev->child_head);
>> diff --git a/include/dm/device.h b/include/dm/device.h
>> index 28ba4ca..4de66d7 100644
>> --- a/include/dm/device.h
>> +++ b/include/dm/device.h
>> @@ -454,6 +454,16 @@ int device_find_next_child(struct udevice **devp);
>>  fdt_addr_t dev_get_addr(struct udevice *dev);
>>
>>  /**
>> + * dev_get_addr() - Get the reg property of a device
> 
> dev_get_addr_index
> 
>> + *
>> + * @dev: Pointer to a device
>> + * @index: reg address array index
> 
> I don't think this is sufficiently clear. Can you add a comment saying
> that the 'reg' property can hold a list of <addr, size> pairs and
> @index is used to select which one is used?
> 

Will add more doc in next version

Regards
Mugunthan V N

[U-Boot] [PATCH v2 05/16] spi: Add support for dual and quad mode

[Mugunthan V N]

spi bus can support dual and quad wire data transfers for tx and
rx. So defining dual and quad modes for both tx and rx. Also add
support to parse bus width used for spi tx and rx transfers.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 drivers/spi/spi-uclass.c | 33 +++++++++++++++++++++++++++++++++
 include/spi.h            |  4 ++++
 2 files changed, 37 insertions(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 58388ef..be365e4 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -349,6 +349,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
 				 struct dm_spi_slave_platdata *plat)
 {
 	int mode = 0;
+	int value;
 
 	plat->cs = fdtdec_get_int(blob, node, "reg", -1);
 	plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
@@ -360,6 +361,38 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
 		mode |= SPI_CS_HIGH;
 	if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
 		mode |= SPI_PREAMBLE;
+
+	/* Device DUAL/QUAD mode */
+	value = fdtdec_get_int(blob, node, "spi-tx-bus-width", 1);
+	switch (value) {
+	case 1:
+		break;
+	case 2:
+		mode |= SPI_TX_DUAL;
+		break;
+	case 4:
+		mode |= SPI_TX_QUAD;
+		break;
+	default:
+		error("spi-tx-bus-width %d not supported\n", value);
+		break;
+	}
+
+	value = fdtdec_get_int(blob, node, "spi-rx-bus-width", 1);
+	switch (value) {
+	case 1:
+		break;
+	case 2:
+		mode |= SPI_RX_DUAL;
+		break;
+	case 4:
+		mode |= SPI_RX_QUAD;
+		break;
+	default:
+		error("spi-rx-bus-width %d not supported\n", value);
+		break;
+	}
+
 	plat->mode = mode;
 
 	return 0;
diff --git a/include/spi.h b/include/spi.h
index b4d2723..40dbb4d 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -23,6 +23,10 @@
 #define	SPI_LOOP	0x20			/* loopback mode */
 #define	SPI_SLAVE	0x40			/* slave mode */
 #define	SPI_PREAMBLE	0x80			/* Skip preamble bytes */
+#define	SPI_TX_DUAL	0x100			/* transmit with 2 wires */
+#define	SPI_TX_QUAD	0x200			/* transmit with 4 wires */
+#define	SPI_RX_DUAL	0x400			/* receive with 2 wires */
+#define	SPI_RX_QUAD	0x800			/* receive with 4 wires */
 
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN		0x01	/* Assert CS before transfer */
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 05/16] spi: Add support for dual and quad mode

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:13PM +0530, Mugunthan V N wrote:

> spi bus can support dual and quad wire data transfers for tx and
> rx. So defining dual and quad modes for both tx and rx. Also add
> support to parse bus width used for spi tx and rx transfers.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 05/16] spi: Add support for dual and quad mode

[Jagan Teki]

On 4 November 2015 at 13:46, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> spi bus can support dual and quad wire data transfers for tx and
> rx. So defining dual and quad modes for both tx and rx. Also add
> support to parse bus width used for spi tx and rx transfers.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>  drivers/spi/spi-uclass.c | 33 +++++++++++++++++++++++++++++++++
>  include/spi.h            |  4 ++++
>  2 files changed, 37 insertions(+)
>
> diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
> index 58388ef..be365e4 100644
> --- a/drivers/spi/spi-uclass.c
> +++ b/drivers/spi/spi-uclass.c
> @@ -349,6 +349,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
>                                  struct dm_spi_slave_platdata *plat)
>  {
>         int mode = 0;
> +       int value;
>
>         plat->cs = fdtdec_get_int(blob, node, "reg", -1);
>         plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
> @@ -360,6 +361,38 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
>                 mode |= SPI_CS_HIGH;
>         if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
>                 mode |= SPI_PREAMBLE;
> +
> +       /* Device DUAL/QUAD mode */
> +       value = fdtdec_get_int(blob, node, "spi-tx-bus-width", 1);

Value never be negative so better to use fdtdec_get_uint, comments?

> +       switch (value) {
> +       case 1:
> +               break;
> +       case 2:
> +               mode |= SPI_TX_DUAL;
> +               break;
> +       case 4:
> +               mode |= SPI_TX_QUAD;
> +               break;
> +       default:
> +               error("spi-tx-bus-width %d not supported\n", value);
> +               break;
> +       }
> +
> +       value = fdtdec_get_int(blob, node, "spi-rx-bus-width", 1);
> +       switch (value) {
> +       case 1:
> +               break;
> +       case 2:
> +               mode |= SPI_RX_DUAL;
> +               break;
> +       case 4:
> +               mode |= SPI_RX_QUAD;
> +               break;
> +       default:
> +               error("spi-rx-bus-width %d not supported\n", value);
> +               break;
> +       }
> +
>         plat->mode = mode;
>
>         return 0;
> diff --git a/include/spi.h b/include/spi.h
> index b4d2723..40dbb4d 100644
> --- a/include/spi.h
> +++ b/include/spi.h
> @@ -23,6 +23,10 @@
>  #define        SPI_LOOP        0x20                    /* loopback mode */
>  #define        SPI_SLAVE       0x40                    /* slave mode */
>  #define        SPI_PREAMBLE    0x80                    /* Skip preamble bytes */
> +#define        SPI_TX_DUAL     0x100                   /* transmit with 2 wires */
> +#define        SPI_TX_QUAD     0x200                   /* transmit with 4 wires */
> +#define        SPI_RX_DUAL     0x400                   /* receive with 2 wires */
> +#define        SPI_RX_QUAD     0x800                   /* receive with 4 wires */
>
>  /* SPI transfer flags */
>  #define SPI_XFER_BEGIN         0x01    /* Assert CS before transfer */
> --
> 2.6.2.280.g74301d6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
Jagan | openedev.

[U-Boot] [PATCH v2 06/16] dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

[Mugunthan V N]

Since spl doesn't support DM currently, do not define DM_SPI and
DM_SPI_FLASH for spl build.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 include/configs/dra7xx_evm.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 6e32de8..525dce7 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -131,6 +131,11 @@
 #define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
 #define CONFIG_QSPI_QUAD_SUPPORT
 
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
 /*
  * Default to using SPI for environment, etc.
  * 0x000000 - 0x010000 : QSPI.SPL (64KiB)
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 06/16] dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

[Simon Glass]

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Since spl doesn't support DM currently, do not define DM_SPI and
> DM_SPI_FLASH for spl build.

Do you mean 'Since OMAP's SPL doesn't support...'?

>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  include/configs/dra7xx_evm.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
> index 6e32de8..525dce7 100644
> --- a/include/configs/dra7xx_evm.h
> +++ b/include/configs/dra7xx_evm.h
> @@ -131,6 +131,11 @@
>  #define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
>  #define CONFIG_QSPI_QUAD_SUPPORT
>
> +#ifdef CONFIG_SPL_BUILD
> +#undef CONFIG_DM_SPI
> +#undef CONFIG_DM_SPI_FLASH
> +#endif
> +
>  /*
>   * Default to using SPI for environment, etc.
>   * 0x000000 - 0x010000 : QSPI.SPL (64KiB)
> --
> 2.6.2.280.g74301d6
>

Regards,
Simon

[U-Boot] [PATCH v2 06/16] dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

[Mugunthan V N]

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
> Hi Mugunthan,
> 
> On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> > Since spl doesn't support DM currently, do not define DM_SPI and
>> > DM_SPI_FLASH for spl build.
> Do you mean 'Since OMAP's SPL doesn't support...'?
> 

Right, for OMAP it is not supported. Will fix it in next version.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 07/16] dts: dra7: add spi alias for qspi

[Mugunthan V N]

add spi alias for qspi so that spi probes the device and driver
successfully.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/dts/dra7.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 8f1e25b..3060e9a 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -41,6 +41,7 @@
 		ethernet1 = &cpsw_emac1;
 		d_can0 = &dcan1;
 		d_can1 = &dcan2;
+		spi0 = &qspi;
 	};
 
 	timer {
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 07/16] dts: dra7: add spi alias for qspi

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:15PM +0530, Mugunthan V N wrote:

> add spi alias for qspi so that spi probes the device and driver
> successfully.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>  arch/arm/dts/dra7.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
> index 8f1e25b..3060e9a 100644
> --- a/arch/arm/dts/dra7.dtsi
> +++ b/arch/arm/dts/dra7.dtsi
> @@ -41,6 +41,7 @@
>  		ethernet1 = &cpsw_emac1;
>  		d_can0 = &dcan1;
>  		d_can1 = &dcan2;
> +		spi0 = &qspi;
>  	};
>  
>  	timer {

Is this upstream already?

-- 
Tom
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[U-Boot] [PATCH v2 08/16] drivers: spi: ti_qspi: convert driver to adopt device driver model

[Mugunthan V N]

adopt ti_qspi driver to device driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/spi/ti_qspi.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 172 insertions(+)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 003df80..fa86f4f 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -11,11 +11,14 @@
 #include <asm/arch/omap.h>
 #include <malloc.h>
 #include <spi.h>
+#include <dm.h>
 #include <asm/gpio.h>
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ti qpsi register bit masks */
 #define QSPI_TIMEOUT                    2000000
 #define QSPI_FCLK                       192000000
@@ -49,12 +52,14 @@
 #define CORE_CTRL_IO                    0x4a002558
 
 #define QSPI_CMD_READ                   (0x3 << 0)
+#define QSPI_CMD_READ_DUAL		(0x6b << 0)
 #define QSPI_CMD_READ_QUAD              (0x6b << 0)
 #define QSPI_CMD_READ_FAST              (0x0b << 0)
 #define QSPI_SETUP0_NUM_A_BYTES         (0x2 << 8)
 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
+#define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
 #define QSPI_CMD_WRITE                  (0x2 << 16)
 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
@@ -294,6 +299,8 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 }
 #endif
 
+#ifndef CONFIG_DM_SPI
+
 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
 {
 	return container_of(slave, struct ti_qspi_priv, slave);
@@ -407,3 +414,168 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	      priv->slave.bus, priv->slave.cs, bitlen, flags);
 	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
 }
+
+#else /* CONFIG_DM_SPI */
+
+static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
+				      struct spi_slave *slave,
+				      bool enable)
+{
+	u32 memval;
+	u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
+
+	if (!enable) {
+		writel(0, &priv->base->setup0);
+		return;
+	}
+
+	memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+
+	switch (mode) {
+	case SPI_RX_QUAD:
+		memval |= QSPI_CMD_READ_QUAD;
+		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+		memval |= QSPI_SETUP0_READ_QUAD;
+		slave->op_mode_rx = SPI_OPM_RX_QOF;
+		break;
+	case SPI_RX_DUAL:
+		memval |= QSPI_CMD_READ_DUAL;
+		memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+		memval |= QSPI_SETUP0_READ_DUAL;
+		break;
+	default:
+		memval |= QSPI_CMD_READ;
+		memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
+		memval |= QSPI_SETUP0_READ_NORMAL;
+		break;
+	}
+
+	writel(memval, &priv->base->setup0);
+}
+
+
+static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+{
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+	ti_spi_set_speed(priv, max_hz);
+
+	return 0;
+}
+
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+{
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+	return __ti_qspi_set_mode(priv, mode);
+}
+
+static int ti_qspi_claim_bus(struct udevice *dev)
+{
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	struct ti_qspi_priv *priv;
+	struct udevice *bus;
+
+	bus = dev->parent;
+	priv = dev_get_priv(bus);
+
+	__ti_qspi_setup_memorymap(priv, slave, true);
+
+	return __ti_qspi_claim_bus(priv, slave_plat->cs);
+}
+
+static int ti_qspi_release_bus(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	struct ti_qspi_priv *priv;
+	struct udevice *bus;
+
+	bus = dev->parent;
+	priv = dev_get_priv(bus);
+
+	__ti_qspi_setup_memorymap(priv, slave, false);
+	__ti_qspi_release_bus(priv);
+
+	return 0;
+}
+
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+			const void *dout, void *din, unsigned long flags)
+{
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	struct ti_qspi_priv *priv;
+	struct udevice *bus;
+
+	bus = dev->parent;
+	priv = dev_get_priv(bus);
+
+	return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+}
+
+static int ti_qspi_probe(struct udevice *bus)
+{
+	/* Nothing to do in probe */
+	return 0;
+}
+
+static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+	fdt_addr_t addr;
+
+	priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
+	priv->slave.memory_map = (void *)dev_get_addr_index(bus, 1);
+	addr = dev_get_addr_index(bus, 2);
+	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+
+	priv->slave.max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+					    -1);
+	if (priv->slave.max_hz < 0) {
+		debug("Error: Max frequency missing\n");
+		return -ENODEV;
+	}
+	priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
+	debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
+	      (int)priv->base, priv->slave.max_hz);
+
+	return 0;
+}
+
+static int ti_qspi_child_pre_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	struct udevice *bus = dev_get_parent(dev);
+	struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+	slave->memory_map = priv->slave.memory_map;
+	return 0;
+}
+
+static const struct dm_spi_ops ti_qspi_ops = {
+	.claim_bus	= ti_qspi_claim_bus,
+	.release_bus	= ti_qspi_release_bus,
+	.xfer		= ti_qspi_xfer,
+	.set_speed	= ti_qspi_set_speed,
+	.set_mode	= ti_qspi_set_mode,
+};
+
+static const struct udevice_id ti_qspi_ids[] = {
+	{ .compatible = "ti,dra7xxx-qspi" },
+	{ .compatible = "ti,am4372-qspi" },
+	{ }
+};
+
+U_BOOT_DRIVER(ti_qspi) = {
+	.name	= "ti_qspi",
+	.id	= UCLASS_SPI,
+	.of_match = ti_qspi_ids,
+	.ops	= &ti_qspi_ops,
+	.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
+	.probe	= ti_qspi_probe,
+	.child_pre_probe = ti_qspi_child_pre_probe,
+};
+#endif /* CONFIG_DM_SPI */
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 08/16] drivers: spi: ti_qspi: convert driver to adopt device driver model

[Simon Glass]

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> adopt ti_qspi driver to device driver model
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/spi/ti_qspi.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 172 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 08/16] drivers: spi: ti_qspi: convert driver to adopt device driver model

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:16PM +0530, Mugunthan V N wrote:

> adopt ti_qspi driver to device driver model
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Mugunthan V N]

Add qspi memory map and control module register maps to device tree.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/dts/dra7.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 3060e9a..7045c0f 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1104,8 +1104,8 @@
 
 		qspi: qspi at 4b300000 {
 			compatible = "ti,dra7xxx-qspi";
-			reg = <0x4b300000 0x100>;
-			reg-names = "qspi_base";
+			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
+			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "qspi";
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:

> Add qspi memory map and control module register maps to device tree.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>  arch/arm/dts/dra7.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
> index 3060e9a..7045c0f 100644
> --- a/arch/arm/dts/dra7.dtsi
> +++ b/arch/arm/dts/dra7.dtsi
> @@ -1104,8 +1104,8 @@
>  
>  		qspi: qspi at 4b300000 {
>  			compatible = "ti,dra7xxx-qspi";
> -			reg = <0x4b300000 0x100>;
> -			reg-names = "qspi_base";
> +			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
> +			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "qspi";

Is this already upstream?

-- 
Tom
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[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Mugunthan V N]

On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:
> On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:
> 
>> Add qspi memory map and control module register maps to device tree.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>>  arch/arm/dts/dra7.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
>> index 3060e9a..7045c0f 100644
>> --- a/arch/arm/dts/dra7.dtsi
>> +++ b/arch/arm/dts/dra7.dtsi
>> @@ -1104,8 +1104,8 @@
>>  
>>  		qspi: qspi at 4b300000 {
>>  			compatible = "ti,dra7xxx-qspi";
>> -			reg = <0x4b300000 0x100>;
>> -			reg-names = "qspi_base";
>> +			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
>> +			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
>>  			#address-cells = <1>;
>>  			#size-cells = <0>;
>>  			ti,hwmods = "qspi";
> 
> Is this already upstream?
> 

The documentation part is already upstreamed. Driver in kernel doesn't
support mmap mode yet so dt changes are not present. Vignesh has
submitted the mmap patches [1] and is under review.

[1]: https://lkml.org/lkml/2015/11/10/14

Regards
Mugunthan V N

[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Tom Rini]

On Thu, Nov 12, 2015 at 02:33:48PM +0530, Mugunthan V N wrote:
> On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:
> > On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:
> > 
> >> Add qspi memory map and control module register maps to device tree.
> >>
> >> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> >> Reviewed-by: Simon Glass <sjg@chromium.org>
> >> ---
> >>  arch/arm/dts/dra7.dtsi | 4 ++--
> >>  1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
> >> index 3060e9a..7045c0f 100644
> >> --- a/arch/arm/dts/dra7.dtsi
> >> +++ b/arch/arm/dts/dra7.dtsi
> >> @@ -1104,8 +1104,8 @@
> >>  
> >>  		qspi: qspi at 4b300000 {
> >>  			compatible = "ti,dra7xxx-qspi";
> >> -			reg = <0x4b300000 0x100>;
> >> -			reg-names = "qspi_base";
> >> +			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
> >> +			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
> >>  			#address-cells = <1>;
> >>  			#size-cells = <0>;
> >>  			ti,hwmods = "qspi";
> > 
> > Is this already upstream?
> > 
> 
> The documentation part is already upstreamed. Driver in kernel doesn't
> support mmap mode yet so dt changes are not present. Vignesh has
> submitted the mmap patches [1] and is under review.
> 
> [1]: https://lkml.org/lkml/2015/11/10/14

OK, and we can't even get the reg names part in the DT upstream until
then?

-- 
Tom
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[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Mugunthan V N]

On Thursday 12 November 2015 06:17 PM, Tom Rini wrote:
> On Thu, Nov 12, 2015 at 02:33:48PM +0530, Mugunthan V N wrote:
>> On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:
>>> On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:
>>>
>>>> Add qspi memory map and control module register maps to device tree.
>>>>
>>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>  arch/arm/dts/dra7.dtsi | 4 ++--
>>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
>>>> index 3060e9a..7045c0f 100644
>>>> --- a/arch/arm/dts/dra7.dtsi
>>>> +++ b/arch/arm/dts/dra7.dtsi
>>>> @@ -1104,8 +1104,8 @@
>>>>  
>>>>  		qspi: qspi at 4b300000 {
>>>>  			compatible = "ti,dra7xxx-qspi";
>>>> -			reg = <0x4b300000 0x100>;
>>>> -			reg-names = "qspi_base";
>>>> +			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
>>>> +			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
>>>>  			#address-cells = <1>;
>>>>  			#size-cells = <0>;
>>>>  			ti,hwmods = "qspi";
>>>
>>> Is this already upstream?
>>>
>>
>> The documentation part is already upstreamed. Driver in kernel doesn't
>> support mmap mode yet so dt changes are not present. Vignesh has
>> submitted the mmap patches [1] and is under review.
>>
>> [1]: https://lkml.org/lkml/2015/11/10/14
> 
> OK, and we can't even get the reg names part in the DT upstream until
> then?
> 

I don't think we can get reg names in the DT upstream separately. But
there shouldn't be any issues as there is documentation already present
in kernel and submitted kernel patch DT nodes are similar to what I have
submitted.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Tom Rini]

On Sat, Nov 14, 2015 at 01:01:45PM +0530, Mugunthan V N wrote:
> On Thursday 12 November 2015 06:17 PM, Tom Rini wrote:
> > On Thu, Nov 12, 2015 at 02:33:48PM +0530, Mugunthan V N wrote:
> >> On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:
> >>> On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:
> >>>
> >>>> Add qspi memory map and control module register maps to device tree.
> >>>>
> >>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> >>>> Reviewed-by: Simon Glass <sjg@chromium.org>
> >>>> ---
> >>>>  arch/arm/dts/dra7.dtsi | 4 ++--
> >>>>  1 file changed, 2 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
> >>>> index 3060e9a..7045c0f 100644
> >>>> --- a/arch/arm/dts/dra7.dtsi
> >>>> +++ b/arch/arm/dts/dra7.dtsi
> >>>> @@ -1104,8 +1104,8 @@
> >>>>  
> >>>>  		qspi: qspi at 4b300000 {
> >>>>  			compatible = "ti,dra7xxx-qspi";
> >>>> -			reg = <0x4b300000 0x100>;
> >>>> -			reg-names = "qspi_base";
> >>>> +			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
> >>>> +			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
> >>>>  			#address-cells = <1>;
> >>>>  			#size-cells = <0>;
> >>>>  			ti,hwmods = "qspi";
> >>>
> >>> Is this already upstream?
> >>>
> >>
> >> The documentation part is already upstreamed. Driver in kernel doesn't
> >> support mmap mode yet so dt changes are not present. Vignesh has
> >> submitted the mmap patches [1] and is under review.
> >>
> >> [1]: https://lkml.org/lkml/2015/11/10/14
> > 
> > OK, and we can't even get the reg names part in the DT upstream until
> > then?
> > 
> 
> I don't think we can get reg names in the DT upstream separately. But
> there shouldn't be any issues as there is documentation already present
> in kernel and submitted kernel patch DT nodes are similar to what I have
> submitted.

Similar or the same?  We'll be dropping in (and quick diff'ing) a new DT
from the kernel at some point in the future.  So if there's chance of
things changing, we want to wait.

-- 
Tom
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[U-Boot] [PATCH v2 09/16] arm: dts: dra7: add qspi register maps for memory map and control module

[Mugunthan V N]

On Monday 16 November 2015 07:43 AM, Tom Rini wrote:
> On Sat, Nov 14, 2015 at 01:01:45PM +0530, Mugunthan V N wrote:
>> On Thursday 12 November 2015 06:17 PM, Tom Rini wrote:
>>> On Thu, Nov 12, 2015 at 02:33:48PM +0530, Mugunthan V N wrote:
>>>> On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:
>>>>> On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:
>>>>>
>>>>>> Add qspi memory map and control module register maps to device tree.
>>>>>>
>>>>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>>>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>>>> ---
>>>>>>  arch/arm/dts/dra7.dtsi | 4 ++--
>>>>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
>>>>>> index 3060e9a..7045c0f 100644
>>>>>> --- a/arch/arm/dts/dra7.dtsi
>>>>>> +++ b/arch/arm/dts/dra7.dtsi
>>>>>> @@ -1104,8 +1104,8 @@
>>>>>>  
>>>>>>  		qspi: qspi at 4b300000 {
>>>>>>  			compatible = "ti,dra7xxx-qspi";
>>>>>> -			reg = <0x4b300000 0x100>;
>>>>>> -			reg-names = "qspi_base";
>>>>>> +			reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
>>>>>> +			reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
>>>>>>  			#address-cells = <1>;
>>>>>>  			#size-cells = <0>;
>>>>>>  			ti,hwmods = "qspi";
>>>>>
>>>>> Is this already upstream?
>>>>>
>>>>
>>>> The documentation part is already upstreamed. Driver in kernel doesn't
>>>> support mmap mode yet so dt changes are not present. Vignesh has
>>>> submitted the mmap patches [1] and is under review.
>>>>
>>>> [1]: https://lkml.org/lkml/2015/11/10/14
>>>
>>> OK, and we can't even get the reg names part in the DT upstream until
>>> then?
>>>
>>
>> I don't think we can get reg names in the DT upstream separately. But
>> there shouldn't be any issues as there is documentation already present
>> in kernel and submitted kernel patch DT nodes are similar to what I have
>> submitted.
> 
> Similar or the same?  We'll be dropping in (and quick diff'ing) a new DT
> from the kernel at some point in the future.  So if there's chance of
> things changing, we want to wait.
> 

Its Similar now, will make it Same in next version

Regards
Mugunthan V N

[U-Boot] [PATCH v2 10/16] drivers: mtd: spi: sf_probe: add compatible for spansion spi flash

[Mugunthan V N]

Add compatible for spansion 32MiB spi flash s25fl256s1.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/mtd/spi/sf_probe.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index c000c53..9cfa9b6 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
 
 static const struct udevice_id spi_flash_std_ids[] = {
 	{ .compatible = "spi-flash" },
+	{ .compatible = "s25fl256s1" },
 	{ }
 };
 
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 10/16] drivers: mtd: spi: sf_probe: add compatible for spansion spi flash

[Simon Glass]

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Add compatible for spansion 32MiB spi flash s25fl256s1.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/mtd/spi/sf_probe.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index c000c53..9cfa9b6 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
>
>  static const struct udevice_id spi_flash_std_ids[] = {
>         { .compatible = "spi-flash" },
> +       { .compatible = "s25fl256s1" },

Instead, is it possible to add "spi-flash" to the list of compatible
strings in your device tree?

>         { }
>  };
>
> --
> 2.6.2.280.g74301d6
>

Regards,
Simon

[U-Boot] [PATCH v2 10/16] drivers: mtd: spi: sf_probe: add compatible for spansion spi flash

[Mugunthan V N]

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
> Hi Mugunthan,
> 
> On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> Add compatible for spansion 32MiB spi flash s25fl256s1.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> ---
>>  drivers/mtd/spi/sf_probe.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>> index c000c53..9cfa9b6 100644
>> --- a/drivers/mtd/spi/sf_probe.c
>> +++ b/drivers/mtd/spi/sf_probe.c
>> @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
>>
>>  static const struct udevice_id spi_flash_std_ids[] = {
>>         { .compatible = "spi-flash" },
>> +       { .compatible = "s25fl256s1" },
> 
> Instead, is it possible to add "spi-flash" to the list of compatible
> strings in your device tree?
> 

The compatible "spi-flash" is not defined/documented in kernel and
compatible "s25fl256s1" is already documented and present in dt files.
So it will be good to follow the same dt compatibles in U-Boot so that
future merge/sync will be easier.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 10/16] drivers: mtd: spi: sf_probe: add compatible for spansion spi flash

[Tom Rini]

On Thu, Nov 12, 2015 at 02:42:41PM +0530, Mugunthan V N wrote:
> On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
> > Hi Mugunthan,
> > 
> > On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> >> Add compatible for spansion 32MiB spi flash s25fl256s1.
> >>
> >> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> >> ---
> >>  drivers/mtd/spi/sf_probe.c | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> >> index c000c53..9cfa9b6 100644
> >> --- a/drivers/mtd/spi/sf_probe.c
> >> +++ b/drivers/mtd/spi/sf_probe.c
> >> @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
> >>
> >>  static const struct udevice_id spi_flash_std_ids[] = {
> >>         { .compatible = "spi-flash" },
> >> +       { .compatible = "s25fl256s1" },
> > 
> > Instead, is it possible to add "spi-flash" to the list of compatible
> > strings in your device tree?
> > 
> 
> The compatible "spi-flash" is not defined/documented in kernel and
> compatible "s25fl256s1" is already documented and present in dt files.
> So it will be good to follow the same dt compatibles in U-Boot so that
> future merge/sync will be easier.

Agreed.

-- 
Tom
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[U-Boot] [PATCH v2 10/16] drivers: mtd: spi: sf_probe: add compatible for spansion spi flash

[Simon Glass]

Hi,

On 12 November 2015 at 05:48, Tom Rini <trini@konsulko.com> wrote:
> On Thu, Nov 12, 2015 at 02:42:41PM +0530, Mugunthan V N wrote:
>> On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
>> > Hi Mugunthan,
>> >
>> > On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> >> Add compatible for spansion 32MiB spi flash s25fl256s1.
>> >>
>> >> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> >> ---
>> >>  drivers/mtd/spi/sf_probe.c | 1 +
>> >>  1 file changed, 1 insertion(+)
>> >>
>> >> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>> >> index c000c53..9cfa9b6 100644
>> >> --- a/drivers/mtd/spi/sf_probe.c
>> >> +++ b/drivers/mtd/spi/sf_probe.c
>> >> @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
>> >>
>> >>  static const struct udevice_id spi_flash_std_ids[] = {
>> >>         { .compatible = "spi-flash" },
>> >> +       { .compatible = "s25fl256s1" },
>> >
>> > Instead, is it possible to add "spi-flash" to the list of compatible
>> > strings in your device tree?
>> >
>>
>> The compatible "spi-flash" is not defined/documented in kernel and
>> compatible "s25fl256s1" is already documented and present in dt files.
>> So it will be good to follow the same dt compatibles in U-Boot so that
>> future merge/sync will be easier.
>
> Agreed.

I see this in kernel upstream at present:

git grep s25fl256s1
arch/arm/boot/dts/dra7-evm.dts:         compatible = "s25fl256s1";
arch/arm/boot/dts/dra72-evm.dts:                compatible = "s25fl256s1";
arch/arm/boot/dts/qcom-ipq8064-ap148.dts:
         compatible = "s25fl256s1";
arch/powerpc/boot/dts/fsl/kmcoge4.dts:
compatible = "spansion,s25fl256s1";
drivers/mtd/devices/m25p80.c:   {"s25fl256s1"}, {"s25fl512s"},
{"s25sl12801"}, {"s25fl008k"},
drivers/mtd/devices/st_spi_fsm.c:       { "s25fl256s1", 0x010219,
0x4d01,  64 * 1024, 512,
drivers/mtd/spi-nor/spi-nor.c:  { "s25fl256s1", INFO(0x010219, 0x4d01,
 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

There seems to be some confusion as to whether to include "spansion"
or not. I feel it should be included.

The problem is that in U-Boot at present this compatible string does
not affect any behaviour. We still scan the chip to figure out its
type from its ID. Do you want to add a .data value for it, and skip
the probing, or are you just trying to trigger the driver to bind?

Regards,
Simon

[U-Boot] [PATCH v2 10/16] drivers: mtd: spi: sf_probe: add compatible for spansion spi flash

[Mugunthan V N]

On Tuesday 17 November 2015 02:38 AM, Simon Glass wrote:
> Hi,
> 
> On 12 November 2015 at 05:48, Tom Rini <trini@konsulko.com> wrote:
>> On Thu, Nov 12, 2015 at 02:42:41PM +0530, Mugunthan V N wrote:
>>> On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
>>>> Hi Mugunthan,
>>>>
>>>> On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>>>>> Add compatible for spansion 32MiB spi flash s25fl256s1.
>>>>>
>>>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>>>>> ---
>>>>>  drivers/mtd/spi/sf_probe.c | 1 +
>>>>>  1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
>>>>> index c000c53..9cfa9b6 100644
>>>>> --- a/drivers/mtd/spi/sf_probe.c
>>>>> +++ b/drivers/mtd/spi/sf_probe.c
>>>>> @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
>>>>>
>>>>>  static const struct udevice_id spi_flash_std_ids[] = {
>>>>>         { .compatible = "spi-flash" },
>>>>> +       { .compatible = "s25fl256s1" },
>>>>
>>>> Instead, is it possible to add "spi-flash" to the list of compatible
>>>> strings in your device tree?
>>>>
>>>
>>> The compatible "spi-flash" is not defined/documented in kernel and
>>> compatible "s25fl256s1" is already documented and present in dt files.
>>> So it will be good to follow the same dt compatibles in U-Boot so that
>>> future merge/sync will be easier.
>>
>> Agreed.
> 
> I see this in kernel upstream at present:
> 
> git grep s25fl256s1
> arch/arm/boot/dts/dra7-evm.dts:         compatible = "s25fl256s1";
> arch/arm/boot/dts/dra72-evm.dts:                compatible = "s25fl256s1";
> arch/arm/boot/dts/qcom-ipq8064-ap148.dts:
>          compatible = "s25fl256s1";
> arch/powerpc/boot/dts/fsl/kmcoge4.dts:
> compatible = "spansion,s25fl256s1";
> drivers/mtd/devices/m25p80.c:   {"s25fl256s1"}, {"s25fl512s"},
> {"s25sl12801"}, {"s25fl008k"},
> drivers/mtd/devices/st_spi_fsm.c:       { "s25fl256s1", 0x010219,
> 0x4d01,  64 * 1024, 512,
> drivers/mtd/spi-nor/spi-nor.c:  { "s25fl256s1", INFO(0x010219, 0x4d01,
>  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> 
> There seems to be some confusion as to whether to include "spansion"
> or not. I feel it should be included.
> 
> The problem is that in U-Boot at present this compatible string does
> not affect any behaviour. We still scan the chip to figure out its
> type from its ID. Do you want to add a .data value for it, and skip
> the probing, or are you just trying to trigger the driver to bind?
> 

These compatibles are just used to bind the driver as spi-flash
compatible is not present/documented in Kernel.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 11/16] drivers: mtd: spi: sf_probe: add compatible for Macronix spi flash

[Mugunthan V N]

Add compatible for Macronix 64MiB spi flash mx66l51235l.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 drivers/mtd/spi/sf_probe.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 9cfa9b6..b16a392 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -503,6 +503,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
 static const struct udevice_id spi_flash_std_ids[] = {
 	{ .compatible = "spi-flash" },
 	{ .compatible = "s25fl256s1" },
+	{ .compatible = "mx66l51235l" },
 	{ }
 };
 
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 11/16] drivers: mtd: spi: sf_probe: add compatible for Macronix spi flash

[Simon Glass]

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Add compatible for Macronix 64MiB spi flash mx66l51235l.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  drivers/mtd/spi/sf_probe.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index 9cfa9b6..b16a392 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -503,6 +503,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {
>  static const struct udevice_id spi_flash_std_ids[] = {
>         { .compatible = "spi-flash" },
>         { .compatible = "s25fl256s1" },
> +       { .compatible = "mx66l51235l" },

Can you add "spi-flash" to your device tree file instead?

>         { }
>  };
>
> --
> 2.6.2.280.g74301d6
>

Regards,
Simon

[U-Boot] [PATCH v2 12/16] defconfig: dra72_evm: enable spi driver model

[Mugunthan V N]

enable mmc driver model for dra72_evm as ti_qspi supports
driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 configs/dra72_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index cce3255..d88b2b7 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -16,3 +16,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 12/16] defconfig: dra72_evm: enable spi driver model

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:20PM +0530, Mugunthan V N wrote:

> enable mmc driver model for dra72_evm as ti_qspi supports
> driver model
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 13/16] defconfig: dra74_evm: enable spi driver model

[Mugunthan V N]

enable mmc driver model for dra74_evm as ti_qspi supports
driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 configs/dra74_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index a57cd7f..b7c541b 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -15,3 +15,5 @@ CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 13/16] defconfig: dra74_evm: enable spi driver model

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:21PM +0530, Mugunthan V N wrote:

> enable mmc driver model for dra74_evm as ti_qspi supports
> driver model
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 14/16] am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

[Mugunthan V N]

Since spl doesn't support DM currently, do not define DM_SPI and
DM_SPI_FLASH for spl build.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 include/configs/am43xx_evm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index d93e3e7..1258492 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -146,6 +146,8 @@
  */
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
 #endif
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 14/16] am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

[Simon Glass]

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Since spl doesn't support DM currently, do not define DM_SPI and
> DM_SPI_FLASH for spl build.

Since spl doesn't support DM currently on OMAP?

It is supported in general, right?

>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> ---
>  include/configs/am43xx_evm.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
> index d93e3e7..1258492 100644
> --- a/include/configs/am43xx_evm.h
> +++ b/include/configs/am43xx_evm.h
> @@ -146,6 +146,8 @@
>   */
>  #ifdef CONFIG_SPL_BUILD
>  #undef CONFIG_DM_MMC
> +#undef CONFIG_DM_SPI
> +#undef CONFIG_DM_SPI_FLASH
>  #endif
>
>  #ifndef CONFIG_SPL_BUILD
> --
> 2.6.2.280.g74301d6
>

Regards,
Simon

[U-Boot] [PATCH v2 14/16] am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl

[Mugunthan V N]

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:
> Hi Mugunthan,
> 
> On 4 November 2015 at 01:16, Mugunthan V N <mugunthanvnm@ti.com> wrote:
>> > Since spl doesn't support DM currently, do not define DM_SPI and
>> > DM_SPI_FLASH for spl build.
> Since spl doesn't support DM currently on OMAP?
> 
> It is supported in general, right?
> 

Right, it is supported in general only for OMAP it is not supported.
Will fix it in next version.

Regards
Mugunthan V N

[U-Boot] [PATCH v2 15/16] arm: dts: am4372: add qspi register maps for memory map

[Mugunthan V N]

Add qspi memory map address to device tree.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/dts/am4372.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index ade28c7..1b30d53 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -25,6 +25,7 @@
 		serial0 = &uart0;
 		ethernet0 = &cpsw_emac0;
 		ethernet1 = &cpsw_emac1;
+		spi0 = &qspi;
 	};
 
 	cpus {
@@ -902,7 +903,8 @@
 
 		qspi: qspi at 47900000 {
 			compatible = "ti,am4372-qspi";
-			reg = <0x47900000 0x100>;
+			reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
+			reg-names = "qspi_base", "qspi_mmap";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "qspi";
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 15/16] arm: dts: am4372: add qspi register maps for memory map

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:23PM +0530, Mugunthan V N wrote:
> Add qspi memory map address to device tree.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>  arch/arm/dts/am4372.dtsi | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
> index ade28c7..1b30d53 100644
> --- a/arch/arm/dts/am4372.dtsi
> +++ b/arch/arm/dts/am4372.dtsi
> @@ -25,6 +25,7 @@
>  		serial0 = &uart0;
>  		ethernet0 = &cpsw_emac0;
>  		ethernet1 = &cpsw_emac1;
> +		spi0 = &qspi;
>  	};
>  
>  	cpus {
> @@ -902,7 +903,8 @@
>  
>  		qspi: qspi at 47900000 {
>  			compatible = "ti,am4372-qspi";
> -			reg = <0x47900000 0x100>;
> +			reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
> +			reg-names = "qspi_base", "qspi_mmap";
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			ti,hwmods = "qspi";

Is this upstream already?

-- 
Tom
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[U-Boot] [PATCH v2 15/16] arm: dts: am4372: add qspi register maps for memory map

[Mugunthan V N]

On Sunday 08 November 2015 07:02 PM, Tom Rini wrote:
> On Wed, Nov 04, 2015 at 01:46:23PM +0530, Mugunthan V N wrote:
>> Add qspi memory map address to device tree.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>>  arch/arm/dts/am4372.dtsi | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
>> index ade28c7..1b30d53 100644
>> --- a/arch/arm/dts/am4372.dtsi
>> +++ b/arch/arm/dts/am4372.dtsi
>> @@ -25,6 +25,7 @@
>>  		serial0 = &uart0;
>>  		ethernet0 = &cpsw_emac0;
>>  		ethernet1 = &cpsw_emac1;
>> +		spi0 = &qspi;
>>  	};
>>  
>>  	cpus {
>> @@ -902,7 +903,8 @@
>>  
>>  		qspi: qspi at 47900000 {
>>  			compatible = "ti,am4372-qspi";
>> -			reg = <0x47900000 0x100>;
>> +			reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
>> +			reg-names = "qspi_base", "qspi_mmap";
>>  			#address-cells = <1>;
>>  			#size-cells = <0>;
>>  			ti,hwmods = "qspi";
> 
> Is this upstream already?
> 

The documentation part is already upstreamed. Driver in kernel doesn't
support mmap mode yet, so dt changes are not present. Vignesh has
submitted the mmap patches [1] and is under review.

[1]: https://lkml.org/lkml/2015/11/10/14

Regards
Mugunthan V N

[U-Boot] [PATCH v2 16/16] defconfig: am437x_sk_evm: enable spi driver model

[Mugunthan V N]

enable mmc driver model for am437x_sk_evm as ti_qspi supports
driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 configs/am437x_sk_evm_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 02485f8..ba0ab84 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -15,3 +15,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_MMC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
-- 
2.6.2.280.g74301d6

[U-Boot] [PATCH v2 16/16] defconfig: am437x_sk_evm: enable spi driver model

[Tom Rini]

On Wed, Nov 04, 2015 at 01:46:24PM +0530, Mugunthan V N wrote:

> enable mmc driver model for am437x_sk_evm as ti_qspi supports
> driver model
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 16/16] defconfig: am437x_sk_evm: enable spi driver model

[Jagan Teki]

On 4 November 2015 at 13:46, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> enable mmc driver model for am437x_sk_evm as ti_qspi supports

typo its should be spi not mmc.

> driver model
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>  configs/am437x_sk_evm_defconfig | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
> index 02485f8..ba0ab84 100644
> --- a/configs/am437x_sk_evm_defconfig
> +++ b/configs/am437x_sk_evm_defconfig
> @@ -15,3 +15,6 @@ CONFIG_SPI_FLASH=y
>  CONFIG_DM_GPIO=y
>  CONFIG_DM_SERIAL=y
>  CONFIG_DM_MMC=y
> +CONFIG_DM_SPI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> --
> 2.6.2.280.g74301d6
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
Jagan | openedev.