From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67636C4CEC6 for ; Thu, 12 Sep 2019 17:04:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4728F20CC7 for ; Thu, 12 Sep 2019 17:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731054AbfILRER (ORCPT ); Thu, 12 Sep 2019 13:04:17 -0400 Received: from mga17.intel.com ([192.55.52.151]:13838 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728286AbfILRER (ORCPT ); Thu, 12 Sep 2019 13:04:17 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Sep 2019 10:04:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,492,1559545200"; d="scan'208";a="190048964" Received: from yoojae-mobl1.amr.corp.intel.com (HELO [10.7.153.148]) ([10.7.153.148]) by orsmga006.jf.intel.com with ESMTP; 12 Sep 2019 10:04:16 -0700 Subject: Re: [PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic To: Andrew Jeffery , Eddie James , Mauro Carvalho Chehab , Joel Stanley Cc: linux-aspeed@lists.ozlabs.org, linux-media@vger.kernel.org, openbmc@lists.ozlabs.org References: <20190910190756.31432-1-jae.hyun.yoo@linux.intel.com> <20190910190756.31432-2-jae.hyun.yoo@linux.intel.com> From: Jae Hyun Yoo Message-ID: <564501a5-f4db-b1ed-76b5-9e76c29aa7d4@linux.intel.com> Date: Thu, 12 Sep 2019 10:04:16 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Hi Andrew, On 9/11/2019 10:33 PM, Andrew Jeffery wrote: > On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote: >> This commit refines hsync/vsync polarity setting logic by making >> also clearing register bits possible based on probed sync state >> accordingly. > > That was tough to parse, but I think I understand. Trying to rephrase: > > Enable clearing of hsync/vsync plarity bits based on probed sync state. Correct. > What was the issue that drove the change? Do you know why it was done > the way it was prior to this patch? Because this driver detects weird resolutions sometimes. Investigated that it uses aspeed_video_update(video, VE_CTRL, 0, ctrl); so only setting of polarity bits is available. Means that clearing of the bits isn't available so it can't set back the polarities to normal. To fix the issue, this patch makes it use aspeed_video_write(video, VE_CTRL, ctrl); instead of above one with adding bit masking code changes. Thanks, Jae