From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Jan Beulich" <JBeulich@suse.com>
Subject: Re: [PATCH] ns16550: limit mapped MMIO size
Date: Tue, 17 Nov 2015 03:19:26 -0700
Message-ID: <564B0D3E02000078000B5C76@prv-mh.provo.novell.com>
References: <5644C3E002000078000B4594@prv-mh.provo.novell.com>
	<1447692731.27871.116.camel@citrix.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
Received: from mail6.bemta14.messagelabs.com ([193.109.254.103])
	by lists.xen.org with esmtp (Exim 4.72)
	(envelope-from <JBeulich@suse.com>) id 1ZydML-00064E-RE
	for xen-devel@lists.xenproject.org; Tue, 17 Nov 2015 10:19:33 +0000
In-Reply-To: <1447692731.27871.116.camel@citrix.com>
Content-Disposition: inline
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Ian Campbell <ian.campbell@citrix.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>, Keir Fraser <keir@xen.org>, Ian Jackson <Ian.Jackson@eu.citrix.com>, TimDeegan <tim@xen.org>
List-Id: xen-devel@lists.xenproject.org

>>> On 16.11.15 at 17:52, <ian.campbell@citrix.com> wrote:
> On Thu, 2015-11-12 at 08:52 -0700, Jan Beulich wrote:
>> There's no point in mapping more than the memory we actually may need
>> to touch, and in fact the too large region could actually extend into
>> another device's one (which currently is benign on x86 since only a
>> single page gets mapped anyway, but which is a latent bug on ARM
>> whenever PCI support gets enabled there).
>> 
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>> 
>> --- a/xen/drivers/char/ns16550.c
>> +++ b/xen/drivers/char/ns16550.c
>> @@ -931,6 +931,8 @@ pci_uart_config (struct ns16550 *uart, i
>>                          uart->io_base += bar_idx *
>> uart_param[p].uart_offset;
>>                          if ( uart_param[p].base_baud )
>>                              uart->clock_hz = uart_param[p].base_baud *
>> 16;
>> +                        size = max(8U << uart_param[p].reg_shift,
>> +                                   uart_param[p].uart_offset);
> 
> I assume 8 bytes (suitably shifted as above) corresponds to the "need to
> touch" set of registers, but I can't fathom the link to uart_offset, rather
> than uart_offset + those 8 bytes or something like that.

uart_offset represents the range of I/O-ports or MMIO that individual
ports are apart. Since advanced functionality may require access to
more than the legacy 8 registers range, and since everything is part of
a single BAR, it seems appropriate to use the maximum of the two
values.

Jan