From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759722AbbKTKs0 (ORCPT ); Fri, 20 Nov 2015 05:48:26 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:43248 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759683AbbKTKsX (ORCPT ); Fri, 20 Nov 2015 05:48:23 -0500 Subject: Re: [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain To: Thomas Gleixner References: <1446549181-31788-1-git-send-email-qais.yousef@imgtec.com> <1446549181-31788-11-git-send-email-qais.yousef@imgtec.com> <56407F3C.4060404@imgtec.com> CC: , , , , , From: Qais Yousef Message-ID: <564EFA74.90606@imgtec.com> Date: Fri, 20 Nov 2015 10:48:20 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.154.94] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thomas, On 11/16/2015 05:17 PM, Thomas Gleixner wrote: > 1) IPI as per_cpu interrupts > > Single hwirq represented by a single irq descriptor > > 2) IPI with consecutive mapping space > > No extra mapping from virq base to target cpu required as its just > linear. Everything can be handled via the base virq. > I think I am seeing a major issue with this approach. Take the case where we reserve an IPI with ipi_mask that has cpu 5 and 6 set only. When allocating a per_cpu or consectuve mapping, we will require 2 consecutive virqs and hwirqs. But since the cpu location is not starting from 0, we can't use the cpu as an offset anymore. So when a user wants to send an IPI to cpu 6 only, the code can't easily tell what's the correct offset from base virq or hwirq to use. Same applies when doing the reverse mapping. In other words, the ipi_mask won't always necessarily be linear to facilitate the 1:1 mapping that this approach assumes. It is a solvable problem, but I think we're losing the elegance that promoted going into this direction and I think sticking to using struct ipi_mapping (with some enhancements to how it's exposed an integrated by/into generic code) is a better approach. Thoughts? I still don't have a working implementation otherwise I would have sent my patches, but I thought I'd raise this up before I spend more time on it unnecessarily. Thanks, Qais From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:16104 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27012943AbbKTKs1jw5TP (ORCPT ); Fri, 20 Nov 2015 11:48:27 +0100 Subject: Re: [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain References: <1446549181-31788-1-git-send-email-qais.yousef@imgtec.com> <1446549181-31788-11-git-send-email-qais.yousef@imgtec.com> <56407F3C.4060404@imgtec.com> From: Qais Yousef Message-ID: <564EFA74.90606@imgtec.com> Date: Fri, 20 Nov 2015 10:48:20 +0000 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Thomas Gleixner Cc: linux-kernel@vger.kernel.org, jason@lakedaemon.net, marc.zyngier@arm.com, jiang.liu@linux.intel.com, ralf@linux-mips.org, linux-mips@linux-mips.org Message-ID: <20151120104820.TjqS4ZCsR3CzJC50IRf6jZy0XmXpwFjoyuTZcXopf0I@z> Hi Thomas, On 11/16/2015 05:17 PM, Thomas Gleixner wrote: > 1) IPI as per_cpu interrupts > > Single hwirq represented by a single irq descriptor > > 2) IPI with consecutive mapping space > > No extra mapping from virq base to target cpu required as its just > linear. Everything can be handled via the base virq. > I think I am seeing a major issue with this approach. Take the case where we reserve an IPI with ipi_mask that has cpu 5 and 6 set only. When allocating a per_cpu or consectuve mapping, we will require 2 consecutive virqs and hwirqs. But since the cpu location is not starting from 0, we can't use the cpu as an offset anymore. So when a user wants to send an IPI to cpu 6 only, the code can't easily tell what's the correct offset from base virq or hwirq to use. Same applies when doing the reverse mapping. In other words, the ipi_mask won't always necessarily be linear to facilitate the 1:1 mapping that this approach assumes. It is a solvable problem, but I think we're losing the elegance that promoted going into this direction and I think sticking to using struct ipi_mapping (with some enhancements to how it's exposed an integrated by/into generic code) is a better approach. Thoughts? I still don't have a working implementation otherwise I would have sent my patches, but I thought I'd raise this up before I spend more time on it unnecessarily. Thanks, Qais