From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932127AbbKWTAj (ORCPT ); Mon, 23 Nov 2015 14:00:39 -0500 Received: from proxima.lp0.eu ([81.2.80.65]:42655 "EHLO proxima.lp0.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751916AbbKWTAg (ORCPT ); Mon, 23 Nov 2015 14:00:36 -0500 Subject: Re: [PATCH 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk To: Florian Fainelli , Jonas Gorski References: <5650BFD6.5030700@simon.arlott.org.uk> <5650C08C.6090300@simon.arlott.org.uk> <5650E2FA.6090408@roeck-us.net> <5650E5BB.6020404@simon.arlott.org.uk> <56512937.6030903@roeck-us.net> <5651CB13.4090704@simon.arlott.org.uk> <5651CC3C.5090200@simon.arlott.org.uk> <565358AF.2090609@gmail.com> Cc: Guenter Roeck , "devicetree@vger.kernel.org" , Ralf Baechle , Thomas Gleixner , Jason Cooper , Marc Zyngier , Kevin Cernekee , Wim Van Sebroeck , Maxime Bizon , Linux Kernel Mailing List , MIPS Mailing List , linux-watchdog@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala From: Simon Arlott Message-ID: <5653624C.3030101@simon.arlott.org.uk> Date: Mon, 23 Nov 2015 19:00:28 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <565358AF.2090609@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/11/15 18:19, Florian Fainelli wrote: > On 23/11/15 07:02, Jonas Gorski wrote: >> On Sun, Nov 22, 2015 at 3:07 PM, Simon Arlott wrote: >>> -#define WDT_HZ 50000000 /* Fclk */ >>> +#define WDT_CLK_NAME "periph" >> >> @Florian: >> Is this correct? The comment for the watchdog in 6358_map_part.h and >> earlier claims that the clock is 40 MHz there, but the code uses 50MHz >> - is this a bug in the comments or is it a bug taken over from the >> original broadcom code? I'm sure that the periph clock being 50 MHz >> even on the older chips is correct, else we'd have noticed that in >> serial output (where it's also used). > > There are references to a Fbus2 clock in documentation, but I could not > find any actual documentation for its actual clock frequency, I would be > surprised if this chip would have diverged from the previous and future > ones and used a 40Mhz clock. 6345 started with a peripheral clock > running at 50Mhz, and that is true for all chips since then AFAICT. > > I agree we would have noticed this with the UART or SPI controllers if > that was not true, so probably a code glitch here... I've tested both the timer and the watchdog and they give near perfect time intervals (within 1-2ms based on printk times over serial) so it'd be obvious if they were out by 25%. -- Simon Arlott From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Arlott Subject: Re: [PATCH 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk Date: Mon, 23 Nov 2015 19:00:28 +0000 Message-ID: <5653624C.3030101@simon.arlott.org.uk> References: <5650BFD6.5030700@simon.arlott.org.uk> <5650C08C.6090300@simon.arlott.org.uk> <5650E2FA.6090408@roeck-us.net> <5650E5BB.6020404@simon.arlott.org.uk> <56512937.6030903@roeck-us.net> <5651CB13.4090704@simon.arlott.org.uk> <5651CC3C.5090200@simon.arlott.org.uk> <565358AF.2090609@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <565358AF.2090609-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: linux-watchdog-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Florian Fainelli , Jonas Gorski Cc: Guenter Roeck , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Ralf Baechle , Thomas Gleixner , Jason Cooper , Marc Zyngier , Kevin Cernekee , Wim Van Sebroeck , Maxime Bizon , Linux Kernel Mailing List , MIPS Mailing List , linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala List-Id: devicetree@vger.kernel.org On 23/11/15 18:19, Florian Fainelli wrote: > On 23/11/15 07:02, Jonas Gorski wrote: >> On Sun, Nov 22, 2015 at 3:07 PM, Simon Arlott wrote: >>> -#define WDT_HZ 50000000 /* Fclk */ >>> +#define WDT_CLK_NAME "periph" >> >> @Florian: >> Is this correct? The comment for the watchdog in 6358_map_part.h and >> earlier claims that the clock is 40 MHz there, but the code uses 50MHz >> - is this a bug in the comments or is it a bug taken over from the >> original broadcom code? I'm sure that the periph clock being 50 MHz >> even on the older chips is correct, else we'd have noticed that in >> serial output (where it's also used). > > There are references to a Fbus2 clock in documentation, but I could not > find any actual documentation for its actual clock frequency, I would be > surprised if this chip would have diverged from the previous and future > ones and used a 40Mhz clock. 6345 started with a peripheral clock > running at 50Mhz, and that is true for all chips since then AFAICT. > > I agree we would have noticed this with the UART or SPI controllers if > that was not true, so probably a code glitch here... I've tested both the timer and the watchdog and they give near perfect time intervals (within 1-2ms based on printk times over serial) so it'd be obvious if they were out by 25%. -- Simon Arlott -- To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html