From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a2HwC-0003no-4v for qemu-devel@nongnu.org; Fri, 27 Nov 2015 07:15:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a2Hw8-0008Og-4A for qemu-devel@nongnu.org; Fri, 27 Nov 2015 07:15:40 -0500 References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-3-git-send-email-benh@kernel.crashing.org> <5658309A.1000904@suse.de> From: Paolo Bonzini Message-ID: <56584963.8090800@redhat.com> Date: Fri, 27 Nov 2015 13:15:31 +0100 MIME-Version: 1.0 In-Reply-To: <5658309A.1000904@suse.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/77] ppc: Use split I/D mmu modes to avoid flushes on interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf , Benjamin Herrenschmidt , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org On 27/11/2015 11:29, Alexander Graf wrote: > > We rework the way the MMU indices are calculated, providing separate > > indices for I and D side based on MSR:IR and MSR:DR respectively, > > and thus no longer need to flush the TLB on context changes. This also > > adds correct support for HV as a separate address space. > > > > Signed-off-by: Benjamin Herrenschmidt > > Paolo had a patch set poking at the same places a while back to speed up > the ppc target by almost 10%. > > Paolo, what happened to those patches? Would you prefer to rebase them > on top of the HV bits or have Ben look into them while he's at it anyway? ;) Ben decided to do it this way, which avoids a proliferation of MMU modes. The net effect of his patches is the same if not better. Paolo