From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757227AbbLAWUp (ORCPT ); Tue, 1 Dec 2015 17:20:45 -0500 Received: from mail-pa0-f51.google.com ([209.85.220.51]:36128 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757133AbbLAWUm (ORCPT ); Tue, 1 Dec 2015 17:20:42 -0500 Message-ID: <565E1D38.7020906@linaro.org> Date: Tue, 01 Dec 2015 14:20:40 -0800 From: "Shi, Yang" User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: ast@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, davem@davemloft.net CC: zlim.lnx@gmail.com, xi.wang@gmail.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org Subject: Re: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction References: <1448922247-5692-1-git-send-email-yang.shi@linaro.org> In-Reply-To: <1448922247-5692-1-git-send-email-yang.shi@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/30/2015 2:24 PM, Yang Shi wrote: > aarch64 doesn't have native store immediate instruction, such operation > has to be implemented by the below instruction sequence: > > Load immediate to register > Store register > > Signed-off-by: Yang Shi > CC: Zi Shen Lim Had email exchange offline with Zi Shen Lim since he is traveling and cannot send text-only mail, quoted below for his reply: "I've given reviewed-by in response to original posting. Unless something has changed, feel free to add it." Since there is nothing changed, added his reviewed-by. Reviewed-by: Zi Shen Lim Thanks, Yang > CC: Xi Wang > --- > Thsi patch might be buried by the storm of xadd discussion, however, it is > absolutely irrelevent to xadd, so resend the patch itself. > > arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c > index 6809647..49c1f1b 100644 > --- a/arch/arm64/net/bpf_jit_comp.c > +++ b/arch/arm64/net/bpf_jit_comp.c > @@ -563,7 +563,25 @@ emit_cond_jmp: > case BPF_ST | BPF_MEM | BPF_H: > case BPF_ST | BPF_MEM | BPF_B: > case BPF_ST | BPF_MEM | BPF_DW: > - goto notyet; > + /* Load imm to a register then store it */ > + ctx->tmp_used = 1; > + emit_a64_mov_i(1, tmp2, off, ctx); > + emit_a64_mov_i(1, tmp, imm, ctx); > + switch (BPF_SIZE(code)) { > + case BPF_W: > + emit(A64_STR32(tmp, dst, tmp2), ctx); > + break; > + case BPF_H: > + emit(A64_STRH(tmp, dst, tmp2), ctx); > + break; > + case BPF_B: > + emit(A64_STRB(tmp, dst, tmp2), ctx); > + break; > + case BPF_DW: > + emit(A64_STR64(tmp, dst, tmp2), ctx); > + break; > + } > + break; > > /* STX: *(size *)(dst + off) = src */ > case BPF_STX | BPF_MEM | BPF_W: > From mboxrd@z Thu Jan 1 00:00:00 1970 From: yang.shi@linaro.org (Shi, Yang) Date: Tue, 01 Dec 2015 14:20:40 -0800 Subject: [RESEND PATCH] arm64: bpf: add 'store immediate' instruction In-Reply-To: <1448922247-5692-1-git-send-email-yang.shi@linaro.org> References: <1448922247-5692-1-git-send-email-yang.shi@linaro.org> Message-ID: <565E1D38.7020906@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 11/30/2015 2:24 PM, Yang Shi wrote: > aarch64 doesn't have native store immediate instruction, such operation > has to be implemented by the below instruction sequence: > > Load immediate to register > Store register > > Signed-off-by: Yang Shi > CC: Zi Shen Lim Had email exchange offline with Zi Shen Lim since he is traveling and cannot send text-only mail, quoted below for his reply: "I've given reviewed-by in response to original posting. Unless something has changed, feel free to add it." Since there is nothing changed, added his reviewed-by. Reviewed-by: Zi Shen Lim Thanks, Yang > CC: Xi Wang > --- > Thsi patch might be buried by the storm of xadd discussion, however, it is > absolutely irrelevent to xadd, so resend the patch itself. > > arch/arm64/net/bpf_jit_comp.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c > index 6809647..49c1f1b 100644 > --- a/arch/arm64/net/bpf_jit_comp.c > +++ b/arch/arm64/net/bpf_jit_comp.c > @@ -563,7 +563,25 @@ emit_cond_jmp: > case BPF_ST | BPF_MEM | BPF_H: > case BPF_ST | BPF_MEM | BPF_B: > case BPF_ST | BPF_MEM | BPF_DW: > - goto notyet; > + /* Load imm to a register then store it */ > + ctx->tmp_used = 1; > + emit_a64_mov_i(1, tmp2, off, ctx); > + emit_a64_mov_i(1, tmp, imm, ctx); > + switch (BPF_SIZE(code)) { > + case BPF_W: > + emit(A64_STR32(tmp, dst, tmp2), ctx); > + break; > + case BPF_H: > + emit(A64_STRH(tmp, dst, tmp2), ctx); > + break; > + case BPF_B: > + emit(A64_STRB(tmp, dst, tmp2), ctx); > + break; > + case BPF_DW: > + emit(A64_STR64(tmp, dst, tmp2), ctx); > + break; > + } > + break; > > /* STX: *(size *)(dst + off) = src */ > case BPF_STX | BPF_MEM | BPF_W: >