From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932065AbbLGJZu (ORCPT ); Mon, 7 Dec 2015 04:25:50 -0500 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]:58495 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754242AbbLGJZq convert rfc822-to-8bit (ORCPT ); Mon, 7 Dec 2015 04:25:46 -0500 Message-ID: <56655095.3010200@arm.com> Date: Mon, 07 Dec 2015 09:25:41 +0000 From: Vladimir Murzin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: arnd@arndb.de, linux@arm.linux.org.uk, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, tglx@linutronix.de, u.kleine-koenig@pengutronix.de, afaerber@suse.de, mcoquelin.stm32@gmail.com CC: Mark.Rutland@arm.com, devicetree@vger.kernel.org, Pawel.Moll@arm.com, ijc+devicetree@hellion.org.uk, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-serial@vger.kernel.org, galak@codeaurora.org, jslaby@suse.cz, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v1 02/10] clockevents/drivers: add MPS2 Timer driver References: <1449048790-25859-1-git-send-email-vladimir.murzin@arm.com> <1449048790-25859-3-git-send-email-vladimir.murzin@arm.com> In-Reply-To: <1449048790-25859-3-git-send-email-vladimir.murzin@arm.com> X-OriginalArrivalTime: 07 Dec 2015 09:25:41.0549 (UTC) FILETIME=[3DE9DDD0:01D130D1] X-MC-Unique: dljbOz7oQpOC0TjCFhYj4Q-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/12/15 09:33, Vladimir Murzin wrote: > MPS2 platform has simple 32 bits general purpose countdown timers. > > The driver uses the first detected timer as a clocksource and the rest > of the timers as a clockevent Daniel, you had concerns on the RFC version. Does this one look fine to you or there is something I should improve? Thanks Vladimir > > Signed-off-by: Vladimir Murzin > --- > drivers/clocksource/Kconfig | 5 + > drivers/clocksource/Makefile | 1 + > drivers/clocksource/mps2-timer.c | 277 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 283 insertions(+) > create mode 100644 drivers/clocksource/mps2-timer.c > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 2eb5f0e..8bca09c 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -137,6 +137,11 @@ config CLKSRC_STM32 > depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) > select CLKSRC_MMIO > > +config CLKSRC_MPS2 > + bool "Clocksource for MPS2 SoCs" if COMPILE_TEST > + depends on OF && ARM > + select CLKSRC_MMIO > + > config ARM_ARCH_TIMER > bool > select CLKSRC_OF if OF > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile > index 56bd16e..7033b9c 100644 > --- a/drivers/clocksource/Makefile > +++ b/drivers/clocksource/Makefile > @@ -39,6 +39,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o > obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o > obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o > obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o > +obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o > obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o > obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o > obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o > diff --git a/drivers/clocksource/mps2-timer.c b/drivers/clocksource/mps2-timer.c > new file mode 100644 > index 0000000..3e19af5 > --- /dev/null > +++ b/drivers/clocksource/mps2-timer.c > @@ -0,0 +1,277 @@ > +/* > + * Copyright (C) 2015 ARM Limited > + * > + * Author: Vladimir Murzin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define TIMER_CTRL 0x0 > +#define TIMER_CTRL_ENABLE BIT(0) > +#define TIMER_CTRL_IE BIT(3) > + > +#define TIMER_VALUE 0x4 > +#define TIMER_RELOAD 0x8 > +#define TIMER_INT 0xc > + > +struct clockevent_mps2 { > + void __iomem *reg; > + u32 clock_count_per_tick; > + struct clock_event_device clkevt; > +}; > + > +static void __iomem *sched_clock_base; > + > +static u64 notrace mps2_sched_read(void) > +{ > + return ~readl_relaxed(sched_clock_base + TIMER_VALUE); > +} > + > +static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c) > +{ > + return container_of(c, struct clockevent_mps2, clkevt); > +} > + > +static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) > +{ > + writel(val, to_mps2_clkevt(c)->reg + offset); > +} > + > +static int mps2_timer_shutdown(struct clock_event_device *ce) > +{ > + clockevent_mps2_writel(0, ce, TIMER_RELOAD); > + clockevent_mps2_writel(0, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce) > +{ > + clockevent_mps2_writel(next, ce, TIMER_VALUE); > + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static int mps2_timer_set_periodic(struct clock_event_device *ce) > +{ > + u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; > + > + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD); > + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE); > + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id) > +{ > + struct clockevent_mps2 *ce = dev_id; > + u32 status = readl(ce->reg + TIMER_INT); > + > + if (!status) { > + pr_warn("spuirous interrupt\n"); > + return IRQ_NONE; > + } > + > + writel(1, ce->reg + TIMER_INT); > + > + ce->clkevt.event_handler(&ce->clkevt); > + > + return IRQ_HANDLED; > +} > + > +static int __init mps2_clockevent_init(struct device_node *np) > +{ > + void __iomem *base; > + struct clk *clk; > + struct clockevent_mps2 *ce; > + u32 rate; > + int irq, ret; > + const char *name = "mps2-clkevt"; > + > + ret = of_property_read_u32(np, "clock-frequency", &rate); > + if (ret) { > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret = PTR_ERR(clk); > + pr_err("failed to get clock for clockevent: %d\n", ret); > + goto err_clk_get; > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable clock for clockevent: %d\n", ret); > + clk_put(clk); > + goto err_clk_enable; > + } > + > + rate = clk_get_rate(clk); > + } > + > + base = of_iomap(np, 0); > + if (!base) { > + ret = -EADDRNOTAVAIL; > + pr_err("failed to map register for clockevent: %d\n", ret); > + goto err_iomap; > + } > + > + irq = irq_of_parse_and_map(np, 0); > + if (!irq) { > + ret = -ENOENT; > + pr_err("failed to get irq for clockevent: %d\n", ret); > + goto err_get_irq; > + } > + > + ce = kzalloc(sizeof(struct clockevent_mps2), GFP_KERNEL); > + if (!ce) { > + ret = -ENOMEM; > + pr_err("failed to allocate clockevent: %d\n", ret); > + goto err_ce_alloc; > + } > + > + ce->reg = base; > + ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ); > + ce->clkevt.irq = irq; > + ce->clkevt.name = name; > + ce->clkevt.rating = 200; > + ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; > + ce->clkevt.cpumask = cpu_possible_mask; > + ce->clkevt.set_state_shutdown = mps2_timer_shutdown, > + ce->clkevt.set_state_periodic = mps2_timer_set_periodic, > + ce->clkevt.set_state_oneshot = mps2_timer_shutdown, > + ce->clkevt.set_next_event = mps2_timer_set_next_event; > + > + /* Ensure timer is disabled */ > + writel(0, base + TIMER_CTRL); > + > + ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce); > + if (ret) { > + pr_err("failed to request irq: %d\n", ret); > + goto err_ia_alloc; > + } > + > + clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff); > + > + return 0; > + > +err_ia_alloc: > + kfree(ce); > +err_ce_alloc: > +err_get_irq: > + iounmap(base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return ret; > +} > + > +static int __init mps2_clocksource_init(struct device_node *np) > +{ > + void __iomem *base; > + struct clk *clk; > + u32 rate; > + int ret; > + const char *name = "mps2-clksrc"; > + > + ret = of_property_read_u32(np, "clock-frequency", &rate); > + if (ret) { > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret = PTR_ERR(clk); > + pr_err("failed to get clock for clocksource: %d\n", ret); > + goto err_clk_get; > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable clock for clocksource: %d\n", ret); > + clk_put(clk); > + goto err_clk_enable; > + } > + > + rate = clk_get_rate(clk); > + } > + > + base = of_iomap(np, 0); > + if (!base) { > + ret = -EADDRNOTAVAIL; > + pr_err("failed to map register for clocksource: %d\n", ret); > + goto err_iomap; > + } > + > + /* Ensure timer is disabled */ > + writel(0, base + TIMER_CTRL); > + > + /* ... and set it up as free-running clocksource */ > + writel(0xffffffff, base + TIMER_VALUE); > + writel(0xffffffff, base + TIMER_RELOAD); > + > + writel(TIMER_CTRL_ENABLE, base + TIMER_CTRL); > + > + ret = clocksource_mmio_init(base + TIMER_VALUE, name, > + rate, 200, 32, > + clocksource_mmio_readl_down); > + if (ret) { > + pr_err("failed to init clocksource: %d\n", ret); > + goto err_clocksource_init; > + } > + > + sched_clock_base = base; > + sched_clock_register(mps2_sched_read, 32, rate); > + > + return 0; > + > +err_clocksource_init: > + iounmap(base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return ret; > +} > + > +static void __init mps2_timer_init(struct device_node *np) > +{ > + static int has_clocksource, has_clockevent; > + int ret; > + > + if (!has_clocksource) { > + ret = mps2_clocksource_init(np); > + if (!ret) { > + has_clocksource = 1; > + return; > + } > + } > + > + if (!has_clockevent) { > + ret = mps2_clockevent_init(np); > + if (!ret) { > + has_clockevent = 1; > + return; > + } > + } > +} > + > +CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init); > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vladimir Murzin Subject: Re: [PATCH v1 02/10] clockevents/drivers: add MPS2 Timer driver Date: Mon, 07 Dec 2015 09:25:41 +0000 Message-ID: <56655095.3010200@arm.com> References: <1449048790-25859-1-git-send-email-vladimir.murzin@arm.com> <1449048790-25859-3-git-send-email-vladimir.murzin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <1449048790-25859-3-git-send-email-vladimir.murzin-5wv7dgnIgG8@public.gmane.org> Sender: linux-api-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: arnd-r2nGTMty4D4@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org, u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org, afaerber-l3A5Bk7waGM@public.gmane.org, mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Cc: Mark.Rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Pawel.Moll-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, linux-api-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, jslaby-AlSwsSmVLrQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On 02/12/15 09:33, Vladimir Murzin wrote: > MPS2 platform has simple 32 bits general purpose countdown timers. > > The driver uses the first detected timer as a clocksource and the rest > of the timers as a clockevent Daniel, you had concerns on the RFC version. Does this one look fine to you or there is something I should improve? Thanks Vladimir > > Signed-off-by: Vladimir Murzin > --- > drivers/clocksource/Kconfig | 5 + > drivers/clocksource/Makefile | 1 + > drivers/clocksource/mps2-timer.c | 277 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 283 insertions(+) > create mode 100644 drivers/clocksource/mps2-timer.c > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 2eb5f0e..8bca09c 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -137,6 +137,11 @@ config CLKSRC_STM32 > depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) > select CLKSRC_MMIO > > +config CLKSRC_MPS2 > + bool "Clocksource for MPS2 SoCs" if COMPILE_TEST > + depends on OF && ARM > + select CLKSRC_MMIO > + > config ARM_ARCH_TIMER > bool > select CLKSRC_OF if OF > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile > index 56bd16e..7033b9c 100644 > --- a/drivers/clocksource/Makefile > +++ b/drivers/clocksource/Makefile > @@ -39,6 +39,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o > obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o > obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o > obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o > +obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o > obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o > obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o > obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o > diff --git a/drivers/clocksource/mps2-timer.c b/drivers/clocksource/mps2-timer.c > new file mode 100644 > index 0000000..3e19af5 > --- /dev/null > +++ b/drivers/clocksource/mps2-timer.c > @@ -0,0 +1,277 @@ > +/* > + * Copyright (C) 2015 ARM Limited > + * > + * Author: Vladimir Murzin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define TIMER_CTRL 0x0 > +#define TIMER_CTRL_ENABLE BIT(0) > +#define TIMER_CTRL_IE BIT(3) > + > +#define TIMER_VALUE 0x4 > +#define TIMER_RELOAD 0x8 > +#define TIMER_INT 0xc > + > +struct clockevent_mps2 { > + void __iomem *reg; > + u32 clock_count_per_tick; > + struct clock_event_device clkevt; > +}; > + > +static void __iomem *sched_clock_base; > + > +static u64 notrace mps2_sched_read(void) > +{ > + return ~readl_relaxed(sched_clock_base + TIMER_VALUE); > +} > + > +static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c) > +{ > + return container_of(c, struct clockevent_mps2, clkevt); > +} > + > +static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) > +{ > + writel(val, to_mps2_clkevt(c)->reg + offset); > +} > + > +static int mps2_timer_shutdown(struct clock_event_device *ce) > +{ > + clockevent_mps2_writel(0, ce, TIMER_RELOAD); > + clockevent_mps2_writel(0, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce) > +{ > + clockevent_mps2_writel(next, ce, TIMER_VALUE); > + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static int mps2_timer_set_periodic(struct clock_event_device *ce) > +{ > + u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; > + > + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD); > + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE); > + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id) > +{ > + struct clockevent_mps2 *ce = dev_id; > + u32 status = readl(ce->reg + TIMER_INT); > + > + if (!status) { > + pr_warn("spuirous interrupt\n"); > + return IRQ_NONE; > + } > + > + writel(1, ce->reg + TIMER_INT); > + > + ce->clkevt.event_handler(&ce->clkevt); > + > + return IRQ_HANDLED; > +} > + > +static int __init mps2_clockevent_init(struct device_node *np) > +{ > + void __iomem *base; > + struct clk *clk; > + struct clockevent_mps2 *ce; > + u32 rate; > + int irq, ret; > + const char *name = "mps2-clkevt"; > + > + ret = of_property_read_u32(np, "clock-frequency", &rate); > + if (ret) { > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret = PTR_ERR(clk); > + pr_err("failed to get clock for clockevent: %d\n", ret); > + goto err_clk_get; > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable clock for clockevent: %d\n", ret); > + clk_put(clk); > + goto err_clk_enable; > + } > + > + rate = clk_get_rate(clk); > + } > + > + base = of_iomap(np, 0); > + if (!base) { > + ret = -EADDRNOTAVAIL; > + pr_err("failed to map register for clockevent: %d\n", ret); > + goto err_iomap; > + } > + > + irq = irq_of_parse_and_map(np, 0); > + if (!irq) { > + ret = -ENOENT; > + pr_err("failed to get irq for clockevent: %d\n", ret); > + goto err_get_irq; > + } > + > + ce = kzalloc(sizeof(struct clockevent_mps2), GFP_KERNEL); > + if (!ce) { > + ret = -ENOMEM; > + pr_err("failed to allocate clockevent: %d\n", ret); > + goto err_ce_alloc; > + } > + > + ce->reg = base; > + ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ); > + ce->clkevt.irq = irq; > + ce->clkevt.name = name; > + ce->clkevt.rating = 200; > + ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; > + ce->clkevt.cpumask = cpu_possible_mask; > + ce->clkevt.set_state_shutdown = mps2_timer_shutdown, > + ce->clkevt.set_state_periodic = mps2_timer_set_periodic, > + ce->clkevt.set_state_oneshot = mps2_timer_shutdown, > + ce->clkevt.set_next_event = mps2_timer_set_next_event; > + > + /* Ensure timer is disabled */ > + writel(0, base + TIMER_CTRL); > + > + ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce); > + if (ret) { > + pr_err("failed to request irq: %d\n", ret); > + goto err_ia_alloc; > + } > + > + clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff); > + > + return 0; > + > +err_ia_alloc: > + kfree(ce); > +err_ce_alloc: > +err_get_irq: > + iounmap(base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return ret; > +} > + > +static int __init mps2_clocksource_init(struct device_node *np) > +{ > + void __iomem *base; > + struct clk *clk; > + u32 rate; > + int ret; > + const char *name = "mps2-clksrc"; > + > + ret = of_property_read_u32(np, "clock-frequency", &rate); > + if (ret) { > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret = PTR_ERR(clk); > + pr_err("failed to get clock for clocksource: %d\n", ret); > + goto err_clk_get; > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable clock for clocksource: %d\n", ret); > + clk_put(clk); > + goto err_clk_enable; > + } > + > + rate = clk_get_rate(clk); > + } > + > + base = of_iomap(np, 0); > + if (!base) { > + ret = -EADDRNOTAVAIL; > + pr_err("failed to map register for clocksource: %d\n", ret); > + goto err_iomap; > + } > + > + /* Ensure timer is disabled */ > + writel(0, base + TIMER_CTRL); > + > + /* ... and set it up as free-running clocksource */ > + writel(0xffffffff, base + TIMER_VALUE); > + writel(0xffffffff, base + TIMER_RELOAD); > + > + writel(TIMER_CTRL_ENABLE, base + TIMER_CTRL); > + > + ret = clocksource_mmio_init(base + TIMER_VALUE, name, > + rate, 200, 32, > + clocksource_mmio_readl_down); > + if (ret) { > + pr_err("failed to init clocksource: %d\n", ret); > + goto err_clocksource_init; > + } > + > + sched_clock_base = base; > + sched_clock_register(mps2_sched_read, 32, rate); > + > + return 0; > + > +err_clocksource_init: > + iounmap(base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return ret; > +} > + > +static void __init mps2_timer_init(struct device_node *np) > +{ > + static int has_clocksource, has_clockevent; > + int ret; > + > + if (!has_clocksource) { > + ret = mps2_clocksource_init(np); > + if (!ret) { > + has_clocksource = 1; > + return; > + } > + } > + > + if (!has_clockevent) { > + ret = mps2_clockevent_init(np); > + if (!ret) { > + has_clockevent = 1; > + return; > + } > + } > +} > + > +CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init); > From mboxrd@z Thu Jan 1 00:00:00 1970 From: vladimir.murzin@arm.com (Vladimir Murzin) Date: Mon, 07 Dec 2015 09:25:41 +0000 Subject: [PATCH v1 02/10] clockevents/drivers: add MPS2 Timer driver In-Reply-To: <1449048790-25859-3-git-send-email-vladimir.murzin@arm.com> References: <1449048790-25859-1-git-send-email-vladimir.murzin@arm.com> <1449048790-25859-3-git-send-email-vladimir.murzin@arm.com> Message-ID: <56655095.3010200@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 02/12/15 09:33, Vladimir Murzin wrote: > MPS2 platform has simple 32 bits general purpose countdown timers. > > The driver uses the first detected timer as a clocksource and the rest > of the timers as a clockevent Daniel, you had concerns on the RFC version. Does this one look fine to you or there is something I should improve? Thanks Vladimir > > Signed-off-by: Vladimir Murzin > --- > drivers/clocksource/Kconfig | 5 + > drivers/clocksource/Makefile | 1 + > drivers/clocksource/mps2-timer.c | 277 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 283 insertions(+) > create mode 100644 drivers/clocksource/mps2-timer.c > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 2eb5f0e..8bca09c 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -137,6 +137,11 @@ config CLKSRC_STM32 > depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) > select CLKSRC_MMIO > > +config CLKSRC_MPS2 > + bool "Clocksource for MPS2 SoCs" if COMPILE_TEST > + depends on OF && ARM > + select CLKSRC_MMIO > + > config ARM_ARCH_TIMER > bool > select CLKSRC_OF if OF > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile > index 56bd16e..7033b9c 100644 > --- a/drivers/clocksource/Makefile > +++ b/drivers/clocksource/Makefile > @@ -39,6 +39,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o > obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o > obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o > obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o > +obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o > obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o > obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o > obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o > diff --git a/drivers/clocksource/mps2-timer.c b/drivers/clocksource/mps2-timer.c > new file mode 100644 > index 0000000..3e19af5 > --- /dev/null > +++ b/drivers/clocksource/mps2-timer.c > @@ -0,0 +1,277 @@ > +/* > + * Copyright (C) 2015 ARM Limited > + * > + * Author: Vladimir Murzin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define TIMER_CTRL 0x0 > +#define TIMER_CTRL_ENABLE BIT(0) > +#define TIMER_CTRL_IE BIT(3) > + > +#define TIMER_VALUE 0x4 > +#define TIMER_RELOAD 0x8 > +#define TIMER_INT 0xc > + > +struct clockevent_mps2 { > + void __iomem *reg; > + u32 clock_count_per_tick; > + struct clock_event_device clkevt; > +}; > + > +static void __iomem *sched_clock_base; > + > +static u64 notrace mps2_sched_read(void) > +{ > + return ~readl_relaxed(sched_clock_base + TIMER_VALUE); > +} > + > +static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c) > +{ > + return container_of(c, struct clockevent_mps2, clkevt); > +} > + > +static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) > +{ > + writel(val, to_mps2_clkevt(c)->reg + offset); > +} > + > +static int mps2_timer_shutdown(struct clock_event_device *ce) > +{ > + clockevent_mps2_writel(0, ce, TIMER_RELOAD); > + clockevent_mps2_writel(0, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce) > +{ > + clockevent_mps2_writel(next, ce, TIMER_VALUE); > + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static int mps2_timer_set_periodic(struct clock_event_device *ce) > +{ > + u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; > + > + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD); > + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE); > + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); > + > + return 0; > +} > + > +static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id) > +{ > + struct clockevent_mps2 *ce = dev_id; > + u32 status = readl(ce->reg + TIMER_INT); > + > + if (!status) { > + pr_warn("spuirous interrupt\n"); > + return IRQ_NONE; > + } > + > + writel(1, ce->reg + TIMER_INT); > + > + ce->clkevt.event_handler(&ce->clkevt); > + > + return IRQ_HANDLED; > +} > + > +static int __init mps2_clockevent_init(struct device_node *np) > +{ > + void __iomem *base; > + struct clk *clk; > + struct clockevent_mps2 *ce; > + u32 rate; > + int irq, ret; > + const char *name = "mps2-clkevt"; > + > + ret = of_property_read_u32(np, "clock-frequency", &rate); > + if (ret) { > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret = PTR_ERR(clk); > + pr_err("failed to get clock for clockevent: %d\n", ret); > + goto err_clk_get; > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable clock for clockevent: %d\n", ret); > + clk_put(clk); > + goto err_clk_enable; > + } > + > + rate = clk_get_rate(clk); > + } > + > + base = of_iomap(np, 0); > + if (!base) { > + ret = -EADDRNOTAVAIL; > + pr_err("failed to map register for clockevent: %d\n", ret); > + goto err_iomap; > + } > + > + irq = irq_of_parse_and_map(np, 0); > + if (!irq) { > + ret = -ENOENT; > + pr_err("failed to get irq for clockevent: %d\n", ret); > + goto err_get_irq; > + } > + > + ce = kzalloc(sizeof(struct clockevent_mps2), GFP_KERNEL); > + if (!ce) { > + ret = -ENOMEM; > + pr_err("failed to allocate clockevent: %d\n", ret); > + goto err_ce_alloc; > + } > + > + ce->reg = base; > + ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ); > + ce->clkevt.irq = irq; > + ce->clkevt.name = name; > + ce->clkevt.rating = 200; > + ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; > + ce->clkevt.cpumask = cpu_possible_mask; > + ce->clkevt.set_state_shutdown = mps2_timer_shutdown, > + ce->clkevt.set_state_periodic = mps2_timer_set_periodic, > + ce->clkevt.set_state_oneshot = mps2_timer_shutdown, > + ce->clkevt.set_next_event = mps2_timer_set_next_event; > + > + /* Ensure timer is disabled */ > + writel(0, base + TIMER_CTRL); > + > + ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce); > + if (ret) { > + pr_err("failed to request irq: %d\n", ret); > + goto err_ia_alloc; > + } > + > + clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff); > + > + return 0; > + > +err_ia_alloc: > + kfree(ce); > +err_ce_alloc: > +err_get_irq: > + iounmap(base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return ret; > +} > + > +static int __init mps2_clocksource_init(struct device_node *np) > +{ > + void __iomem *base; > + struct clk *clk; > + u32 rate; > + int ret; > + const char *name = "mps2-clksrc"; > + > + ret = of_property_read_u32(np, "clock-frequency", &rate); > + if (ret) { > + clk = of_clk_get(np, 0); > + if (IS_ERR(clk)) { > + ret = PTR_ERR(clk); > + pr_err("failed to get clock for clocksource: %d\n", ret); > + goto err_clk_get; > + } > + > + ret = clk_prepare_enable(clk); > + if (ret) { > + pr_err("failed to enable clock for clocksource: %d\n", ret); > + clk_put(clk); > + goto err_clk_enable; > + } > + > + rate = clk_get_rate(clk); > + } > + > + base = of_iomap(np, 0); > + if (!base) { > + ret = -EADDRNOTAVAIL; > + pr_err("failed to map register for clocksource: %d\n", ret); > + goto err_iomap; > + } > + > + /* Ensure timer is disabled */ > + writel(0, base + TIMER_CTRL); > + > + /* ... and set it up as free-running clocksource */ > + writel(0xffffffff, base + TIMER_VALUE); > + writel(0xffffffff, base + TIMER_RELOAD); > + > + writel(TIMER_CTRL_ENABLE, base + TIMER_CTRL); > + > + ret = clocksource_mmio_init(base + TIMER_VALUE, name, > + rate, 200, 32, > + clocksource_mmio_readl_down); > + if (ret) { > + pr_err("failed to init clocksource: %d\n", ret); > + goto err_clocksource_init; > + } > + > + sched_clock_base = base; > + sched_clock_register(mps2_sched_read, 32, rate); > + > + return 0; > + > +err_clocksource_init: > + iounmap(base); > +err_iomap: > + clk_disable_unprepare(clk); > +err_clk_enable: > + clk_put(clk); > +err_clk_get: > + return ret; > +} > + > +static void __init mps2_timer_init(struct device_node *np) > +{ > + static int has_clocksource, has_clockevent; > + int ret; > + > + if (!has_clocksource) { > + ret = mps2_clocksource_init(np); > + if (!ret) { > + has_clocksource = 1; > + return; > + } > + } > + > + if (!has_clockevent) { > + ret = mps2_clockevent_init(np); > + if (!ret) { > + has_clockevent = 1; > + return; > + } > + } > +} > + > +CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init); >