* [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0
@ 2015-12-07 16:29 Mika Kuoppala
2015-12-07 16:29 ` [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on Mika Kuoppala
2015-12-08 9:33 ` [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Kamble, Sagar A
0 siblings, 2 replies; 5+ messages in thread
From: Mika Kuoppala @ 2015-12-07 16:29 UTC (permalink / raw)
To: intel-gfx
There is conflicting info between E0 and F0 steppings
for this workarounds. Trust more authoritative source and
be conservative and extend also for F0.
This prevents numerous (>50) gpu hangs with SKL GT4e
during piglit run.
References: HSD: gen9lp/2134184
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee05ce8..7096c06 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4717,7 +4717,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
*/
if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
- IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
+ IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
I915_WRITE(GEN9_PG_ENABLE, 0);
else
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
--
2.5.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on
2015-12-07 16:29 [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Mika Kuoppala
@ 2015-12-07 16:29 ` Mika Kuoppala
2015-12-08 5:25 ` Kamble, Sagar A
2015-12-08 9:33 ` [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Kamble, Sagar A
1 sibling, 1 reply; 5+ messages in thread
From: Mika Kuoppala @ 2015-12-07 16:29 UTC (permalink / raw)
To: intel-gfx
WaRsDoubleRc6WrlWithCoarsePowerGating should
be enabled for all Skylakes. Make it so.
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7096c06..8598456 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4673,8 +4673,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
/* 2b: Program RC6 thresholds.*/
/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
- if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
- IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
+ if (IS_SKYLAKE(dev))
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
else
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
--
2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on
2015-12-07 16:29 ` [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on Mika Kuoppala
@ 2015-12-08 5:25 ` Kamble, Sagar A
0 siblings, 0 replies; 5+ messages in thread
From: Kamble, Sagar A @ 2015-12-08 5:25 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
On 12/7/2015 9:59 PM, Mika Kuoppala wrote:
> WaRsDoubleRc6WrlWithCoarsePowerGating should
> be enabled for all Skylakes. Make it so.
>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7096c06..8598456 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4673,8 +4673,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
> /* 2b: Program RC6 thresholds.*/
>
> /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
> - if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
> - IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
> + if (IS_SKYLAKE(dev))
> I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> else
> I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0
2015-12-07 16:29 [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Mika Kuoppala
2015-12-07 16:29 ` [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on Mika Kuoppala
@ 2015-12-08 9:33 ` Kamble, Sagar A
2015-12-08 14:23 ` Jani Nikula
1 sibling, 1 reply; 5+ messages in thread
From: Kamble, Sagar A @ 2015-12-08 9:33 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
On 12/7/2015 9:59 PM, Mika Kuoppala wrote:
> There is conflicting info between E0 and F0 steppings
> for this workarounds. Trust more authoritative source and
> be conservative and extend also for F0.
>
> This prevents numerous (>50) gpu hangs with SKL GT4e
> during piglit run.
>
> References: HSD: gen9lp/2134184
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ee05ce8..7096c06 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4717,7 +4717,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
> */
> if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
> ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
> - IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
> + IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
> I915_WRITE(GEN9_PG_ENABLE, 0);
> else
> I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0
2015-12-08 9:33 ` [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Kamble, Sagar A
@ 2015-12-08 14:23 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2015-12-08 14:23 UTC (permalink / raw)
To: Kamble, Sagar A, Mika Kuoppala, intel-gfx
Both patches pushed to drm-intel-next-queued, and then backported to
drm-intel-fixes with cc: stable. Thanks for the patches and review.
BR,
Jani.
On Tue, 08 Dec 2015, "Kamble, Sagar A" <sagar.a.kamble@intel.com> wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>
> On 12/7/2015 9:59 PM, Mika Kuoppala wrote:
>> There is conflicting info between E0 and F0 steppings
>> for this workarounds. Trust more authoritative source and
>> be conservative and extend also for F0.
>>
>> This prevents numerous (>50) gpu hangs with SKL GT4e
>> during piglit run.
>>
>> References: HSD: gen9lp/2134184
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index ee05ce8..7096c06 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4717,7 +4717,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
>> */
>> if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
>> ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
>> - IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
>> + IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
>> I915_WRITE(GEN9_PG_ENABLE, 0);
>> else
>> I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-12-08 14:23 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-07 16:29 [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Mika Kuoppala
2015-12-07 16:29 ` [PATCH 2/2] drm/i915/skl: Double RC6 WRL always on Mika Kuoppala
2015-12-08 5:25 ` Kamble, Sagar A
2015-12-08 9:33 ` [PATCH 1/2] drm/i915/skl: Disable coarse power gating up until F0 Kamble, Sagar A
2015-12-08 14:23 ` Jani Nikula
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