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* [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
@ 2015-12-09  4:07 Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 01/19] PM / devfreq: exynos: Add generic exynos bus frequency driver Chanwoo Choi
                   ` (20 more replies)
  0 siblings, 21 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch-set includes the two features as following. The generic exynos bus
frequency driver is able to support almost Exynos SoCs for bus frequency
scaling. And the new passive governor is able to make the dependency on
between devices for frequency/voltage scaling. I had posted the patch-set[1]
with the similiar concept. This is is revised version for exynos bus frequency.
- Generic exynos bus frequency driver
- New passive governor of DEVFREQ framework

Depends on:
- This patch-set is based on devfreq.git[2].
[1] https://lkml.org/lkml/2015/1/7/872
   : [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
[2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch: for-rafael)

Changes from v1:
(https://lkml.org/lkml/2015/11/26/260)
- Check whether the instance of regulator is NULL or not
  when executing regulator_disable() because of only parent
  devfreq device has the regulator instance. After fixing it,
  the wake-up from suspend state is well working. (patch1)
- Fix bug which checks 'bus-clk' instead of 'bus->regulator'
  after calling devm_clk_get() (on patch1)
- Update the documentation to remove the description about
  DEVFREQ-EVENT subsystem (on patch2)
- Add the full name of DMC (Dynamic Memory Controller) (on patch2)
- Modify the detailed correlation of buses for Exynos3250
  on documentation (patch2)
- Add the MFC bus node for Exynos3250 (on patch11, patch12)
- Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
- Add the PPMU node for exynos4412-odroidu3
- Add the support of bus frequency for exynos4412-odroidu3

Detailed descirption for patch-set:
1. Add generic exynos bus frequency driver
: This patch-set adds the generic exynos bus frequency driver for AXI bus
of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
architecture for bus between DRAM and sub-blocks in SoC.

 There are the different buses according to Exynos SoC because Exynos SoC
has the differnt sub-blocks and bus speed. In spite of this difference
among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
unique data of each bus in the devicetree file.

 In devicetree, each bus node has a bus clock, regulator, operation-point
and devfreq-event devices which measure the utilization of each bus block.

For example,
- The bus of DMC block in exynos3250.dtsi are listed below:

	bus_dmc: bus_dmc {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_dmc CLK_DIV_DMC>;
		clock-names = "bus";
		operating-points-v2 = <&bus_dmc_opp_table>;
		status = "disabled";
	};

	bus_dmc_opp_table: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <50000000>;
			opp-microvolt = <800000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <800000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <134000000>;
			opp-microvolt = <800000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <800000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <875000>;
		};
	};

- Usage case to handle the frequency and voltage of bus on runtime
  in exynos3250-rinato.dts are listed below:

	&bus_dmc {
		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
		status = "okay";
	};

2. Add new passive governor of DEVFREQ framework (patch5-patch7)
: This patch-set add the new passive governor for DEVFREQ framework.
The existing governors (ondemand, performance and so on) are used for DVFS
(Dynamic Voltage and Frequency Scaling) drivers. The existing governors
are independently used for specific device driver which don't give the
influence to other device drviers and also don't receive the effect from
other device drivers.

 The passive governor depends on operation of parent driver with existing
governors(ondemand, performance and so on) extremely and is not able to
decide the new frequency by oneself. According to the decided new frequency
of parent driver with governor, the passive governor uses it to decide
the appropriate frequency for own device driver. The passive governor
must need the following information from device tree:

For exameple,
 There are one more bus device drivers in Exynos3250 which need to
change their source clock according to their utilization on runtime.
But, they share the same power line (e.g., regulator). So, LEFTBUS bus
driver is operated as parent with ondemand governor and then the rest
device driver with passive governor.

 The buses of Internal block in exynos3250.dtsi are listed below:
When LEFTBUS bus driver (parent) changes the bus frequency with
ondemand governor on runtime, the rest bus devices which sharing
the same power line (VDD_INT) will change the each bus frequency
according to the decision of LEFTBUS bus driver (parent).

- INT (Internal) block
	: VDD_INT |--- LEFTBUS
		  |--- PERIL
		  |--- MFC
		  |--- G3D
		  |--- RIGHTBUS
		  |--- FSYS
		  |--- LCD0
		  |--- PERIR
		  |--- ISP
		  |--- CAM

- The buss of INT block in exynos3250.dtsi are listed below:
	bus_leftbus: bus_leftbus {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu CLK_DIV_GDL>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		status = "disabled";
	};

	bus_rightbus: bus_rightbus {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu CLK_DIV_GDR>;
		clock-names = "bus";
		operating-points-v2 = <&bus_leftbus_opp_table>;
		status = "disabled";
	};

	(Omit the rest bus dt node)

- Usage case to handle the frequency and voltage of bus on runtime
  in exynos3250-rinato.dts are listed below:
	/* Parent bus device of VDD_INT */
	&bus_leftbus {
		devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
		vdd-supply = <&buck3_reg>;
		status = "okay";
	};

	/* Passive bus device depend on LEFTBUS bus. */
	&bus_rightbus {
		devfreq = <&bus_leftbus>; /* 'devfreq' property indicates
					     the phandle of parent device. */
		status = "okay";
	};

	(Omit the rest bus dt node)

Chanwoo Choi (19):
  PM / devfreq: exynos: Add generic exynos bus frequency driver
  PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
  ARM: dts: Add DMC bus node for Exynos3250
  ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
  PM / devfreq: Add new passive governor
  PM / devfreq: Add devfreq_get_devfreq_by_phandle()
  PM / devfreq: Show the related information according to governor type
  PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
  PM / devfreq: exynos: Update documentation for bus devices using passive governor
  PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
  PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
  ARM: dts: Add bus nodes using VDD_INT for Exynos3250
  ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
  ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
  ARM: dts: Add PPMU node for exynos4412-odroidu3
  ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
  ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
  ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3

 .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
 arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
 arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
 arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
 arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
 arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
 arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
 drivers/devfreq/Kconfig                            |   37 +-
 drivers/devfreq/Makefile                           |    2 +
 drivers/devfreq/devfreq.c                          |  120 ++-
 drivers/devfreq/exynos/Makefile                    |    3 +-
 drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
 drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
 drivers/devfreq/exynos/exynos4_bus.h               |  110 --
 drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
 drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
 drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
 drivers/devfreq/governor.h                         |    7 +
 drivers/devfreq/governor_passive.c                 |  109 ++
 drivers/devfreq/governor_performance.c             |    1 +
 drivers/devfreq/governor_powersave.c               |    1 +
 drivers/devfreq/governor_simpleondemand.c          |    1 +
 drivers/devfreq/governor_userspace.c               |    1 +
 include/linux/devfreq.h                            |   28 +
 25 files changed, 1958 insertions(+), 1828 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
 create mode 100644 drivers/devfreq/exynos/exynos-bus.c
 delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
 delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
 delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
 delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
 delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
 create mode 100644 drivers/devfreq/governor_passive.c

-- 
1.9.1


^ permalink raw reply	[flat|nested] 72+ messages in thread

* [PATCH v2 01/19] PM / devfreq: exynos: Add generic exynos bus frequency driver
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for " Chanwoo Choi
                   ` (19 subsequent siblings)
  20 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the generic exynos bus frequency driver for AMBA AXI bus
of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC
have the common architecture for bus between DRAM and sub-blocks in SoC.
This driver can support the generic bus frequency driver for Exynos SoCs.

In devicetree, Each bus block has a bus clock, regulator, operation-point
and devfreq-event devices which measure the utilization of each bus block.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/Kconfig             |  15 ++
 drivers/devfreq/Makefile            |   1 +
 drivers/devfreq/exynos/Makefile     |   1 +
 drivers/devfreq/exynos/exynos-bus.c | 449 ++++++++++++++++++++++++++++++++++++
 4 files changed, 466 insertions(+)
 create mode 100644 drivers/devfreq/exynos/exynos-bus.c

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 64281bb2f650..55ec774f794c 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -66,6 +66,21 @@ config DEVFREQ_GOV_USERSPACE
 
 comment "DEVFREQ Drivers"
 
+config ARM_EXYNOS_BUS_DEVFREQ
+	bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
+	depends on ARCH_EXYNOS
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select DEVFREQ_EVENT_EXYNOS_PPMU
+	select PM_DEVFREQ_EVENT
+	select PM_OPP
+	help
+	  This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
+	  Memory bus has one more group of memory bus (e.g, MIF and INT block).
+	  Each memory bus group could contain many memoby bus block. It reads
+	  PPMU counters of memory controllers by using DEVFREQ-event device
+	  and adjusts the operating frequencies and voltages with OPP support.
+	  This does not yet operate with optimal voltages.
+
 config ARM_EXYNOS4_BUS_DEVFREQ
 	bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
 	depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 5134f9ee983d..375ebbb4fcfb 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)	+= governor_powersave.o
 obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)	+= governor_userspace.o
 
 # DEVFREQ Drivers
+obj-$(CONFIG_ARCH_EXYNOS)		+= exynos/
 obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)	+= exynos/
 obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)	+= exynos/
 obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra-devfreq.o
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 49bc9175f923..4ec06d322996 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,3 +1,4 @@
 # Exynos DEVFREQ Drivers
+obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o
 obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)	+= exynos_ppmu.o exynos4_bus.o
 obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)	+= exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos-bus.c b/drivers/devfreq/exynos/exynos-bus.c
new file mode 100644
index 000000000000..f1bc20839650
--- /dev/null
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -0,0 +1,449 @@
+/*
+ * Generic Exynos Bus frequency driver with DEVFREQ Framework
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This driver support Exynos Bus frequency feature by using
+ * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+
+#define DEFAULT_SATURATION_RATIO	40
+
+struct exynos_bus {
+	struct device *dev;
+
+	struct devfreq *devfreq;
+	struct devfreq_event_dev **edev;
+	unsigned int edev_count;
+	struct mutex lock;
+
+	struct dev_pm_opp *curr_opp;
+
+	struct regulator *regulator;
+	struct clk *clk;
+	int ratio;
+};
+
+/*
+ * Control the devfreq-event device to get the current state of bus
+ */
+#define exynos_bus_ops_edev(ops)				\
+static int exynos_bus_##ops(struct exynos_bus *bus)		\
+{								\
+	int i, ret;						\
+								\
+	for (i = 0; i < bus->edev_count; i++) {			\
+		if (!bus->edev[i])				\
+			continue;				\
+		ret = devfreq_event_##ops(bus->edev[i]);	\
+		if (ret < 0)					\
+			return ret;				\
+	}							\
+								\
+	return 0;						\
+}
+exynos_bus_ops_edev(enable_edev);
+exynos_bus_ops_edev(disable_edev);
+exynos_bus_ops_edev(set_event);
+
+static int exynos_bus_get_event(struct exynos_bus *bus,
+				struct devfreq_event_data *edata)
+{
+	struct devfreq_event_data event_data;
+	unsigned long load_count = 0, total_count = 0;
+	int i, ret = 0;
+
+	for (i = 0; i < bus->edev_count; i++) {
+		if (!bus->edev[i])
+			continue;
+
+		ret = devfreq_event_get_event(bus->edev[i], &event_data);
+		if (ret < 0)
+			return ret;
+
+		if (i == 0 || event_data.load_count > load_count) {
+			load_count = event_data.load_count;
+			total_count = event_data.total_count;
+		}
+	}
+
+	edata->load_count = load_count;
+	edata->total_count = total_count;
+
+	return ret;
+}
+
+/*
+ * Must necessary function for devfreq governor
+ */
+static int exynos_bus_target(struct device *dev, unsigned long *freq, u32 flags)
+{
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	struct dev_pm_opp *new_opp;
+	unsigned long old_freq, new_freq, old_volt, new_volt;
+	int ret = 0;
+
+	/* Get new opp-bus instance according to new bus clock */
+	rcu_read_lock();
+	new_opp = devfreq_recommended_opp(dev, freq, flags);
+	if (IS_ERR_OR_NULL(new_opp)) {
+		dev_err(dev, "failed to get recommed opp instance\n");
+		rcu_read_unlock();
+		return PTR_ERR(new_opp);
+	}
+
+	new_freq = dev_pm_opp_get_freq(new_opp);
+	new_volt = dev_pm_opp_get_voltage(new_opp);
+	old_freq = dev_pm_opp_get_freq(bus->curr_opp);
+	old_volt = dev_pm_opp_get_voltage(bus->curr_opp);
+	rcu_read_unlock();
+
+	if (old_freq == new_freq)
+		return 0;
+
+	/* Change voltage and frequency according to new OPP level */
+	mutex_lock(&bus->lock);
+
+	if (old_freq < new_freq) {
+		ret = regulator_set_voltage(bus->regulator, new_volt, new_volt);
+		if (ret < 0) {
+			dev_err(bus->dev, "failed to set voltage\n");
+			regulator_set_voltage(bus->regulator, old_volt,
+						old_volt);
+			goto out;
+		}
+	}
+
+	ret = clk_set_rate(bus->clk, new_freq);
+	if (ret < 0) {
+		dev_err(dev, "failed to change clock of bus\n");
+		clk_set_rate(bus->clk, old_freq);
+		goto out;
+	}
+
+	if (old_freq > new_freq) {
+		ret = regulator_set_voltage(bus->regulator, new_volt, new_volt);
+		if (ret < 0) {
+			dev_err(bus->dev, "failed to set voltage\n");
+			regulator_set_voltage(bus->regulator, old_volt,
+						old_volt);
+			goto out;
+		}
+	}
+	bus->curr_opp = new_opp;
+
+	dev_dbg(dev, "Set the frequency of bus (%ldkHz -> %ldkHz)\n",
+			old_freq/1000, new_freq/1000);
+out:
+	mutex_unlock(&bus->lock);
+
+	return ret;
+}
+
+static int exynos_bus_get_dev_status(struct device *dev,
+				     struct devfreq_dev_status *stat)
+{
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	struct devfreq_event_data edata;
+	int ret;
+
+	rcu_read_lock();
+	stat->current_frequency = dev_pm_opp_get_freq(bus->curr_opp);
+	rcu_read_unlock();
+
+	ret = exynos_bus_get_event(bus, &edata);
+	if (ret < 0) {
+		stat->total_time = stat->busy_time = 0;
+		goto err;
+	}
+
+	stat->busy_time = (edata.load_count * 100) / bus->ratio;
+	stat->total_time = edata.total_count;
+
+	dev_dbg(dev, "Usage of devfreq-event : %ld/%ld\n", stat->busy_time,
+							stat->total_time);
+
+err:
+	ret = exynos_bus_set_event(bus);
+	if (ret < 0) {
+		dev_err(dev, "failed to set event to devfreq-event devices\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static void exynos_bus_exit(struct device *dev)
+{
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	int ret;
+
+	ret = exynos_bus_disable_edev(bus);
+	if (ret < 0)
+		dev_warn(dev, "failed to disable the devfreq-event devices\n");
+
+	if (bus->regulator)
+		regulator_disable(bus->regulator);
+
+	dev_pm_opp_of_remove_table(dev);
+}
+
+static int exynos_bus_parse_of(struct device_node *np,
+			      struct exynos_bus *bus)
+{
+	struct device *dev = bus->dev;
+	unsigned long rate;
+	int i, ret, count, size;
+
+	/* Get the clock to provide each bus with source clock */
+	bus->clk = devm_clk_get(dev, "bus");
+	if (IS_ERR(bus->clk)) {
+		dev_err(dev, "failed to get bus clock\n");
+		return PTR_ERR(bus->clk);
+	}
+
+	ret = clk_prepare_enable(bus->clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get enable clock\n");
+		return ret;
+	}
+
+	/* Get the freq/voltage OPP table to scale the bus frequency */
+	rcu_read_lock();
+	ret = dev_pm_opp_of_add_table(dev);
+	if (ret < 0) {
+		dev_err(dev, "failed to get OPP table\n");
+		rcu_read_unlock();
+		return ret;
+	}
+
+	rate = clk_get_rate(bus->clk);
+	bus->curr_opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+	if (IS_ERR(bus->curr_opp)) {
+		dev_err(dev, "failed to find dev_pm_opp\n");
+		rcu_read_unlock();
+		ret = PTR_ERR(bus->curr_opp);
+		goto err_opp;
+	}
+	rcu_read_unlock();
+
+	/* Get the regulator to provide each bus with the power */
+	bus->regulator = devm_regulator_get(dev, "vdd");
+	if (IS_ERR(bus->regulator)) {
+		dev_err(dev, "failed to get VDD regulator\n");
+		ret = PTR_ERR(bus->regulator);
+		goto err_opp;
+	}
+
+	ret = regulator_enable(bus->regulator);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable VDD regulator\n");
+		goto err_opp;
+	}
+
+	/*
+	 * Get the devfreq-event devices to get the current utilization of
+	 * buses. This raw data will be used in devfreq ondemand governor.
+	 */
+	count = devfreq_event_get_edev_count(dev);
+	if (count < 0) {
+		dev_err(dev, "failed to get the count of devfreq-event dev\n");
+		ret = count;
+		goto err_regulator;
+	}
+	bus->edev_count = count;
+
+	size = sizeof(*bus->edev) * count;
+	bus->edev = devm_kzalloc(dev, size, GFP_KERNEL);
+	if (!bus->edev) {
+		ret = -ENOMEM;
+		goto err_regulator;
+	}
+
+	for (i = 0; i < count; i++) {
+		bus->edev[i] = devfreq_event_get_edev_by_phandle(dev, i);
+		if (IS_ERR(bus->edev[i])) {
+			ret = -EPROBE_DEFER;
+			goto err_regulator;
+		}
+	}
+
+	/*
+	 * Optionally, Get the saturation ratio according to Exynos SoC
+	 * When measuring the utilization of each AXI bus with devfreq-event
+	 * devices, the measured real cycle might be much lower than the
+	 * total cycle of bus during sampling rate. In result, the devfreq
+	 * simple-ondemand governor might not decide to change the current
+	 * frequency due to too utilization (= real cycle/total cycle).
+	 * So, this property is used to adjust the utilization when calculating
+	 * the busy_time in exynos_bus_get_dev_status().
+	 */
+	if (of_property_read_u32(np, "exynos,saturation-ratio", &bus->ratio))
+		bus->ratio = DEFAULT_SATURATION_RATIO;
+
+	return 0;
+
+err_regulator:
+	regulator_disable(bus->regulator);
+err_opp:
+	dev_pm_opp_of_remove_table(dev);
+
+	return ret;
+}
+
+static int exynos_bus_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct devfreq_dev_profile *profile;
+	struct devfreq_simple_ondemand_data *ondemand_data;
+	struct exynos_bus *bus;
+	int ret;
+
+	if (!np) {
+		dev_err(dev, "failed to find devicetree node\n");
+		return -EINVAL;
+	}
+
+	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
+	if (!bus)
+		return -ENOMEM;
+	mutex_init(&bus->lock);
+	bus->dev = &pdev->dev;
+	platform_set_drvdata(pdev, bus);
+
+	/* Parse the device-tree to get the resource information */
+	ret = exynos_bus_parse_of(np, bus);
+	if (ret < 0)
+		return ret;
+
+	/* Initalize the struct profile and governor data */
+	profile = devm_kzalloc(dev, sizeof(*profile), GFP_KERNEL);
+	if (!profile)
+		return -ENOMEM;
+	profile->polling_ms = 50;
+	profile->target = exynos_bus_target;
+	profile->get_dev_status = exynos_bus_get_dev_status;
+	profile->exit = exynos_bus_exit;
+
+	ondemand_data = devm_kzalloc(dev, sizeof(*ondemand_data), GFP_KERNEL);
+	if (!ondemand_data)
+		return -ENOMEM;
+	ondemand_data->upthreshold = 40;
+	ondemand_data->downdifferential = 5;
+
+	/* Add devfreq device to monitor and handle the exynos bus */
+	bus->devfreq = devm_devfreq_add_device(dev, profile, "simple_ondemand",
+						ondemand_data);
+	if (IS_ERR_OR_NULL(bus->devfreq)) {
+		dev_err(dev, "failed to add devfreq device\n");
+		return  PTR_ERR(bus->devfreq);
+	}
+
+	/* Register opp_notifier to catch the change of OPP  */
+	ret = devm_devfreq_register_opp_notifier(dev, bus->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to register opp notifier\n");
+		return ret;
+	}
+
+	/*
+	 * Enable devfreq-event to get raw data which is used to determine
+	 * current bus load.
+	 */
+	ret = exynos_bus_enable_edev(bus);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = exynos_bus_set_event(bus);
+	if (ret < 0) {
+		dev_err(dev, "failed to set event to devfreq-event devices\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_bus_resume(struct device *dev)
+{
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	int ret;
+
+	if (bus->regulator) {
+		ret = regulator_enable(bus->regulator);
+		if (ret < 0) {
+			dev_err(dev, "failed to enable VDD regulator\n");
+			return ret;
+		}
+	}
+
+	ret = exynos_bus_enable_edev(bus);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable the devfreq-event devices\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int exynos_bus_suspend(struct device *dev)
+{
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	int ret;
+
+	ret = exynos_bus_disable_edev(bus);
+	if (ret < 0) {
+		dev_err(dev, "failed to disable the devfreq-event devices\n");
+		return ret;
+	}
+
+	if (bus->regulator)
+		regulator_disable(bus->regulator);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops exynos_bus_pm = {
+	SET_SYSTEM_SLEEP_PM_OPS(exynos_bus_suspend, exynos_bus_resume)
+};
+
+static const struct of_device_id exynos_bus_of_match[] = {
+	{ .compatible = "samsung,exynos-bus", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, exynos_bus_of_match);
+
+static struct platform_driver exynos_bus_platdrv = {
+	.probe		= exynos_bus_probe,
+	.driver = {
+		.name	= "exynos-bus",
+		.pm	= &exynos_bus_pm,
+		.of_match_table = of_match_ptr(exynos_bus_of_match),
+	},
+};
+module_platform_driver(exynos_bus_platdrv);
+
+MODULE_DESCRIPTION("Generic Exynos Bus frequency driver");
+MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 01/19] PM / devfreq: exynos: Add generic exynos bus frequency driver Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-10  0:39   ` Krzysztof Kozlowski
  2015-12-09  4:07 ` [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250 Chanwoo Choi
                   ` (18 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the documentation for generic exynos bus frequency
driver.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt     | 94 ++++++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
new file mode 100644
index 000000000000..54a1f9c46c88
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,94 @@
+* Generic Exynos Bus frequency device
+
+The Samsung Exynos SoC have many buses for data transfer between DRAM
+and sub-blocks in SoC. Almost Exynos SoC have the common architecture
+for buses. Generally, the each bus of Exynos SoC includes the source clock
+and power line and then is able to change the clock according to the usage
+of each buses on runtime. When gathering the usage of each buses on runtime,
+thie driver uses the PPMU (Platform Performance Monitoring Unit) which
+is able to measure the current load of sub-blocks.
+
+There are a little different composition among Exynos SoC because each Exynos
+SoC has the different sub-blocks. So, this difference should be specified
+in devicetree file instead of each device driver. In result, this driver
+is able to support the bus frequency for all Exynos SoCs.
+
+Required properties for bus device:
+- compatible: Should be "samsung,exynos-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- #clock-cells: should be 1.
+- operating-points-v2: the OPP table including frequency/voltage information
+  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+- vdd-supply: the regulator to provide the buses with the voltage.
+- devfreq-events: the devfreq-event device to monitor the curret utilization
+  of buses.
+
+Optional properties for bus device:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+                   the performance count againt total cycle count.
+
+Example1:
+	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
+	power line (regulator). The MIF (Memory Interface) AXI bus is used to
+	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
+
+	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+
+	- MIF bus's frequency/voltage table
+	-----------------------
+	|Lv| Freq   | Voltage |
+	-----------------------
+	|L1| 50000  |800000   |
+	|L2| 100000 |800000   |
+	|L3| 134000 |800000   |
+	|L4| 200000 |800000   |
+	|L5| 400000 |875000   |
+	-----------------------
+
+Example2 :
+	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
+	are listed below:
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu_dmc CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <800000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <800000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <800000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <800000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <875000>;
+		};
+	};
+
+	Usage case to handle the frequency and voltage of bus on runtime
+	in exynos3250-rinato.dts are listed below:
+
+	&bus_dmc {
+		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
+		status = "okay";
+	};
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 01/19] PM / devfreq: exynos: Add generic exynos bus frequency driver Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for " Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-10  0:44   ` Krzysztof Kozlowski
  2015-12-09  4:07 ` [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk Chanwoo Choi
                   ` (17 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
SDRAM devices. The bus includes the OPP tables and the source clock for DMC
block.

Following list specifies the detailed relation between the clock and DMC block:
- The source clock of DMC block : div_dmc

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 2f30d632f1cc..7214c5e42150 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -687,6 +687,40 @@
 			clock-names = "ppmu";
 			status = "disabled";
 		};
+
+		bus_dmc: bus_dmc {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu_dmc CLK_DIV_DMC>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_dmc_opp_table>;
+			status = "disabled";
+		};
+
+		bus_dmc_opp_table: opp_table1 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp00 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <800000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <800000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <134000000>;
+				opp-microvolt = <800000>;
+			};
+			opp03 {
+				opp-hz = /bits/ 64 <200000000>;
+				opp-microvolt = <800000>;
+			};
+			opp04 {
+				opp-hz = /bits/ 64 <400000000>;
+				opp-microvolt = <875000>;
+			};
+		};
 	};
 };
 
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (2 preceding siblings ...)
  2015-12-09  4:07 ` [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250 Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-10  0:53   ` Krzysztof Kozlowski
  2015-12-09  4:07 ` [PATCH v2 05/19] PM / devfreq: Add new passive governor Chanwoo Choi
                   ` (16 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the DMC (Dynamic Memory Controller) bus frequency node
which includes the devfreq-events and regulator properties. The bus
frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
with ondemand governor.

The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
the DMC block.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos3250-monk.dts   | 6 ++++++
 arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 443a35085846..d982586a6533 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -498,6 +498,12 @@
 	};
 };
 
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
 &xusbxti {
 	clock-frequency = <24000000>;
 };
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 3e64d5dcdd60..61477943015b 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -675,6 +675,12 @@
 	};
 };
 
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
 &xusbxti {
 	clock-frequency = <24000000>;
 };
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 05/19] PM / devfreq: Add new passive governor
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (3 preceding siblings ...)
  2015-12-09  4:07 ` [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 06/19] PM / devfreq: Add devfreq_get_devfreq_by_phandle() Chanwoo Choi
                   ` (15 subsequent siblings)
  20 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the new passive governor for DEVFREQ framework. The following
governors are already present and used for DVFS (Dynamic Voltage and Frequency
Scaling) drivers. The following governors are independently used for one device
driver which don't give the influence to other device drviers and also don't
receive the effect from other device drivers.
- ondemand / performance / powersave / userspace

The passive governor depends on operation of parent driver with specific
governos extremely and is not able to decide the new frequency by oneself.
According to the decided new frequency of parent driver with governor,
the passive governor uses it to decide the appropriate frequency for own
device driver. The passive governor must need the following information
from device tree:
- the source clock and OPP tables
- the instance of parent device

For exameple,
there are one more devfreq device drivers which need to change their source
clock according to their utilization on runtime. But, they share the same
power line (e.g., regulator). So, specific device driver is operated as parent
with ondemand governor and then the rest device driver with passive governor
is influenced by parent device.

Suggested-by: Myungjoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/Kconfig            |   9 ++++
 drivers/devfreq/Makefile           |   1 +
 drivers/devfreq/devfreq.c          |  47 ++++++++++++++++
 drivers/devfreq/governor_passive.c | 108 +++++++++++++++++++++++++++++++++++++
 include/linux/devfreq.h            |  17 ++++++
 5 files changed, 182 insertions(+)
 create mode 100644 drivers/devfreq/governor_passive.c

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 55ec774f794c..d03f635a93e1 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -64,6 +64,15 @@ config DEVFREQ_GOV_USERSPACE
 	  Otherwise, the governor does not change the frequnecy
 	  given at the initialization.
 
+config DEVFREQ_GOV_PASSIVE
+	tristate "Passive"
+	help
+	  Sets the frequency by other governors (simple_ondemand, performance,
+	  powersave, usersapce) of a parent devfreq device. This governor
+	  always has the dependency on the chosen frequency from paired
+	  governor. This governor does not change the frequency by oneself
+	  through sysfs entry.
+
 comment "DEVFREQ Drivers"
 
 config ARM_EXYNOS_BUS_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 375ebbb4fcfb..f81c313b4b79 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)	+= governor_simpleondemand.o
 obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE)	+= governor_performance.o
 obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)	+= governor_powersave.o
 obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)	+= governor_userspace.o
+obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)	+= governor_passive.o
 
 # DEVFREQ Drivers
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos/
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 984c5e9e7bdd..15e58779e4c0 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -190,6 +190,31 @@ static struct devfreq_governor *find_devfreq_governor(const char *name)
 
 /* Load monitoring helper functions for governors use */
 
+static int update_devfreq_passive(struct devfreq *devfreq, unsigned long freq)
+{
+	struct devfreq *passive;
+	unsigned long rate;
+	int ret;
+
+	list_for_each_entry(passive, &devfreq->passive_dev_list, passive_node) {
+		if (!passive->governor)
+			continue;
+		rate = freq;
+
+		ret = passive->governor->get_target_freq(passive, &rate);
+		if (ret)
+			return ret;
+
+		ret = passive->profile->target(passive->dev.parent, &rate, 0);
+		if (ret)
+			return ret;
+
+		passive->previous_freq = rate;
+	}
+
+	return 0;
+}
+
 /**
  * update_devfreq() - Reevaluate the device and configure frequency.
  * @devfreq:	the devfreq instance.
@@ -233,10 +258,18 @@ int update_devfreq(struct devfreq *devfreq)
 		flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */
 	}
 
+	if (!list_empty(&devfreq->passive_dev_list)
+		&& devfreq->previous_freq > freq)
+		update_devfreq_passive(devfreq, freq);
+
 	err = devfreq->profile->target(devfreq->dev.parent, &freq, flags);
 	if (err)
 		return err;
 
+	if (!list_empty(&devfreq->passive_dev_list)
+		&& devfreq->previous_freq < freq)
+		update_devfreq_passive(devfreq, freq);
+
 	if (devfreq->profile->freq_table)
 		if (devfreq_update_status(devfreq, freq))
 			dev_err(&devfreq->dev,
@@ -442,6 +475,10 @@ static void _remove_devfreq(struct devfreq *devfreq)
 		return;
 	}
 	list_del(&devfreq->node);
+	list_del(&devfreq->passive_node);
+	if (!list_empty(&devfreq->passive_dev_list))
+		list_del_init(&devfreq->passive_dev_list);
+
 	mutex_unlock(&devfreq_list_lock);
 
 	if (devfreq->governor)
@@ -559,6 +596,16 @@ struct devfreq *devfreq_add_device(struct device *dev,
 		goto err_init;
 	}
 
+	if (!strncmp(devfreq->governor_name, "passive", 7)) {
+		struct devfreq *parent_devfreq =
+			((struct devfreq_passive_data *)data)->parent;
+
+		list_add(&devfreq->passive_node,
+			&parent_devfreq->passive_dev_list);
+	} else {
+		INIT_LIST_HEAD(&devfreq->passive_dev_list);
+	}
+
 	return devfreq;
 
 err_init:
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
new file mode 100644
index 000000000000..7443ae4b92f9
--- /dev/null
+++ b/drivers/devfreq/governor_passive.c
@@ -0,0 +1,108 @@
+/*
+ * linux/drivers/devfreq/governor_passive.c
+ *
+ * Copyright (C) 2015 Samsung Electronics
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/devfreq.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/devfreq.h>
+#include "governor.h"
+
+static int devfreq_passive_get_target_freq(struct devfreq *passive,
+					unsigned long *freq)
+{
+	struct devfreq_passive_data *passive_data = passive->data;
+	struct devfreq *parent_devfreq = passive_data->parent;
+	unsigned long child_freq = ULONG_MAX;
+	int i, count;
+
+	/*
+	 * Each devfreq has the OPP table. After deciding the new frequency
+	 * from the governor of parent devfreq device, the passive governor
+	 * need to get the index of new frequency on OPP table of parent
+	 * device. And then the index is used for getting the suitable
+	 * new frequency for passive devfreq device.
+	 */
+
+	if (!passive->profile || !passive->profile->freq_table
+		|| passive->profile->max_state <= 0)
+		return -EINVAL;
+
+	/*
+	 * When new frequency is lower than previous frequency of parent
+	 * devfreq device, passive governor get the correct frequency from OPP
+	 * list of parent device. Because in this case, *freq is temporary
+	 * value which is decided by ondemand governor.
+	 */
+	if (parent_devfreq->previous_freq > *freq) {
+		struct dev_pm_opp *opp;
+		opp = devfreq_recommended_opp(parent_devfreq->dev.parent,
+						freq, 0);
+		if (IS_ERR_OR_NULL(opp))
+			return PTR_ERR(opp);
+	}
+
+	/*
+	 * Get the OPP table's index of decided freqeuncy by governor
+	 * of parent device.
+	 */
+	for (i = 0; i < parent_devfreq->profile->max_state; i++)
+		if (parent_devfreq->profile->freq_table[i] == *freq)
+			break;
+
+	if (i == parent_devfreq->profile->max_state)
+		return -EINVAL;
+	count = passive->profile->max_state;
+
+	/* Get the suitable frequency by using index of parent device. */
+	if (i < passive->profile->max_state)
+		child_freq = passive->profile->freq_table[i];
+	else
+		child_freq = passive->profile->freq_table[count - 1];
+
+	/* Return the suitable frequency for passive device. */
+	*freq = child_freq;
+
+	return 0;
+}
+
+static int devfreq_passive_event_handler(struct devfreq *devfreq,
+				unsigned int event, void *data)
+{
+	return 0;
+}
+
+static struct devfreq_governor devfreq_passive = {
+	.name = "passive",
+	.get_target_freq = devfreq_passive_get_target_freq,
+	.event_handler = devfreq_passive_event_handler,
+};
+
+static int __init devfreq_passive_init(void)
+{
+	return devfreq_add_governor(&devfreq_passive);
+}
+subsys_initcall(devfreq_passive_init);
+
+static void __exit devfreq_passive_exit(void)
+{
+	int ret;
+
+	ret = devfreq_remove_governor(&devfreq_passive);
+	if (ret)
+		pr_err("%s: failed remove governor %d\n", __func__, ret);
+
+	return;
+}
+module_exit(devfreq_passive_exit);
+
+MODULE_AUTHOR("Chanwoo Choi <cw00.choi@samsung.com>");
+MODULE_DESCRIPTION("DEVFREQ Passive governor");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index 6fa02a20eb63..f7a6e6bd716e 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -177,6 +177,9 @@ struct devfreq {
 	unsigned int *trans_table;
 	unsigned long *time_in_state;
 	unsigned long last_stat_updated;
+
+	struct list_head passive_dev_list;
+	struct list_head passive_node;
 };
 
 #if defined(CONFIG_PM_DEVFREQ)
@@ -241,6 +244,20 @@ struct devfreq_simple_ondemand_data {
 };
 #endif
 
+#if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
+/**
+ * struct devfreq_passive_data - void *data fed to struct devfreq
+ *	and devfreq_add_device
+ * @parent:		The parent devfreq device.
+ *
+ * If the fed devfreq_passive_data pointer is NULL to the governor,
+ * the governor return ERROR.
+ */
+struct devfreq_passive_data {
+	struct devfreq *parent;
+};
+#endif
+
 #else /* !CONFIG_PM_DEVFREQ */
 static inline struct devfreq *devfreq_add_device(struct device *dev,
 					  struct devfreq_dev_profile *profile,
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 06/19] PM / devfreq: Add devfreq_get_devfreq_by_phandle()
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (4 preceding siblings ...)
  2015-12-09  4:07 ` [PATCH v2 05/19] PM / devfreq: Add new passive governor Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-09  4:07 ` [PATCH v2 07/19] PM / devfreq: Show the related information according to governor type Chanwoo Choi
                   ` (14 subsequent siblings)
  20 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the new devfreq_get_devfreq_by_phandle() OF helper function
which can find the instance of devfreq device by using phandle ("devfreq").

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/devfreq.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/devfreq.h   |  9 +++++++++
 2 files changed, 53 insertions(+)

diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 15e58779e4c0..78ea4cdaa82c 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -25,6 +25,7 @@
 #include <linux/list.h>
 #include <linux/printk.h>
 #include <linux/hrtimer.h>
+#include <linux/of.h>
 #include "governor.h"
 
 static struct class *devfreq_class;
@@ -686,6 +687,49 @@ struct devfreq *devm_devfreq_add_device(struct device *dev,
 }
 EXPORT_SYMBOL(devm_devfreq_add_device);
 
+#ifdef CONFIG_OF
+/*
+ * devfreq_get_devfreq_by_phandle - Get the devfreq device from devicetree
+ * @dev - instance to the given device
+ * @index - index into list of devfreq
+ *
+ * return the instance of devfreq device
+ */
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+	struct device_node *node;
+	struct devfreq *devfreq;
+
+	if (!dev)
+		return ERR_PTR(-EINVAL);
+
+	if (!dev->of_node)
+		return ERR_PTR(-EINVAL);
+
+	node = of_parse_phandle(dev->of_node, "devfreq", index);
+	if (!node)
+		return ERR_PTR(-ENODEV);
+
+	mutex_lock(&devfreq_list_lock);
+	list_for_each_entry(devfreq, &devfreq_list, node) {
+		if (devfreq->dev.parent
+			&& devfreq->dev.parent->of_node == node) {
+			mutex_unlock(&devfreq_list_lock);
+			return devfreq;
+		}
+	}
+	mutex_unlock(&devfreq_list_lock);
+
+	return ERR_PTR(-EPROBE_DEFER);
+}
+#else
+struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev, int index)
+{
+	return ERR_PTR(-ENODEV);
+}
+#endif /* CONFIG_OF */
+EXPORT_SYMBOL_GPL(devfreq_get_devfreq_by_phandle);
+
 /**
  * devm_devfreq_remove_device() - Resource-managed devfreq_remove_device()
  * @dev:	the device to add devfreq feature.
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index f7a6e6bd716e..d648041145ba 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -211,6 +211,9 @@ extern int devm_devfreq_register_opp_notifier(struct device *dev,
 extern void devm_devfreq_unregister_opp_notifier(struct device *dev,
 						struct devfreq *devfreq);
 
+extern struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev,
+						int index);
+
 /**
  * devfreq_update_stats() - update the last_status pointer in struct devfreq
  * @df:		the devfreq instance whose status needs updating
@@ -324,6 +327,12 @@ static inline void devm_devfreq_unregister_opp_notifier(struct device *dev,
 {
 }
 
+static inline struct devfreq *devfreq_get_devfreq_by_phandle(struct device *dev,
+							int index)
+{
+	return ERR_PTR(-ENODEV);
+}
+
 static inline int devfreq_update_stats(struct devfreq *df)
 {
 	return -EINVAL;
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 07/19] PM / devfreq: Show the related information according to governor type
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (5 preceding siblings ...)
  2015-12-09  4:07 ` [PATCH v2 06/19] PM / devfreq: Add devfreq_get_devfreq_by_phandle() Chanwoo Choi
@ 2015-12-09  4:07 ` Chanwoo Choi
  2015-12-09  4:08   ` Chanwoo Choi
                   ` (13 subsequent siblings)
  20 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:07 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch modifies the following sysfs entry of DEVFREQ framework
because the devfreq device using passive governor don't need the same
information of the devfreq device using rest governor.
- polling_interval    : passive gov don't use the sampling rate.
- available_governors : passive gov don't be changed on runtime in this version.
- trans_stat          : passive governor don't support trans_stat in this version.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/devfreq.c                 | 31 +++++++++++++++++++++++++------
 drivers/devfreq/governor.h                |  7 +++++++
 drivers/devfreq/governor_passive.c        |  1 +
 drivers/devfreq/governor_performance.c    |  1 +
 drivers/devfreq/governor_powersave.c      |  1 +
 drivers/devfreq/governor_simpleondemand.c |  1 +
 drivers/devfreq/governor_userspace.c      |  1 +
 include/linux/devfreq.h                   |  2 ++
 8 files changed, 39 insertions(+), 6 deletions(-)

diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 78ea4cdaa82c..18ad956fec93 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -597,7 +597,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
 		goto err_init;
 	}
 
-	if (!strncmp(devfreq->governor_name, "passive", 7)) {
+	if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
 		struct devfreq *parent_devfreq =
 			((struct devfreq_passive_data *)data)->parent;
 
@@ -963,13 +963,23 @@ static ssize_t available_governors_show(struct device *d,
 					struct device_attribute *attr,
 					char *buf)
 {
-	struct devfreq_governor *tmp_governor;
+	struct devfreq *devfreq = to_devfreq(d);
 	ssize_t count = 0;
 
 	mutex_lock(&devfreq_list_lock);
-	list_for_each_entry(tmp_governor, &devfreq_governor_list, node)
+	if (devfreq->governor->type == DEVFREQ_GOV_PASSIVE) {
 		count += scnprintf(&buf[count], (PAGE_SIZE - count - 2),
-				   "%s ", tmp_governor->name);
+					   "%s ", devfreq->governor->name);
+	} else {
+		struct devfreq_governor *tmp_governor;
+
+		list_for_each_entry(tmp_governor, &devfreq_governor_list, node) {
+			if (tmp_governor->type == DEVFREQ_GOV_PASSIVE)
+				continue;
+			count += scnprintf(&buf[count], (PAGE_SIZE - count - 2),
+					   "%s ", tmp_governor->name);
+		}
+	}
 	mutex_unlock(&devfreq_list_lock);
 
 	/* Truncate the trailing space */
@@ -1006,6 +1016,11 @@ static DEVICE_ATTR_RO(target_freq);
 static ssize_t polling_interval_show(struct device *dev,
 				     struct device_attribute *attr, char *buf)
 {
+	struct devfreq *df = to_devfreq(dev);
+
+	if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+		return sprintf(buf, "Not Supported.\n");
+
 	return sprintf(buf, "%d\n", to_devfreq(dev)->profile->polling_ms);
 }
 
@@ -1020,6 +1035,9 @@ static ssize_t polling_interval_store(struct device *dev,
 	if (!df->governor)
 		return -EINVAL;
 
+	if (df->governor->type == DEVFREQ_GOV_PASSIVE)
+		return -EINVAL;
+
 	ret = sscanf(buf, "%u", &value);
 	if (ret != 1)
 		return -EINVAL;
@@ -1137,11 +1155,12 @@ static ssize_t trans_stat_show(struct device *dev,
 	int i, j;
 	unsigned int max_state = devfreq->profile->max_state;
 
+	if (max_state == 0 || devfreq->governor->type == DEVFREQ_GOV_PASSIVE)
+		return sprintf(buf, "Not Supported.\n");
+
 	if (!devfreq->stop_polling &&
 			devfreq_update_status(devfreq, devfreq->previous_freq))
 		return 0;
-	if (max_state == 0)
-		return sprintf(buf, "Not Supported.\n");
 
 	len = sprintf(buf, "     From  :   To\n");
 	len += sprintf(buf + len, "           :");
diff --git a/drivers/devfreq/governor.h b/drivers/devfreq/governor.h
index fad7d6321978..43513a58f5bf 100644
--- a/drivers/devfreq/governor.h
+++ b/drivers/devfreq/governor.h
@@ -18,6 +18,13 @@
 
 #define to_devfreq(DEV)	container_of((DEV), struct devfreq, dev)
 
+/* Devfreq governor type */
+#define DEVFREQ_GOV_ONDEMAND			0x1
+#define DEVFREQ_GOV_PERFORMANCE			0x2
+#define DEVFREQ_GOV_POWERSAVE			0x3
+#define DEVFREQ_GOV_USERSPACE			0x4
+#define DEVFREQ_GOV_PASSIVE			0x4
+
 /* Devfreq events */
 #define DEVFREQ_GOV_START			0x1
 #define DEVFREQ_GOV_STOP			0x2
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index 7443ae4b92f9..adfdee9a9cd1 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -81,6 +81,7 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
 
 static struct devfreq_governor devfreq_passive = {
 	.name = "passive",
+	.type = DEVFREQ_GOV_PASSIVE,
 	.get_target_freq = devfreq_passive_get_target_freq,
 	.event_handler = devfreq_passive_event_handler,
 };
diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/governor_performance.c
index c72f942f30a8..594d8ecb13fb 100644
--- a/drivers/devfreq/governor_performance.c
+++ b/drivers/devfreq/governor_performance.c
@@ -43,6 +43,7 @@ static int devfreq_performance_handler(struct devfreq *devfreq,
 
 static struct devfreq_governor devfreq_performance = {
 	.name = "performance",
+	.type = DEVFREQ_GOV_PERFORMANCE,
 	.get_target_freq = devfreq_performance_func,
 	.event_handler = devfreq_performance_handler,
 };
diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governor_powersave.c
index 0c6bed567e6d..e2817e1f2a31 100644
--- a/drivers/devfreq/governor_powersave.c
+++ b/drivers/devfreq/governor_powersave.c
@@ -40,6 +40,7 @@ static int devfreq_powersave_handler(struct devfreq *devfreq,
 
 static struct devfreq_governor devfreq_powersave = {
 	.name = "powersave",
+	.type = DEVFREQ_GOV_POWERSAVE,
 	.get_target_freq = devfreq_powersave_func,
 	.event_handler = devfreq_powersave_handler,
 };
diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/governor_simpleondemand.c
index ae72ba5e78df..b905a535d486 100644
--- a/drivers/devfreq/governor_simpleondemand.c
+++ b/drivers/devfreq/governor_simpleondemand.c
@@ -126,6 +126,7 @@ static int devfreq_simple_ondemand_handler(struct devfreq *devfreq,
 
 static struct devfreq_governor devfreq_simple_ondemand = {
 	.name = "simple_ondemand",
+	.type = DEVFREQ_GOV_ONDEMAND,
 	.get_target_freq = devfreq_simple_ondemand_func,
 	.event_handler = devfreq_simple_ondemand_handler,
 };
diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governor_userspace.c
index 35de6e83c1fe..c78ab78a5220 100644
--- a/drivers/devfreq/governor_userspace.c
+++ b/drivers/devfreq/governor_userspace.c
@@ -138,6 +138,7 @@ static int devfreq_userspace_handler(struct devfreq *devfreq,
 
 static struct devfreq_governor devfreq_userspace = {
 	.name = "userspace",
+	.type = DEVFREQ_GOV_USERSPACE,
 	.get_target_freq = devfreq_userspace_func,
 	.event_handler = devfreq_userspace_handler,
 };
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index d648041145ba..0c39022aaf2c 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -97,6 +97,7 @@ struct devfreq_dev_profile {
  * struct devfreq_governor - Devfreq policy governor
  * @node:		list node - contains registered devfreq governors
  * @name:		Governor's name
+ * @type:		Governor's type
  * @get_target_freq:	Returns desired operating frequency for the device.
  *			Basically, get_target_freq will run
  *			devfreq_dev_profile.get_dev_status() to get the
@@ -114,6 +115,7 @@ struct devfreq_governor {
 	struct list_head node;
 
 	const char name[DEVFREQ_NAME_LEN];
+	const int type;
 	int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
 	int (*event_handler)(struct devfreq *devfreq,
 				unsigned int event, void *data);
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 08/19] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
@ 2015-12-09  4:08   ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the source clock and
regulator at the same time. So, this patch uses the passive governor to support
the bus frequency for all buses which sharing the one power line.

For example,

Exynos3250 include the two power line for AXI buses as following:
: VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller)
  with the power (regulator).
: VDD_INT : INT (Internal) provide the various sub-blocks with the power
  (regulator).

Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus
use the power line. So, there is no any depencency between buese. But, in the
case of VDD_INT, various buses share the one power line of VDD_INT. We need to
make the depenency between buses. When using passive governor, there is no
problem to support the bus frequency as DVFS for all buses. One bus should be
operated as the parent bus device which gathering the current load of INT block
and then decides the new frequency with some governors except of passive
governor. After deciding the new frequency by the parent bus device, the rest
bus devices will change the each source clock according to new frequency of the
parent bus device.

- MIF (Memory Interface) block
: VDD_MIF |--- DMC

- INT (Internal) block
: VDD_INT |--- LEFTBUS (parent)
          |--- PERIL
          |--- MFC
          |--- G3D
          |--- RIGHTBUS
	  |--- FSYS
          |--- LCD0
          |--- PERIR
          |--- ISP
          |--- CAM

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/Kconfig             |   1 +
 drivers/devfreq/exynos/exynos-bus.c | 170 ++++++++++++++++++++++++++++--------
 2 files changed, 136 insertions(+), 35 deletions(-)

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index d03f635a93e1..88f7cc4539b8 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -79,6 +79,7 @@ config ARM_EXYNOS_BUS_DEVFREQ
 	bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
 	depends on ARCH_EXYNOS
 	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select DEVFREQ_GOV_PASSIVE
 	select DEVFREQ_EVENT_EXYNOS_PPMU
 	select PM_DEVFREQ_EVENT
 	select PM_OPP
diff --git a/drivers/devfreq/exynos/exynos-bus.c b/drivers/devfreq/exynos/exynos-bus.c
index f1bc20839650..2efc2bba757e 100644
--- a/drivers/devfreq/exynos/exynos-bus.c
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -91,7 +91,7 @@ static int exynos_bus_get_event(struct exynos_bus *bus,
 }
 
 /*
- * Must necessary function for devfreq governor
+ * Must necessary function for devfreq simple-ondemand governor
  */
 static int exynos_bus_target(struct device *dev, unsigned long *freq, u32 flags)
 {
@@ -205,57 +205,74 @@ static void exynos_bus_exit(struct device *dev)
 	dev_pm_opp_of_remove_table(dev);
 }
 
-static int exynos_bus_parse_of(struct device_node *np,
-			      struct exynos_bus *bus)
+/*
+ * Must necessary function for devfreq passive governor
+ */
+static int exynos_bus_passive_target(struct device *dev, unsigned long *freq,
+					u32 flags)
 {
-	struct device *dev = bus->dev;
-	unsigned long rate;
-	int i, ret, count, size;
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	struct dev_pm_opp *new_opp;
+	unsigned long old_freq, new_freq;
+	int ret = 0;
 
-	/* Get the clock to provide each bus with source clock */
-	bus->clk = devm_clk_get(dev, "bus");
-	if (IS_ERR(bus->clk)) {
-		dev_err(dev, "failed to get bus clock\n");
-		return PTR_ERR(bus->clk);
+	/* Get new opp-bus instance according to new bus clock */
+	rcu_read_lock();
+	new_opp = devfreq_recommended_opp(dev, freq, flags);
+	if (IS_ERR_OR_NULL(new_opp)) {
+		dev_err(dev, "failed to get recommed opp instance\n");
+		rcu_read_unlock();
+		return PTR_ERR(new_opp);
 	}
 
-	ret = clk_prepare_enable(bus->clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to get enable clock\n");
-		return ret;
-	}
+	new_freq = dev_pm_opp_get_freq(new_opp);
+	old_freq = dev_pm_opp_get_freq(bus->curr_opp);
+	rcu_read_unlock();
 
-	/* Get the freq/voltage OPP table to scale the bus frequency */
-	rcu_read_lock();
-	ret = dev_pm_opp_of_add_table(dev);
+	if (old_freq == new_freq)
+		return 0;
+
+	/* Change the frequency according to new OPP level */
+	mutex_lock(&bus->lock);
+
+	ret = clk_set_rate(bus->clk, new_freq);
 	if (ret < 0) {
-		dev_err(dev, "failed to get OPP table\n");
-		rcu_read_unlock();
-		return ret;
+		dev_err(dev, "failed to set the clock of bus\n");
+		goto out;
 	}
 
-	rate = clk_get_rate(bus->clk);
-	bus->curr_opp = dev_pm_opp_find_freq_ceil(dev, &rate);
-	if (IS_ERR(bus->curr_opp)) {
-		dev_err(dev, "failed to find dev_pm_opp\n");
-		rcu_read_unlock();
-		ret = PTR_ERR(bus->curr_opp);
-		goto err_opp;
-	}
-	rcu_read_unlock();
+	bus->curr_opp = new_opp;
+
+	dev_dbg(dev, "Set the frequency of bus (%ldkHz -> %ldkHz)\n",
+			old_freq/1000, new_freq/1000);
+out:
+	mutex_unlock(&bus->lock);
+
+	return ret;
+}
+
+static void exynos_bus_passive_exit(struct device *dev)
+{
+	dev_pm_opp_of_remove_table(dev);
+}
+
+static int exynos_bus_parent_parse_of(struct device_node *np,
+					struct exynos_bus *bus)
+{
+	struct device *dev = bus->dev;
+	int i, ret, count, size;
 
 	/* Get the regulator to provide each bus with the power */
 	bus->regulator = devm_regulator_get(dev, "vdd");
 	if (IS_ERR(bus->regulator)) {
 		dev_err(dev, "failed to get VDD regulator\n");
-		ret = PTR_ERR(bus->regulator);
-		goto err_opp;
+		return PTR_ERR(bus->regulator);
 	}
 
 	ret = regulator_enable(bus->regulator);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable VDD regulator\n");
-		goto err_opp;
+		return ret;
 	}
 
 	/*
@@ -302,6 +319,51 @@ static int exynos_bus_parse_of(struct device_node *np,
 
 err_regulator:
 	regulator_disable(bus->regulator);
+
+	return ret;
+}
+
+static int exynos_bus_parse_of(struct device_node *np,
+			      struct exynos_bus *bus)
+{
+	struct device *dev = bus->dev;
+	unsigned long rate;
+	int ret;
+
+	/* Get the clock to provide each bus with source clock */
+	bus->clk = devm_clk_get(dev, "bus");
+	if (IS_ERR(bus->clk)) {
+		dev_err(dev, "failed to get bus clock\n");
+		return PTR_ERR(bus->clk);
+	}
+
+	ret = clk_prepare_enable(bus->clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get enable clock\n");
+		return ret;
+	}
+
+	/* Get the freq and voltage from OPP table to scale the bus freq */
+	rcu_read_lock();
+	ret = dev_pm_opp_of_add_table(dev);
+	if (ret < 0) {
+		dev_err(dev, "failed to get OPP table\n");
+		rcu_read_unlock();
+		return ret;
+	}
+
+	rate = clk_get_rate(bus->clk);
+	bus->curr_opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+	if (IS_ERR(bus->curr_opp)) {
+		dev_err(dev, "failed to find dev_pm_opp\n");
+		rcu_read_unlock();
+		ret = PTR_ERR(bus->curr_opp);
+		goto err_opp;
+	}
+	rcu_read_unlock();
+
+	return 0;
+
 err_opp:
 	dev_pm_opp_of_remove_table(dev);
 
@@ -314,6 +376,8 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	struct devfreq_dev_profile *profile;
 	struct devfreq_simple_ondemand_data *ondemand_data;
+	struct devfreq_passive_data *passive_data;
+	struct devfreq *parent_devfreq;
 	struct exynos_bus *bus;
 	int ret;
 
@@ -334,10 +398,19 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;
 
-	/* Initalize the struct profile and governor data */
 	profile = devm_kzalloc(dev, sizeof(*profile), GFP_KERNEL);
 	if (!profile)
 		return -ENOMEM;
+
+	if (of_parse_phandle(dev->of_node, "devfreq", 0))
+		goto passive;
+	else
+		ret = exynos_bus_parent_parse_of(np, bus);
+
+	if (ret < 0)
+		return ret;
+
+	/* Initalize the struct profile and governor data for parent device */
 	profile->polling_ms = 50;
 	profile->target = exynos_bus_target;
 	profile->get_dev_status = exynos_bus_get_dev_status;
@@ -381,6 +454,33 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	}
 
 	return 0;
+
+passive:
+	/* Initalize the struct profile and governor data for passive device */
+	profile->target = exynos_bus_passive_target;
+	profile->exit = exynos_bus_passive_exit;
+
+	passive_data = devm_kzalloc(dev, sizeof(*passive_data), GFP_KERNEL);
+	if (!passive_data)
+		return -ENOMEM;
+
+	/* Get the instance of parent devfreq device */
+	parent_devfreq = devfreq_get_devfreq_by_phandle(dev, 0);
+	if (IS_ERR(parent_devfreq)) {
+		return -EPROBE_DEFER;
+	}
+	passive_data->parent = parent_devfreq;
+
+	/* Add devfreq device for exynos bus with passive governor */
+	bus->devfreq = devm_devfreq_add_device(dev, profile, "passive",
+						passive_data);
+	if (IS_ERR_OR_NULL(bus->devfreq)) {
+		dev_err(dev,
+			"failed to add devfreq dev with passive governor\n");
+		return -EPROBE_DEFER;
+	}
+
+	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 08/19] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
@ 2015-12-09  4:08   ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ,
	k.kozlowski-Sze3O3UU22JBDgjK7y7TUQ, kgene-DgEjT+Ai2ygdnm+yROfE0A
  Cc: kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	tjakobi-o02PS0xoJP9W0yFyLvAVXMxlOr/tl8fh,
	linux.amoon-Re5JQEeQqe8AvxtiuMwx3w,
	cw00.choi-Sze3O3UU22JBDgjK7y7TUQ,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-pm-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA

This patch adds the support of bus frequency feature for sub-blocks which share
the one power line. If each bus depends on the power line, each bus is not able
to change the voltage by oneself. To optimize the power-consumption on runtime,
some buses using the same power line should change the source clock and
regulator at the same time. So, this patch uses the passive governor to support
the bus frequency for all buses which sharing the one power line.

For example,

Exynos3250 include the two power line for AXI buses as following:
: VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller)
  with the power (regulator).
: VDD_INT : INT (Internal) provide the various sub-blocks with the power
  (regulator).

Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus
use the power line. So, there is no any depencency between buese. But, in the
case of VDD_INT, various buses share the one power line of VDD_INT. We need to
make the depenency between buses. When using passive governor, there is no
problem to support the bus frequency as DVFS for all buses. One bus should be
operated as the parent bus device which gathering the current load of INT block
and then decides the new frequency with some governors except of passive
governor. After deciding the new frequency by the parent bus device, the rest
bus devices will change the each source clock according to new frequency of the
parent bus device.

- MIF (Memory Interface) block
: VDD_MIF |--- DMC

- INT (Internal) block
: VDD_INT |--- LEFTBUS (parent)
          |--- PERIL
          |--- MFC
          |--- G3D
          |--- RIGHTBUS
	  |--- FSYS
          |--- LCD0
          |--- PERIR
          |--- ISP
          |--- CAM

Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/devfreq/Kconfig             |   1 +
 drivers/devfreq/exynos/exynos-bus.c | 170 ++++++++++++++++++++++++++++--------
 2 files changed, 136 insertions(+), 35 deletions(-)

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index d03f635a93e1..88f7cc4539b8 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -79,6 +79,7 @@ config ARM_EXYNOS_BUS_DEVFREQ
 	bool "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
 	depends on ARCH_EXYNOS
 	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select DEVFREQ_GOV_PASSIVE
 	select DEVFREQ_EVENT_EXYNOS_PPMU
 	select PM_DEVFREQ_EVENT
 	select PM_OPP
diff --git a/drivers/devfreq/exynos/exynos-bus.c b/drivers/devfreq/exynos/exynos-bus.c
index f1bc20839650..2efc2bba757e 100644
--- a/drivers/devfreq/exynos/exynos-bus.c
+++ b/drivers/devfreq/exynos/exynos-bus.c
@@ -91,7 +91,7 @@ static int exynos_bus_get_event(struct exynos_bus *bus,
 }
 
 /*
- * Must necessary function for devfreq governor
+ * Must necessary function for devfreq simple-ondemand governor
  */
 static int exynos_bus_target(struct device *dev, unsigned long *freq, u32 flags)
 {
@@ -205,57 +205,74 @@ static void exynos_bus_exit(struct device *dev)
 	dev_pm_opp_of_remove_table(dev);
 }
 
-static int exynos_bus_parse_of(struct device_node *np,
-			      struct exynos_bus *bus)
+/*
+ * Must necessary function for devfreq passive governor
+ */
+static int exynos_bus_passive_target(struct device *dev, unsigned long *freq,
+					u32 flags)
 {
-	struct device *dev = bus->dev;
-	unsigned long rate;
-	int i, ret, count, size;
+	struct exynos_bus *bus = dev_get_drvdata(dev);
+	struct dev_pm_opp *new_opp;
+	unsigned long old_freq, new_freq;
+	int ret = 0;
 
-	/* Get the clock to provide each bus with source clock */
-	bus->clk = devm_clk_get(dev, "bus");
-	if (IS_ERR(bus->clk)) {
-		dev_err(dev, "failed to get bus clock\n");
-		return PTR_ERR(bus->clk);
+	/* Get new opp-bus instance according to new bus clock */
+	rcu_read_lock();
+	new_opp = devfreq_recommended_opp(dev, freq, flags);
+	if (IS_ERR_OR_NULL(new_opp)) {
+		dev_err(dev, "failed to get recommed opp instance\n");
+		rcu_read_unlock();
+		return PTR_ERR(new_opp);
 	}
 
-	ret = clk_prepare_enable(bus->clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to get enable clock\n");
-		return ret;
-	}
+	new_freq = dev_pm_opp_get_freq(new_opp);
+	old_freq = dev_pm_opp_get_freq(bus->curr_opp);
+	rcu_read_unlock();
 
-	/* Get the freq/voltage OPP table to scale the bus frequency */
-	rcu_read_lock();
-	ret = dev_pm_opp_of_add_table(dev);
+	if (old_freq == new_freq)
+		return 0;
+
+	/* Change the frequency according to new OPP level */
+	mutex_lock(&bus->lock);
+
+	ret = clk_set_rate(bus->clk, new_freq);
 	if (ret < 0) {
-		dev_err(dev, "failed to get OPP table\n");
-		rcu_read_unlock();
-		return ret;
+		dev_err(dev, "failed to set the clock of bus\n");
+		goto out;
 	}
 
-	rate = clk_get_rate(bus->clk);
-	bus->curr_opp = dev_pm_opp_find_freq_ceil(dev, &rate);
-	if (IS_ERR(bus->curr_opp)) {
-		dev_err(dev, "failed to find dev_pm_opp\n");
-		rcu_read_unlock();
-		ret = PTR_ERR(bus->curr_opp);
-		goto err_opp;
-	}
-	rcu_read_unlock();
+	bus->curr_opp = new_opp;
+
+	dev_dbg(dev, "Set the frequency of bus (%ldkHz -> %ldkHz)\n",
+			old_freq/1000, new_freq/1000);
+out:
+	mutex_unlock(&bus->lock);
+
+	return ret;
+}
+
+static void exynos_bus_passive_exit(struct device *dev)
+{
+	dev_pm_opp_of_remove_table(dev);
+}
+
+static int exynos_bus_parent_parse_of(struct device_node *np,
+					struct exynos_bus *bus)
+{
+	struct device *dev = bus->dev;
+	int i, ret, count, size;
 
 	/* Get the regulator to provide each bus with the power */
 	bus->regulator = devm_regulator_get(dev, "vdd");
 	if (IS_ERR(bus->regulator)) {
 		dev_err(dev, "failed to get VDD regulator\n");
-		ret = PTR_ERR(bus->regulator);
-		goto err_opp;
+		return PTR_ERR(bus->regulator);
 	}
 
 	ret = regulator_enable(bus->regulator);
 	if (ret < 0) {
 		dev_err(dev, "failed to enable VDD regulator\n");
-		goto err_opp;
+		return ret;
 	}
 
 	/*
@@ -302,6 +319,51 @@ static int exynos_bus_parse_of(struct device_node *np,
 
 err_regulator:
 	regulator_disable(bus->regulator);
+
+	return ret;
+}
+
+static int exynos_bus_parse_of(struct device_node *np,
+			      struct exynos_bus *bus)
+{
+	struct device *dev = bus->dev;
+	unsigned long rate;
+	int ret;
+
+	/* Get the clock to provide each bus with source clock */
+	bus->clk = devm_clk_get(dev, "bus");
+	if (IS_ERR(bus->clk)) {
+		dev_err(dev, "failed to get bus clock\n");
+		return PTR_ERR(bus->clk);
+	}
+
+	ret = clk_prepare_enable(bus->clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get enable clock\n");
+		return ret;
+	}
+
+	/* Get the freq and voltage from OPP table to scale the bus freq */
+	rcu_read_lock();
+	ret = dev_pm_opp_of_add_table(dev);
+	if (ret < 0) {
+		dev_err(dev, "failed to get OPP table\n");
+		rcu_read_unlock();
+		return ret;
+	}
+
+	rate = clk_get_rate(bus->clk);
+	bus->curr_opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+	if (IS_ERR(bus->curr_opp)) {
+		dev_err(dev, "failed to find dev_pm_opp\n");
+		rcu_read_unlock();
+		ret = PTR_ERR(bus->curr_opp);
+		goto err_opp;
+	}
+	rcu_read_unlock();
+
+	return 0;
+
 err_opp:
 	dev_pm_opp_of_remove_table(dev);
 
@@ -314,6 +376,8 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	struct devfreq_dev_profile *profile;
 	struct devfreq_simple_ondemand_data *ondemand_data;
+	struct devfreq_passive_data *passive_data;
+	struct devfreq *parent_devfreq;
 	struct exynos_bus *bus;
 	int ret;
 
@@ -334,10 +398,19 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;
 
-	/* Initalize the struct profile and governor data */
 	profile = devm_kzalloc(dev, sizeof(*profile), GFP_KERNEL);
 	if (!profile)
 		return -ENOMEM;
+
+	if (of_parse_phandle(dev->of_node, "devfreq", 0))
+		goto passive;
+	else
+		ret = exynos_bus_parent_parse_of(np, bus);
+
+	if (ret < 0)
+		return ret;
+
+	/* Initalize the struct profile and governor data for parent device */
 	profile->polling_ms = 50;
 	profile->target = exynos_bus_target;
 	profile->get_dev_status = exynos_bus_get_dev_status;
@@ -381,6 +454,33 @@ static int exynos_bus_probe(struct platform_device *pdev)
 	}
 
 	return 0;
+
+passive:
+	/* Initalize the struct profile and governor data for passive device */
+	profile->target = exynos_bus_passive_target;
+	profile->exit = exynos_bus_passive_exit;
+
+	passive_data = devm_kzalloc(dev, sizeof(*passive_data), GFP_KERNEL);
+	if (!passive_data)
+		return -ENOMEM;
+
+	/* Get the instance of parent devfreq device */
+	parent_devfreq = devfreq_get_devfreq_by_phandle(dev, 0);
+	if (IS_ERR(parent_devfreq)) {
+		return -EPROBE_DEFER;
+	}
+	passive_data->parent = parent_devfreq;
+
+	/* Add devfreq device for exynos bus with passive governor */
+	bus->devfreq = devm_devfreq_add_device(dev, profile, "passive",
+						passive_data);
+	if (IS_ERR_OR_NULL(bus->devfreq)) {
+		dev_err(dev,
+			"failed to add devfreq dev with passive governor\n");
+		return -EPROBE_DEFER;
+	}
+
+	return 0;
 }
 
 #ifdef CONFIG_PM_SLEEP
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (7 preceding siblings ...)
  2015-12-09  4:08   ` Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  1:31   ` Krzysztof Kozlowski
  2015-12-10 14:21   ` Rob Herring
  2015-12-09  4:08   ` Chanwoo Choi
                   ` (11 subsequent siblings)
  20 siblings, 2 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch updates the documentation for passive bus devices and adds the
detailed example of Exynos3250.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
 1 file changed, 241 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index 54a1f9c46c88..c4fdc70f8eac 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
 in devicetree file instead of each device driver. In result, this driver
 is able to support the bus frequency for all Exynos SoCs.
 
-Required properties for bus device:
+Required properties for all bus devices:
 - compatible: Should be "samsung,exynos-bus".
 - clock-names : the name of clock used by the bus, "bus".
 - clocks : phandles for clock specified in "clock-names" property.
 - #clock-cells: should be 1.
 - operating-points-v2: the OPP table including frequency/voltage information
   to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+
+Required properties for only parent bus device:
 - vdd-supply: the regulator to provide the buses with the voltage.
 - devfreq-events: the devfreq-event device to monitor the curret utilization
   of buses.
 
-Optional properties for bus device:
+Required properties for only passive bus device:
+- devfreq: the parent bus device.
+
+Optional properties for only parent bus device:
 - exynos,saturation-ratio: the percentage value which is used to calibrate
                    the performance count againt total cycle count.
 
@@ -33,7 +38,20 @@ Example1:
 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
 	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
 
-	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
+	- MIF (Memory Interface) block
+	: VDD_MIF |--- DMC (Dynamic Memory Controller)
+
+	- INT (Internal) block
+	: VDD_INT |--- LEFTBUS (parent device)
+		  |--- PERIL
+		  |--- MFC
+		  |--- G3D
+		  |--- RIGHTBUS
+		  |--- FSYS
+		  |--- LCD0
+		  |--- PERIR
+		  |--- ISP
+		  |--- CAM
 
 	- MIF bus's frequency/voltage table
 	-----------------------
@@ -46,6 +64,24 @@ Example1:
 	|L5| 400000 |875000   |
 	-----------------------
 
+	- INT bus's frequency/voltage table
+	----------------------------------------------------------
+	|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
+	| name|       |LCD0    |       |       |       ||        |
+	|     |       |FSYS    |       |       |       ||        |
+	|     |       |MFC     |       |       |       ||        |
+	----------------------------------------------------------
+	|Mode |*parent|passive |passive|passive|passive||        |
+	----------------------------------------------------------
+	|Lv   |Frequency                               ||Voltage |
+	----------------------------------------------------------
+	|L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
+	|L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
+	|L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
+	|L4   |134000 |134000  |200000 |200000 |       ||1000000 |
+	|L5   |200000 |200000  |400000 |300000 |       ||1000000 |
+	----------------------------------------------------------
+
 Example2 :
 	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
 	are listed below:
@@ -84,6 +120,167 @@ Example2 :
 		};
 	};
 
+	bus_leftbus: bus_leftbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_GDL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_rightbus: bus_rightbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_GDR>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_lcd0: bus_lcd0 {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_ACLK_160>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys: bus_fsys {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_ACLK_200>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mcuisp: bus_mcuisp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_mcuisp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_isp: bus_isp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_ACLK_266>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_isp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_peril: bus_perir {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_DIV_ACLK_100>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_peril_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mfc: bus_mfc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&cmu CLK_SCLK_MFC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_leftbus_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <80000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+	bus_mcuisp_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <80000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+	bus_isp_opp_table: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <80000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+	bus_peril_opp_table: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <80000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+
 	Usage case to handle the frequency and voltage of bus on runtime
 	in exynos3250-rinato.dts are listed below:
 
@@ -92,3 +289,44 @@ Example2 :
 		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
 		status = "okay";
 	};
+
+	&bus_leftbus {
+		devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+		vdd-supply = <&buck3_reg>;
+		status = "okay";
+	};
+
+	&bus_rightbus {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
+
+	&bus_lcd0 {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
+
+	&bus_fsys {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
+
+	&bus_mcuisp {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
+
+	&bus_isp {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
+
+	&bus_peril {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
+
+	&bus_mfc {
+		devfreq = <&bus_leftbus>;
+		status = "okay";
+	};
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 10/19] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
@ 2015-12-09  4:08   ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos3250, Exynos4210 and Exynos4x12.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt     | 51 ++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index c4fdc70f8eac..ed639c4f6466 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -33,6 +33,57 @@ Optional properties for only parent bus device:
 - exynos,saturation-ratio: the percentage value which is used to calibrate
                    the performance count againt total cycle count.
 
+Detailed correlation between sub-blocks and power line according to Exynos SoC:
+- In case of Exynos3250, there are two power line as following:
+	VDD_MIF |--- DMC
+
+	VDD_INT |--- LEFTBUS (parent device)
+		|--- PERIL
+		|--- MFC
+		|--- G3D
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- FSYS
+		|--- LCD0
+		|--- PERIR
+		|--- ISP
+		|--- CAM
+
+- In case of Exynos4210, there is one power line as following:
+	VDD_INT |--- DMC (parent device)
+		|--- LEFTBUS
+		|--- PERIL
+		|--- MFC(L)
+		|--- G3D
+		|--- TV
+		|--- LCD0
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- MFC(R)
+		|--- CAM
+		|--- FSYS
+		|--- GPS
+		|--- LCD0
+		|--- LCD1
+
+- In case of Exynos4x12, there are two power line as following:
+	VDD_MIF |--- DMC
+
+	VDD_INT |--- LEFTBUS (parent device)
+		|--- PERIL
+		|--- MFC(L)
+		|--- G3D
+		|--- TV
+		|--- IMAGE
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- MFC(R)
+		|--- CAM
+		|--- FSYS
+		|--- GPS
+		|--- LCD0
+		|--- ISP
+
 Example1:
 	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 10/19] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
@ 2015-12-09  4:08   ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ,
	k.kozlowski-Sze3O3UU22JBDgjK7y7TUQ, kgene-DgEjT+Ai2ygdnm+yROfE0A
  Cc: kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	tjakobi-o02PS0xoJP9W0yFyLvAVXMxlOr/tl8fh,
	linux.amoon-Re5JQEeQqe8AvxtiuMwx3w,
	cw00.choi-Sze3O3UU22JBDgjK7y7TUQ,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-pm-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos3250, Exynos4210 and Exynos4x12.

Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 .../devicetree/bindings/devfreq/exynos-bus.txt     | 51 ++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index c4fdc70f8eac..ed639c4f6466 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -33,6 +33,57 @@ Optional properties for only parent bus device:
 - exynos,saturation-ratio: the percentage value which is used to calibrate
                    the performance count againt total cycle count.
 
+Detailed correlation between sub-blocks and power line according to Exynos SoC:
+- In case of Exynos3250, there are two power line as following:
+	VDD_MIF |--- DMC
+
+	VDD_INT |--- LEFTBUS (parent device)
+		|--- PERIL
+		|--- MFC
+		|--- G3D
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- FSYS
+		|--- LCD0
+		|--- PERIR
+		|--- ISP
+		|--- CAM
+
+- In case of Exynos4210, there is one power line as following:
+	VDD_INT |--- DMC (parent device)
+		|--- LEFTBUS
+		|--- PERIL
+		|--- MFC(L)
+		|--- G3D
+		|--- TV
+		|--- LCD0
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- MFC(R)
+		|--- CAM
+		|--- FSYS
+		|--- GPS
+		|--- LCD0
+		|--- LCD1
+
+- In case of Exynos4x12, there are two power line as following:
+	VDD_MIF |--- DMC
+
+	VDD_INT |--- LEFTBUS (parent device)
+		|--- PERIL
+		|--- MFC(L)
+		|--- G3D
+		|--- TV
+		|--- IMAGE
+		|--- RIGHTBUS
+		|--- PERIR
+		|--- MFC(R)
+		|--- CAM
+		|--- FSYS
+		|--- GPS
+		|--- LCD0
+		|--- ISP
+
 Example1:
 	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 11/19] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (9 preceding siblings ...)
  2015-12-09  4:08   ` Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-09  4:08 ` [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Chanwoo Choi
                   ` (9 subsequent siblings)
  20 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch removes the unused exynos4/5 busfreq driver. Instead,
generic exynos-bus frequency driver support the all Exynos SoCs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/devfreq/Kconfig              |   22 -
 drivers/devfreq/exynos/Makefile      |    2 -
 drivers/devfreq/exynos/exynos4_bus.c | 1055 ----------------------------------
 drivers/devfreq/exynos/exynos4_bus.h |  110 ----
 drivers/devfreq/exynos/exynos5_bus.c |  431 --------------
 drivers/devfreq/exynos/exynos_ppmu.c |  119 ----
 drivers/devfreq/exynos/exynos_ppmu.h |   86 ---
 7 files changed, 1825 deletions(-)
 delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
 delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
 delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
 delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
 delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 88f7cc4539b8..e82b1d8cd200 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -91,28 +91,6 @@ config ARM_EXYNOS_BUS_DEVFREQ
 	  and adjusts the operating frequencies and voltages with OPP support.
 	  This does not yet operate with optimal voltages.
 
-config ARM_EXYNOS4_BUS_DEVFREQ
-	bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
-	depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
-	select DEVFREQ_GOV_SIMPLE_ONDEMAND
-	select PM_OPP
-	help
-	  This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
-	  and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
-	  It reads PPMU counters of memory controllers and adjusts
-	  the operating frequencies and voltages with OPP support.
-	  This does not yet operate with optimal voltages.
-
-config ARM_EXYNOS5_BUS_DEVFREQ
-	tristate "ARM Exynos5250 Bus DEVFREQ Driver"
-	depends on SOC_EXYNOS5250
-	select DEVFREQ_GOV_SIMPLE_ONDEMAND
-	select PM_OPP
-	help
-	  This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).
-	  It reads PPMU counters of memory controllers and adjusts the
-	  operating frequencies and voltages with OPP support.
-
 config ARM_TEGRA_DEVFREQ
        tristate "Tegra DEVFREQ Driver"
        depends on ARCH_TEGRA_124_SOC
diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile
index 4ec06d322996..bc695ad81c7d 100644
--- a/drivers/devfreq/exynos/Makefile
+++ b/drivers/devfreq/exynos/Makefile
@@ -1,4 +1,2 @@
 # Exynos DEVFREQ Drivers
 obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o
-obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)	+= exynos_ppmu.o exynos4_bus.o
-obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)	+= exynos_ppmu.o exynos5_bus.o
diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c
deleted file mode 100644
index da9509205169..000000000000
--- a/drivers/devfreq/exynos/exynos4_bus.c
+++ /dev/null
@@ -1,1055 +0,0 @@
-/* drivers/devfreq/exynos4210_memorybus.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com/
- *	MyungJoo Ham <myungjoo.ham@samsung.com>
- *
- * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
- *	This version supports EXYNOS4210 only. This changes bus frequencies
- *	and vddint voltages. Exynos4412/4212 should be able to be supported
- *	with minor modifications.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/mutex.h>
-#include <linux/suspend.h>
-#include <linux/pm_opp.h>
-#include <linux/devfreq.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/consumer.h>
-#include <linux/module.h>
-
-#include <mach/map.h>
-
-#include "exynos_ppmu.h"
-#include "exynos4_bus.h"
-
-#define MAX_SAFEVOLT	1200000 /* 1.2V */
-
-enum exynos4_busf_type {
-	TYPE_BUSF_EXYNOS4210,
-	TYPE_BUSF_EXYNOS4x12,
-};
-
-/* Assume that the bus is saturated if the utilization is 40% */
-#define BUS_SATURATION_RATIO	40
-
-enum busclk_level_idx {
-	LV_0 = 0,
-	LV_1,
-	LV_2,
-	LV_3,
-	LV_4,
-	_LV_END
-};
-
-enum exynos_ppmu_idx {
-	PPMU_DMC0,
-	PPMU_DMC1,
-	PPMU_END,
-};
-
-#define EX4210_LV_MAX	LV_2
-#define EX4x12_LV_MAX	LV_4
-#define EX4210_LV_NUM	(LV_2 + 1)
-#define EX4x12_LV_NUM	(LV_4 + 1)
-
-/**
- * struct busfreq_opp_info - opp information for bus
- * @rate:	Frequency in hertz
- * @volt:	Voltage in microvolts corresponding to this OPP
- */
-struct busfreq_opp_info {
-	unsigned long rate;
-	unsigned long volt;
-};
-
-struct busfreq_data {
-	enum exynos4_busf_type type;
-	struct device *dev;
-	struct devfreq *devfreq;
-	bool disabled;
-	struct regulator *vdd_int;
-	struct regulator *vdd_mif; /* Exynos4412/4212 only */
-	struct busfreq_opp_info curr_oppinfo;
-	struct busfreq_ppmu_data ppmu_data;
-
-	struct notifier_block pm_notifier;
-	struct mutex lock;
-
-	/* Dividers calculated at boot/probe-time */
-	unsigned int dmc_divtable[_LV_END]; /* DMC0 */
-	unsigned int top_divtable[_LV_END];
-};
-
-/* 4210 controls clock of mif and voltage of int */
-static struct bus_opp_table exynos4210_busclk_table[] = {
-	{LV_0, 400000, 1150000},
-	{LV_1, 267000, 1050000},
-	{LV_2, 133000, 1025000},
-	{0, 0, 0},
-};
-
-/*
- * MIF is the main control knob clock for Exynos4x12 MIF/INT
- * clock and voltage of both mif/int are controlled.
- */
-static struct bus_opp_table exynos4x12_mifclk_table[] = {
-	{LV_0, 400000, 1100000},
-	{LV_1, 267000, 1000000},
-	{LV_2, 160000, 950000},
-	{LV_3, 133000, 950000},
-	{LV_4, 100000, 950000},
-	{0, 0, 0},
-};
-
-/*
- * INT is not the control knob of 4x12. LV_x is not meant to represent
- * the current performance. (MIF does)
- */
-static struct bus_opp_table exynos4x12_intclk_table[] = {
-	{LV_0, 200000, 1000000},
-	{LV_1, 160000, 950000},
-	{LV_2, 133000, 925000},
-	{LV_3, 100000, 900000},
-	{0, 0, 0},
-};
-
-/* TODO: asv volt definitions are "__initdata"? */
-/* Some chips have different operating voltages */
-static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
-	{1150000, 1050000, 1050000},
-	{1125000, 1025000, 1025000},
-	{1100000, 1000000, 1000000},
-	{1075000, 975000, 975000},
-	{1050000, 950000, 950000},
-};
-
-static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
-	/* 400      267     160     133     100 */
-	{1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
-	{1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
-	{1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
-	{1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
-	{1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
-	{1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
-	{1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
-	{1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
-	{1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
-};
-
-static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
-	/* 200    160      133     100 */
-	{1000000, 950000, 925000, 900000}, /* ASV0 */
-	{975000,  925000, 925000, 900000}, /* ASV1 */
-	{950000,  925000, 900000, 875000}, /* ASV2 */
-	{950000,  900000, 900000, 875000}, /* ASV3 */
-	{925000,  875000, 875000, 875000}, /* ASV4 */
-	{900000,  850000, 850000, 850000}, /* ASV5 */
-	{900000,  850000, 850000, 850000}, /* ASV6 */
-	{900000,  850000, 850000, 850000}, /* ASV7 */
-	{900000,  850000, 850000, 850000}, /* ASV8 */
-};
-
-/*** Clock Divider Data for Exynos4210 ***/
-static unsigned int exynos4210_clkdiv_dmc0[][8] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
-	 *		DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
-	 */
-
-	/* DMC L0: 400MHz */
-	{ 3, 1, 1, 1, 1, 1, 3, 1 },
-	/* DMC L1: 266.7MHz */
-	{ 4, 1, 1, 2, 1, 1, 3, 1 },
-	/* DMC L2: 133MHz */
-	{ 5, 1, 1, 5, 1, 1, 3, 1 },
-};
-static unsigned int exynos4210_clkdiv_top[][5] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
-	 */
-	/* ACLK200 L0: 200MHz */
-	{ 3, 7, 4, 5, 1 },
-	/* ACLK200 L1: 160MHz */
-	{ 4, 7, 5, 6, 1 },
-	/* ACLK200 L2: 133MHz */
-	{ 5, 7, 7, 7, 1 },
-};
-static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVGDL/R, DIVGPL/R }
-	 */
-	/* ACLK_GDL/R L1: 200MHz */
-	{ 3, 1 },
-	/* ACLK_GDL/R L2: 160MHz */
-	{ 4, 1 },
-	/* ACLK_GDL/R L3: 133MHz */
-	{ 5, 1 },
-};
-
-/*** Clock Divider Data for Exynos4212/4412 ***/
-static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
-	 *              DIVDMCP}
-	 */
-
-	/* DMC L0: 400MHz */
-	{3, 1, 1, 1, 1, 1},
-	/* DMC L1: 266.7MHz */
-	{4, 1, 1, 2, 1, 1},
-	/* DMC L2: 160MHz */
-	{5, 1, 1, 4, 1, 1},
-	/* DMC L3: 133MHz */
-	{5, 1, 1, 5, 1, 1},
-	/* DMC L4: 100MHz */
-	{7, 1, 1, 7, 1, 1},
-};
-static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
-	/*
-	 * Clock divider value for following
-	 * { G2DACP, DIVC2C, DIVC2C_ACLK }
-	 */
-
-	/* DMC L0: 400MHz */
-	{3, 1, 1},
-	/* DMC L1: 266.7MHz */
-	{4, 2, 1},
-	/* DMC L2: 160MHz */
-	{5, 4, 1},
-	/* DMC L3: 133MHz */
-	{5, 5, 1},
-	/* DMC L4: 100MHz */
-	{7, 7, 1},
-};
-static unsigned int exynos4x12_clkdiv_top[][5] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
-		DIVACLK133, DIVONENAND }
-	 */
-
-	/* ACLK_GDL/R L0: 200MHz */
-	{2, 7, 4, 5, 1},
-	/* ACLK_GDL/R L1: 200MHz */
-	{2, 7, 4, 5, 1},
-	/* ACLK_GDL/R L2: 160MHz */
-	{4, 7, 5, 7, 1},
-	/* ACLK_GDL/R L3: 133MHz */
-	{4, 7, 5, 7, 1},
-	/* ACLK_GDL/R L4: 100MHz */
-	{7, 7, 7, 7, 1},
-};
-static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVGDL/R, DIVGPL/R }
-	 */
-
-	/* ACLK_GDL/R L0: 200MHz */
-	{3, 1},
-	/* ACLK_GDL/R L1: 200MHz */
-	{3, 1},
-	/* ACLK_GDL/R L2: 160MHz */
-	{4, 1},
-	/* ACLK_GDL/R L3: 133MHz */
-	{5, 1},
-	/* ACLK_GDL/R L4: 100MHz */
-	{7, 1},
-};
-static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
-	/*
-	 * Clock divider value for following
-	 * { DIVMFC, DIVJPEG, DIVFIMC0~3}
-	 */
-
-	/* SCLK_MFC: 200MHz */
-	{3, 3, 4},
-	/* SCLK_MFC: 200MHz */
-	{3, 3, 4},
-	/* SCLK_MFC: 160MHz */
-	{4, 4, 5},
-	/* SCLK_MFC: 133MHz */
-	{5, 5, 5},
-	/* SCLK_MFC: 100MHz */
-	{7, 7, 7},
-};
-
-
-static int exynos4210_set_busclk(struct busfreq_data *data,
-				 struct busfreq_opp_info *oppi)
-{
-	unsigned int index;
-	unsigned int tmp;
-
-	for (index = LV_0; index < EX4210_LV_NUM; index++)
-		if (oppi->rate == exynos4210_busclk_table[index].clk)
-			break;
-
-	if (index == EX4210_LV_NUM)
-		return -EINVAL;
-
-	/* Change Divider - DMC0 */
-	tmp = data->dmc_divtable[index];
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
-	} while (tmp & 0x11111111);
-
-	/* Change Divider - TOP */
-	tmp = data->top_divtable[index];
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
-	} while (tmp & 0x11111);
-
-	/* Change Divider - LEFTBUS */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
-
-	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
-
-	tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
-				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
-		(exynos4210_clkdiv_lr_bus[index][1] <<
-				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
-	} while (tmp & 0x11);
-
-	/* Change Divider - RIGHTBUS */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
-
-	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
-
-	tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
-				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
-		(exynos4210_clkdiv_lr_bus[index][1] <<
-				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
-	} while (tmp & 0x11);
-
-	return 0;
-}
-
-static int exynos4x12_set_busclk(struct busfreq_data *data,
-				 struct busfreq_opp_info *oppi)
-{
-	unsigned int index;
-	unsigned int tmp;
-
-	for (index = LV_0; index < EX4x12_LV_NUM; index++)
-		if (oppi->rate == exynos4x12_mifclk_table[index].clk)
-			break;
-
-	if (index == EX4x12_LV_NUM)
-		return -EINVAL;
-
-	/* Change Divider - DMC0 */
-	tmp = data->dmc_divtable[index];
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
-	} while (tmp & 0x11111111);
-
-	/* Change Divider - DMC1 */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
-
-	tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
-		EXYNOS4_CLKDIV_DMC1_C2C_MASK |
-		EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
-				EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
-		(exynos4x12_clkdiv_dmc1[index][1] <<
-				EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
-		(exynos4x12_clkdiv_dmc1[index][2] <<
-				EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
-	} while (tmp & 0x111111);
-
-	/* Change Divider - TOP */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
-
-	tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
-		EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
-		EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
-		EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
-		EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_top[index][0] <<
-				EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
-		(exynos4x12_clkdiv_top[index][1] <<
-				EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
-		(exynos4x12_clkdiv_top[index][2] <<
-				EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
-		(exynos4x12_clkdiv_top[index][3] <<
-				EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
-		(exynos4x12_clkdiv_top[index][4] <<
-				EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
-	} while (tmp & 0x11111);
-
-	/* Change Divider - LEFTBUS */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
-
-	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
-				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
-		(exynos4x12_clkdiv_lr_bus[index][1] <<
-				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
-	} while (tmp & 0x11);
-
-	/* Change Divider - RIGHTBUS */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
-
-	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
-				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
-		(exynos4x12_clkdiv_lr_bus[index][1] <<
-				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
-	} while (tmp & 0x11);
-
-	/* Change Divider - MFC */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
-
-	tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
-				EXYNOS4_CLKDIV_MFC_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
-	} while (tmp & 0x1);
-
-	/* Change Divider - JPEG */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
-
-	tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
-				EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
-	} while (tmp & 0x1);
-
-	/* Change Divider - FIMC0~3 */
-	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
-
-	tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
-		EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
-
-	tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
-				EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
-		(exynos4x12_clkdiv_sclkip[index][2] <<
-				EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
-		(exynos4x12_clkdiv_sclkip[index][2] <<
-				EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
-		(exynos4x12_clkdiv_sclkip[index][2] <<
-				EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
-
-	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
-
-	do {
-		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
-	} while (tmp & 0x1111);
-
-	return 0;
-}
-
-static int exynos4x12_get_intspec(unsigned long mifclk)
-{
-	int i = 0;
-
-	while (exynos4x12_intclk_table[i].clk) {
-		if (exynos4x12_intclk_table[i].clk <= mifclk)
-			return i;
-		i++;
-	}
-
-	return -EINVAL;
-}
-
-static int exynos4_bus_setvolt(struct busfreq_data *data,
-			       struct busfreq_opp_info *oppi,
-			       struct busfreq_opp_info *oldoppi)
-{
-	int err = 0, tmp;
-	unsigned long volt = oppi->volt;
-
-	switch (data->type) {
-	case TYPE_BUSF_EXYNOS4210:
-		/* OPP represents DMC clock + INT voltage */
-		err = regulator_set_voltage(data->vdd_int, volt,
-					    MAX_SAFEVOLT);
-		break;
-	case TYPE_BUSF_EXYNOS4x12:
-		/* OPP represents MIF clock + MIF voltage */
-		err = regulator_set_voltage(data->vdd_mif, volt,
-					    MAX_SAFEVOLT);
-		if (err)
-			break;
-
-		tmp = exynos4x12_get_intspec(oppi->rate);
-		if (tmp < 0) {
-			err = tmp;
-			regulator_set_voltage(data->vdd_mif,
-					      oldoppi->volt,
-					      MAX_SAFEVOLT);
-			break;
-		}
-		err = regulator_set_voltage(data->vdd_int,
-					    exynos4x12_intclk_table[tmp].volt,
-					    MAX_SAFEVOLT);
-		/*  Try to recover */
-		if (err)
-			regulator_set_voltage(data->vdd_mif,
-					      oldoppi->volt,
-					      MAX_SAFEVOLT);
-		break;
-	default:
-		err = -EINVAL;
-	}
-
-	return err;
-}
-
-static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
-			      u32 flags)
-{
-	int err = 0;
-	struct platform_device *pdev = container_of(dev, struct platform_device,
-						    dev);
-	struct busfreq_data *data = platform_get_drvdata(pdev);
-	struct dev_pm_opp *opp;
-	unsigned long freq;
-	unsigned long old_freq = data->curr_oppinfo.rate;
-	struct busfreq_opp_info	new_oppinfo;
-
-	rcu_read_lock();
-	opp = devfreq_recommended_opp(dev, _freq, flags);
-	if (IS_ERR(opp)) {
-		rcu_read_unlock();
-		return PTR_ERR(opp);
-	}
-	new_oppinfo.rate = dev_pm_opp_get_freq(opp);
-	new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
-	rcu_read_unlock();
-	freq = new_oppinfo.rate;
-
-	if (old_freq == freq)
-		return 0;
-
-	dev_dbg(dev, "targeting %lukHz %luuV\n", freq, new_oppinfo.volt);
-
-	mutex_lock(&data->lock);
-
-	if (data->disabled)
-		goto out;
-
-	if (old_freq < freq)
-		err = exynos4_bus_setvolt(data, &new_oppinfo,
-					  &data->curr_oppinfo);
-	if (err)
-		goto out;
-
-	if (old_freq != freq) {
-		switch (data->type) {
-		case TYPE_BUSF_EXYNOS4210:
-			err = exynos4210_set_busclk(data, &new_oppinfo);
-			break;
-		case TYPE_BUSF_EXYNOS4x12:
-			err = exynos4x12_set_busclk(data, &new_oppinfo);
-			break;
-		default:
-			err = -EINVAL;
-		}
-	}
-	if (err)
-		goto out;
-
-	if (old_freq > freq)
-		err = exynos4_bus_setvolt(data, &new_oppinfo,
-					  &data->curr_oppinfo);
-	if (err)
-		goto out;
-
-	data->curr_oppinfo = new_oppinfo;
-out:
-	mutex_unlock(&data->lock);
-	return err;
-}
-
-static int exynos4_bus_get_dev_status(struct device *dev,
-				      struct devfreq_dev_status *stat)
-{
-	struct busfreq_data *data = dev_get_drvdata(dev);
-	struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
-	int busier;
-
-	exynos_read_ppmu(ppmu_data);
-	busier = exynos_get_busier_ppmu(ppmu_data);
-	stat->current_frequency = data->curr_oppinfo.rate;
-
-	/* Number of cycles spent on memory access */
-	stat->busy_time = ppmu_data->ppmu[busier].count[PPMU_PMNCNT3];
-	stat->busy_time *= 100 / BUS_SATURATION_RATIO;
-	stat->total_time = ppmu_data->ppmu[busier].ccnt;
-
-	/* If the counters have overflown, retry */
-	if (ppmu_data->ppmu[busier].ccnt_overflow ||
-	    ppmu_data->ppmu[busier].count_overflow[0])
-		return -EAGAIN;
-
-	return 0;
-}
-
-static struct devfreq_dev_profile exynos4_devfreq_profile = {
-	.initial_freq	= 400000,
-	.polling_ms	= 50,
-	.target		= exynos4_bus_target,
-	.get_dev_status	= exynos4_bus_get_dev_status,
-};
-
-static int exynos4210_init_tables(struct busfreq_data *data)
-{
-	u32 tmp;
-	int mgrp;
-	int i, err = 0;
-
-	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
-	for (i = LV_0; i < EX4210_LV_NUM; i++) {
-		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
-			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
-			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
-			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
-			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
-			EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
-			EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
-			EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
-
-		tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
-					EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][1] <<
-					EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][2] <<
-					EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][3] <<
-					EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][4] <<
-					EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][5] <<
-					EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][6] <<
-					EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
-			(exynos4210_clkdiv_dmc0[i][7] <<
-					EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
-
-		data->dmc_divtable[i] = tmp;
-	}
-
-	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
-	for (i = LV_0; i <  EX4210_LV_NUM; i++) {
-		tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
-			EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
-			EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
-			EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
-			EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
-
-		tmp |= ((exynos4210_clkdiv_top[i][0] <<
-					EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
-			(exynos4210_clkdiv_top[i][1] <<
-					EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
-			(exynos4210_clkdiv_top[i][2] <<
-					EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
-			(exynos4210_clkdiv_top[i][3] <<
-					EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
-			(exynos4210_clkdiv_top[i][4] <<
-					EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
-
-		data->top_divtable[i] = tmp;
-	}
-
-	/*
-	 * TODO: init tmp based on busfreq_data
-	 * (device-tree or platform-data)
-	 */
-	tmp = 0; /* Max voltages for the reliability of the unknown */
-
-	pr_debug("ASV Group of Exynos4 is %d\n", tmp);
-	/* Use merged grouping for voltage */
-	switch (tmp) {
-	case 0:
-		mgrp = 0;
-		break;
-	case 1:
-	case 2:
-		mgrp = 1;
-		break;
-	case 3:
-	case 4:
-		mgrp = 2;
-		break;
-	case 5:
-	case 6:
-		mgrp = 3;
-		break;
-	case 7:
-		mgrp = 4;
-		break;
-	default:
-		pr_warn("Unknown ASV Group. Use max voltage.\n");
-		mgrp = 0;
-	}
-
-	for (i = LV_0; i < EX4210_LV_NUM; i++)
-		exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
-
-	for (i = LV_0; i < EX4210_LV_NUM; i++) {
-		err = dev_pm_opp_add(data->dev, exynos4210_busclk_table[i].clk,
-			      exynos4210_busclk_table[i].volt);
-		if (err) {
-			dev_err(data->dev, "Cannot add opp entries.\n");
-			return err;
-		}
-	}
-
-
-	return 0;
-}
-
-static int exynos4x12_init_tables(struct busfreq_data *data)
-{
-	unsigned int i;
-	unsigned int tmp;
-	int ret;
-
-	/* Enable pause function for DREX2 DVFS */
-	tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
-	tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
-	__raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
-
-	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
-
-	for (i = 0; i <  EX4x12_LV_NUM; i++) {
-		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
-			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
-			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
-			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
-			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
-			EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
-
-		tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
-					EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
-			(exynos4x12_clkdiv_dmc0[i][1] <<
-					EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
-			(exynos4x12_clkdiv_dmc0[i][2] <<
-					EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
-			(exynos4x12_clkdiv_dmc0[i][3] <<
-					EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
-			(exynos4x12_clkdiv_dmc0[i][4] <<
-					EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
-			(exynos4x12_clkdiv_dmc0[i][5] <<
-					EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
-
-		data->dmc_divtable[i] = tmp;
-	}
-
-	tmp = 0; /* Max voltages for the reliability of the unknown */
-
-	if (tmp > 8)
-		tmp = 0;
-	pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
-
-	for (i = 0; i < EX4x12_LV_NUM; i++) {
-		exynos4x12_mifclk_table[i].volt =
-			exynos4x12_mif_step_50[tmp][i];
-		exynos4x12_intclk_table[i].volt =
-			exynos4x12_int_volt[tmp][i];
-	}
-
-	for (i = 0; i < EX4x12_LV_NUM; i++) {
-		ret = dev_pm_opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
-			      exynos4x12_mifclk_table[i].volt);
-		if (ret) {
-			dev_err(data->dev, "Fail to add opp entries.\n");
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
-		unsigned long event, void *ptr)
-{
-	struct busfreq_data *data = container_of(this, struct busfreq_data,
-						 pm_notifier);
-	struct dev_pm_opp *opp;
-	struct busfreq_opp_info	new_oppinfo;
-	unsigned long maxfreq = ULONG_MAX;
-	int err = 0;
-
-	switch (event) {
-	case PM_SUSPEND_PREPARE:
-		/* Set Fastest and Deactivate DVFS */
-		mutex_lock(&data->lock);
-
-		data->disabled = true;
-
-		rcu_read_lock();
-		opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq);
-		if (IS_ERR(opp)) {
-			rcu_read_unlock();
-			dev_err(data->dev, "%s: unable to find a min freq\n",
-				__func__);
-			mutex_unlock(&data->lock);
-			return PTR_ERR(opp);
-		}
-		new_oppinfo.rate = dev_pm_opp_get_freq(opp);
-		new_oppinfo.volt = dev_pm_opp_get_voltage(opp);
-		rcu_read_unlock();
-
-		err = exynos4_bus_setvolt(data, &new_oppinfo,
-					  &data->curr_oppinfo);
-		if (err)
-			goto unlock;
-
-		switch (data->type) {
-		case TYPE_BUSF_EXYNOS4210:
-			err = exynos4210_set_busclk(data, &new_oppinfo);
-			break;
-		case TYPE_BUSF_EXYNOS4x12:
-			err = exynos4x12_set_busclk(data, &new_oppinfo);
-			break;
-		default:
-			err = -EINVAL;
-		}
-		if (err)
-			goto unlock;
-
-		data->curr_oppinfo = new_oppinfo;
-unlock:
-		mutex_unlock(&data->lock);
-		if (err)
-			return err;
-		return NOTIFY_OK;
-	case PM_POST_RESTORE:
-	case PM_POST_SUSPEND:
-		/* Reactivate */
-		mutex_lock(&data->lock);
-		data->disabled = false;
-		mutex_unlock(&data->lock);
-		return NOTIFY_OK;
-	}
-
-	return NOTIFY_DONE;
-}
-
-static int exynos4_busfreq_probe(struct platform_device *pdev)
-{
-	struct busfreq_data *data;
-	struct busfreq_ppmu_data *ppmu_data;
-	struct dev_pm_opp *opp;
-	struct device *dev = &pdev->dev;
-	int err = 0;
-
-	data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL);
-	if (data == NULL) {
-		dev_err(dev, "Cannot allocate memory.\n");
-		return -ENOMEM;
-	}
-
-	ppmu_data = &data->ppmu_data;
-	ppmu_data->ppmu_end = PPMU_END;
-	ppmu_data->ppmu = devm_kzalloc(dev,
-				       sizeof(struct exynos_ppmu) * PPMU_END,
-				       GFP_KERNEL);
-	if (!ppmu_data->ppmu) {
-		dev_err(dev, "Failed to allocate memory for exynos_ppmu\n");
-		return -ENOMEM;
-	}
-
-	data->type = pdev->id_entry->driver_data;
-	ppmu_data->ppmu[PPMU_DMC0].hw_base = S5P_VA_DMC0;
-	ppmu_data->ppmu[PPMU_DMC1].hw_base = S5P_VA_DMC1;
-	data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
-	data->dev = dev;
-	mutex_init(&data->lock);
-
-	switch (data->type) {
-	case TYPE_BUSF_EXYNOS4210:
-		err = exynos4210_init_tables(data);
-		break;
-	case TYPE_BUSF_EXYNOS4x12:
-		err = exynos4x12_init_tables(data);
-		break;
-	default:
-		dev_err(dev, "Cannot determine the device id %d\n", data->type);
-		err = -EINVAL;
-	}
-	if (err) {
-		dev_err(dev, "Cannot initialize busfreq table %d\n",
-			     data->type);
-		return err;
-	}
-
-	data->vdd_int = devm_regulator_get(dev, "vdd_int");
-	if (IS_ERR(data->vdd_int)) {
-		dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
-		return PTR_ERR(data->vdd_int);
-	}
-	if (data->type == TYPE_BUSF_EXYNOS4x12) {
-		data->vdd_mif = devm_regulator_get(dev, "vdd_mif");
-		if (IS_ERR(data->vdd_mif)) {
-			dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
-			return PTR_ERR(data->vdd_mif);
-		}
-	}
-
-	rcu_read_lock();
-	opp = dev_pm_opp_find_freq_floor(dev,
-					 &exynos4_devfreq_profile.initial_freq);
-	if (IS_ERR(opp)) {
-		rcu_read_unlock();
-		dev_err(dev, "Invalid initial frequency %lu kHz.\n",
-			exynos4_devfreq_profile.initial_freq);
-		return PTR_ERR(opp);
-	}
-	data->curr_oppinfo.rate = dev_pm_opp_get_freq(opp);
-	data->curr_oppinfo.volt = dev_pm_opp_get_voltage(opp);
-	rcu_read_unlock();
-
-	platform_set_drvdata(pdev, data);
-
-	data->devfreq = devm_devfreq_add_device(dev, &exynos4_devfreq_profile,
-					   "simple_ondemand", NULL);
-	if (IS_ERR(data->devfreq))
-		return PTR_ERR(data->devfreq);
-
-	/*
-	 * Start PPMU (Performance Profiling Monitoring Unit) to check
-	 * utilization of each IP in the Exynos4 SoC.
-	 */
-	busfreq_mon_reset(ppmu_data);
-
-	/* Register opp_notifier for Exynos4 busfreq */
-	err = devm_devfreq_register_opp_notifier(dev, data->devfreq);
-	if (err < 0) {
-		dev_err(dev, "Failed to register opp notifier\n");
-		return err;
-	}
-
-	/* Register pm_notifier for Exynos4 busfreq */
-	err = register_pm_notifier(&data->pm_notifier);
-	if (err) {
-		dev_err(dev, "Failed to setup pm notifier\n");
-		return err;
-	}
-
-	return 0;
-}
-
-static int exynos4_busfreq_remove(struct platform_device *pdev)
-{
-	struct busfreq_data *data = platform_get_drvdata(pdev);
-
-	/* Unregister all of notifier chain */
-	unregister_pm_notifier(&data->pm_notifier);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_busfreq_resume(struct device *dev)
-{
-	struct busfreq_data *data = dev_get_drvdata(dev);
-	struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
-
-	busfreq_mon_reset(ppmu_data);
-	return 0;
-}
-#endif
-
-static SIMPLE_DEV_PM_OPS(exynos4_busfreq_pm_ops, NULL, exynos4_busfreq_resume);
-
-static const struct platform_device_id exynos4_busfreq_id[] = {
-	{ "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
-	{ "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
-	{ "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
-	{ },
-};
-
-static struct platform_driver exynos4_busfreq_driver = {
-	.probe	= exynos4_busfreq_probe,
-	.remove	= exynos4_busfreq_remove,
-	.id_table = exynos4_busfreq_id,
-	.driver = {
-		.name	= "exynos4-busfreq",
-		.pm	= &exynos4_busfreq_pm_ops,
-	},
-};
-
-static int __init exynos4_busfreq_init(void)
-{
-	return platform_driver_register(&exynos4_busfreq_driver);
-}
-late_initcall(exynos4_busfreq_init);
-
-static void __exit exynos4_busfreq_exit(void)
-{
-	platform_driver_unregister(&exynos4_busfreq_driver);
-}
-module_exit(exynos4_busfreq_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
-MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>");
diff --git a/drivers/devfreq/exynos/exynos4_bus.h b/drivers/devfreq/exynos/exynos4_bus.h
deleted file mode 100644
index 94c73c18d28c..000000000000
--- a/drivers/devfreq/exynos/exynos4_bus.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com/
- *
- * EXYNOS4 BUS header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __DEVFREQ_EXYNOS4_BUS_H
-#define __DEVFREQ_EXYNOS4_BUS_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_CLKDIV_LEFTBUS			(S5P_VA_CMU + 0x04500)
-#define EXYNOS4_CLKDIV_STAT_LEFTBUS		(S5P_VA_CMU + 0x04600)
-
-#define EXYNOS4_CLKDIV_RIGHTBUS			(S5P_VA_CMU + 0x08500)
-#define EXYNOS4_CLKDIV_STAT_RIGHTBUS		(S5P_VA_CMU + 0x08600)
-
-#define EXYNOS4_CLKDIV_TOP			(S5P_VA_CMU + 0x0C510)
-#define EXYNOS4_CLKDIV_CAM			(S5P_VA_CMU + 0x0C520)
-#define EXYNOS4_CLKDIV_MFC			(S5P_VA_CMU + 0x0C528)
-
-#define EXYNOS4_CLKDIV_STAT_TOP			(S5P_VA_CMU + 0x0C610)
-#define EXYNOS4_CLKDIV_STAT_MFC			(S5P_VA_CMU + 0x0C628)
-
-#define EXYNOS4210_CLKGATE_IP_IMAGE		(S5P_VA_CMU + 0x0C930)
-#define EXYNOS4212_CLKGATE_IP_IMAGE		(S5P_VA_CMU + 0x04930)
-
-#define EXYNOS4_CLKDIV_DMC0			(S5P_VA_CMU + 0x10500)
-#define EXYNOS4_CLKDIV_DMC1			(S5P_VA_CMU + 0x10504)
-#define EXYNOS4_CLKDIV_STAT_DMC0		(S5P_VA_CMU + 0x10600)
-#define EXYNOS4_CLKDIV_STAT_DMC1		(S5P_VA_CMU + 0x10604)
-
-#define EXYNOS4_DMC_PAUSE_CTRL			(S5P_VA_CMU + 0x11094)
-#define EXYNOS4_DMC_PAUSE_ENABLE		(1 << 0)
-
-#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT		(0)
-#define EXYNOS4_CLKDIV_DMC0_ACP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)
-#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT		(8)
-#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT		(12)
-#define EXYNOS4_CLKDIV_DMC0_DMC_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT		(16)
-#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT		(20)
-#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT		(24)
-#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
-#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT	(28)
-#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT	(0)
-#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK	(0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT		(4)
-#define EXYNOS4_CLKDIV_DMC1_C2C_MASK		(0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT		(8)
-#define EXYNOS4_CLKDIV_DMC1_PWI_MASK		(0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT	(12)
-#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT		(16)
-#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK		(0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
-#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT		(24)
-#define EXYNOS4_CLKDIV_DMC1_DPM_MASK		(0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
-
-#define EXYNOS4_CLKDIV_MFC_SHIFT		(0)
-#define EXYNOS4_CLKDIV_MFC_MASK			(0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
-
-#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT	(0)
-#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT	(4)
-#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK		(0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT	(8)
-#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT	(12)
-#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT	(16)
-#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT	(20)
-#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
-#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT	(24)
-#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
-
-#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT		(0)
-#define EXYNOS4_CLKDIV_BUS_GDLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
-#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT		(4)
-#define EXYNOS4_CLKDIV_BUS_GPLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
-
-#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT		(0)
-#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT		(4)
-#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT		(8)
-#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
-#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT		(12)
-#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
-
-#define EXYNOS4_CLKDIV_CAM1			(S5P_VA_CMU + 0x0C568)
-
-#define EXYNOS4_CLKDIV_STAT_CAM1		(S5P_VA_CMU + 0x0C668)
-
-#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT		(0)
-#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK		(0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
-
-#endif /* __DEVFREQ_EXYNOS4_BUS_H */
diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c
deleted file mode 100644
index 297ea30d4159..000000000000
--- a/drivers/devfreq/exynos/exynos5_bus.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com/
- *
- * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework
- * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com>
- * Support for only EXYNOS5250 is present.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/devfreq.h>
-#include <linux/io.h>
-#include <linux/pm_opp.h>
-#include <linux/slab.h>
-#include <linux/suspend.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/pm_qos.h>
-#include <linux/regulator/consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-
-#include "exynos_ppmu.h"
-
-#define MAX_SAFEVOLT			1100000 /* 1.10V */
-/* Assume that the bus is saturated if the utilization is 25% */
-#define INT_BUS_SATURATION_RATIO	25
-
-enum int_level_idx {
-	LV_0,
-	LV_1,
-	LV_2,
-	LV_3,
-	LV_4,
-	_LV_END
-};
-
-enum exynos_ppmu_list {
-	PPMU_RIGHT,
-	PPMU_END,
-};
-
-struct busfreq_data_int {
-	struct device *dev;
-	struct devfreq *devfreq;
-	struct regulator *vdd_int;
-	struct busfreq_ppmu_data ppmu_data;
-	unsigned long curr_freq;
-	bool disabled;
-
-	struct notifier_block pm_notifier;
-	struct mutex lock;
-	struct pm_qos_request int_req;
-	struct clk *int_clk;
-};
-
-struct int_bus_opp_table {
-	unsigned int idx;
-	unsigned long clk;
-	unsigned long volt;
-};
-
-static struct int_bus_opp_table exynos5_int_opp_table[] = {
-	{LV_0, 266000, 1025000},
-	{LV_1, 200000, 1025000},
-	{LV_2, 160000, 1025000},
-	{LV_3, 133000, 1025000},
-	{LV_4, 100000, 1025000},
-	{0, 0, 0},
-};
-
-static int exynos5_int_setvolt(struct busfreq_data_int *data,
-				unsigned long volt)
-{
-	return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT);
-}
-
-static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq,
-			      u32 flags)
-{
-	int err = 0;
-	struct platform_device *pdev = container_of(dev, struct platform_device,
-						    dev);
-	struct busfreq_data_int *data = platform_get_drvdata(pdev);
-	struct dev_pm_opp *opp;
-	unsigned long old_freq, freq;
-	unsigned long volt;
-
-	rcu_read_lock();
-	opp = devfreq_recommended_opp(dev, _freq, flags);
-	if (IS_ERR(opp)) {
-		rcu_read_unlock();
-		dev_err(dev, "%s: Invalid OPP.\n", __func__);
-		return PTR_ERR(opp);
-	}
-
-	freq = dev_pm_opp_get_freq(opp);
-	volt = dev_pm_opp_get_voltage(opp);
-	rcu_read_unlock();
-
-	old_freq = data->curr_freq;
-
-	if (old_freq == freq)
-		return 0;
-
-	dev_dbg(dev, "targeting %lukHz %luuV\n", freq, volt);
-
-	mutex_lock(&data->lock);
-
-	if (data->disabled)
-		goto out;
-
-	if (freq > exynos5_int_opp_table[0].clk)
-		pm_qos_update_request(&data->int_req, freq * 16 / 1000);
-	else
-		pm_qos_update_request(&data->int_req, -1);
-
-	if (old_freq < freq)
-		err = exynos5_int_setvolt(data, volt);
-	if (err)
-		goto out;
-
-	err = clk_set_rate(data->int_clk, freq * 1000);
-
-	if (err)
-		goto out;
-
-	if (old_freq > freq)
-		err = exynos5_int_setvolt(data, volt);
-	if (err)
-		goto out;
-
-	data->curr_freq = freq;
-out:
-	mutex_unlock(&data->lock);
-	return err;
-}
-
-static int exynos5_int_get_dev_status(struct device *dev,
-				      struct devfreq_dev_status *stat)
-{
-	struct platform_device *pdev = container_of(dev, struct platform_device,
-						    dev);
-	struct busfreq_data_int *data = platform_get_drvdata(pdev);
-	struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
-	int busier_dmc;
-
-	exynos_read_ppmu(ppmu_data);
-	busier_dmc = exynos_get_busier_ppmu(ppmu_data);
-
-	stat->current_frequency = data->curr_freq;
-
-	/* Number of cycles spent on memory access */
-	stat->busy_time = ppmu_data->ppmu[busier_dmc].count[PPMU_PMNCNT3];
-	stat->busy_time *= 100 / INT_BUS_SATURATION_RATIO;
-	stat->total_time = ppmu_data->ppmu[busier_dmc].ccnt;
-
-	return 0;
-}
-
-static struct devfreq_dev_profile exynos5_devfreq_int_profile = {
-	.initial_freq		= 160000,
-	.polling_ms		= 100,
-	.target			= exynos5_busfreq_int_target,
-	.get_dev_status		= exynos5_int_get_dev_status,
-};
-
-static int exynos5250_init_int_tables(struct busfreq_data_int *data)
-{
-	int i, err = 0;
-
-	for (i = LV_0; i < _LV_END; i++) {
-		err = dev_pm_opp_add(data->dev, exynos5_int_opp_table[i].clk,
-				exynos5_int_opp_table[i].volt);
-		if (err) {
-			dev_err(data->dev, "Cannot add opp entries.\n");
-			return err;
-		}
-	}
-
-	return 0;
-}
-
-static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this,
-		unsigned long event, void *ptr)
-{
-	struct busfreq_data_int *data = container_of(this,
-					struct busfreq_data_int, pm_notifier);
-	struct dev_pm_opp *opp;
-	unsigned long maxfreq = ULONG_MAX;
-	unsigned long freq;
-	unsigned long volt;
-	int err = 0;
-
-	switch (event) {
-	case PM_SUSPEND_PREPARE:
-		/* Set Fastest and Deactivate DVFS */
-		mutex_lock(&data->lock);
-
-		data->disabled = true;
-
-		rcu_read_lock();
-		opp = dev_pm_opp_find_freq_floor(data->dev, &maxfreq);
-		if (IS_ERR(opp)) {
-			rcu_read_unlock();
-			err = PTR_ERR(opp);
-			goto unlock;
-		}
-		freq = dev_pm_opp_get_freq(opp);
-		volt = dev_pm_opp_get_voltage(opp);
-		rcu_read_unlock();
-
-		err = exynos5_int_setvolt(data, volt);
-		if (err)
-			goto unlock;
-
-		err = clk_set_rate(data->int_clk, freq * 1000);
-
-		if (err)
-			goto unlock;
-
-		data->curr_freq = freq;
-unlock:
-		mutex_unlock(&data->lock);
-		if (err)
-			return NOTIFY_BAD;
-		return NOTIFY_OK;
-	case PM_POST_RESTORE:
-	case PM_POST_SUSPEND:
-		/* Reactivate */
-		mutex_lock(&data->lock);
-		data->disabled = false;
-		mutex_unlock(&data->lock);
-		return NOTIFY_OK;
-	}
-
-	return NOTIFY_DONE;
-}
-
-static int exynos5_busfreq_int_probe(struct platform_device *pdev)
-{
-	struct busfreq_data_int *data;
-	struct busfreq_ppmu_data *ppmu_data;
-	struct dev_pm_opp *opp;
-	struct device *dev = &pdev->dev;
-	struct device_node *np;
-	unsigned long initial_freq;
-	unsigned long initial_volt;
-	int err = 0;
-	int i;
-
-	data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int),
-				GFP_KERNEL);
-	if (data == NULL) {
-		dev_err(dev, "Cannot allocate memory.\n");
-		return -ENOMEM;
-	}
-
-	ppmu_data = &data->ppmu_data;
-	ppmu_data->ppmu_end = PPMU_END;
-	ppmu_data->ppmu = devm_kzalloc(dev,
-				       sizeof(struct exynos_ppmu) * PPMU_END,
-				       GFP_KERNEL);
-	if (!ppmu_data->ppmu) {
-		dev_err(dev, "Failed to allocate memory for exynos_ppmu\n");
-		return -ENOMEM;
-	}
-
-	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-ppmu");
-	if (np == NULL) {
-		pr_err("Unable to find PPMU node\n");
-		return -ENOENT;
-	}
-
-	for (i = 0; i < ppmu_data->ppmu_end; i++) {
-		/* map PPMU memory region */
-		ppmu_data->ppmu[i].hw_base = of_iomap(np, i);
-		if (ppmu_data->ppmu[i].hw_base == NULL) {
-			dev_err(&pdev->dev, "failed to map memory region\n");
-			return -ENOMEM;
-		}
-	}
-	data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event;
-	data->dev = dev;
-	mutex_init(&data->lock);
-
-	err = exynos5250_init_int_tables(data);
-	if (err)
-		return err;
-
-	data->vdd_int = devm_regulator_get(dev, "vdd_int");
-	if (IS_ERR(data->vdd_int)) {
-		dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
-		return PTR_ERR(data->vdd_int);
-	}
-
-	data->int_clk = devm_clk_get(dev, "int_clk");
-	if (IS_ERR(data->int_clk)) {
-		dev_err(dev, "Cannot get clock \"int_clk\"\n");
-		return PTR_ERR(data->int_clk);
-	}
-
-	rcu_read_lock();
-	opp = dev_pm_opp_find_freq_floor(dev,
-			&exynos5_devfreq_int_profile.initial_freq);
-	if (IS_ERR(opp)) {
-		rcu_read_unlock();
-		dev_err(dev, "Invalid initial frequency %lu kHz.\n",
-		       exynos5_devfreq_int_profile.initial_freq);
-		return PTR_ERR(opp);
-	}
-	initial_freq = dev_pm_opp_get_freq(opp);
-	initial_volt = dev_pm_opp_get_voltage(opp);
-	rcu_read_unlock();
-	data->curr_freq = initial_freq;
-
-	err = clk_set_rate(data->int_clk, initial_freq * 1000);
-	if (err) {
-		dev_err(dev, "Failed to set initial frequency\n");
-		return err;
-	}
-
-	err = exynos5_int_setvolt(data, initial_volt);
-	if (err)
-		return err;
-
-	platform_set_drvdata(pdev, data);
-
-	busfreq_mon_reset(ppmu_data);
-
-	data->devfreq = devm_devfreq_add_device(dev, &exynos5_devfreq_int_profile,
-					   "simple_ondemand", NULL);
-	if (IS_ERR(data->devfreq))
-		return PTR_ERR(data->devfreq);
-
-	err = devm_devfreq_register_opp_notifier(dev, data->devfreq);
-	if (err < 0) {
-		dev_err(dev, "Failed to register opp notifier\n");
-		return err;
-	}
-
-	err = register_pm_notifier(&data->pm_notifier);
-	if (err) {
-		dev_err(dev, "Failed to setup pm notifier\n");
-		return err;
-	}
-
-	/* TODO: Add a new QOS class for int/mif bus */
-	pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1);
-
-	return 0;
-}
-
-static int exynos5_busfreq_int_remove(struct platform_device *pdev)
-{
-	struct busfreq_data_int *data = platform_get_drvdata(pdev);
-
-	pm_qos_remove_request(&data->int_req);
-	unregister_pm_notifier(&data->pm_notifier);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos5_busfreq_int_resume(struct device *dev)
-{
-	struct platform_device *pdev = container_of(dev, struct platform_device,
-						    dev);
-	struct busfreq_data_int *data = platform_get_drvdata(pdev);
-	struct busfreq_ppmu_data *ppmu_data = &data->ppmu_data;
-
-	busfreq_mon_reset(ppmu_data);
-	return 0;
-}
-static const struct dev_pm_ops exynos5_busfreq_int_pm = {
-	.resume	= exynos5_busfreq_int_resume,
-};
-#endif
-static SIMPLE_DEV_PM_OPS(exynos5_busfreq_int_pm_ops, NULL,
-			 exynos5_busfreq_int_resume);
-
-/* platform device pointer for exynos5 devfreq device. */
-static struct platform_device *exynos5_devfreq_pdev;
-
-static struct platform_driver exynos5_busfreq_int_driver = {
-	.probe		= exynos5_busfreq_int_probe,
-	.remove		= exynos5_busfreq_int_remove,
-	.driver		= {
-		.name		= "exynos5-bus-int",
-		.pm		= &exynos5_busfreq_int_pm_ops,
-	},
-};
-
-static int __init exynos5_busfreq_int_init(void)
-{
-	int ret;
-
-	ret = platform_driver_register(&exynos5_busfreq_int_driver);
-	if (ret < 0)
-		goto out;
-
-	exynos5_devfreq_pdev =
-		platform_device_register_simple("exynos5-bus-int", -1, NULL, 0);
-	if (IS_ERR(exynos5_devfreq_pdev)) {
-		ret = PTR_ERR(exynos5_devfreq_pdev);
-		goto out1;
-	}
-
-	return 0;
-out1:
-	platform_driver_unregister(&exynos5_busfreq_int_driver);
-out:
-	return ret;
-}
-late_initcall(exynos5_busfreq_int_init);
-
-static void __exit exynos5_busfreq_int_exit(void)
-{
-	platform_device_unregister(exynos5_devfreq_pdev);
-	platform_driver_unregister(&exynos5_busfreq_int_driver);
-}
-module_exit(exynos5_busfreq_int_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework");
diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c
deleted file mode 100644
index 97b75e513d29..000000000000
--- a/drivers/devfreq/exynos/exynos_ppmu.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com/
- *
- * EXYNOS - PPMU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include "exynos_ppmu.h"
-
-void exynos_ppmu_reset(void __iomem *ppmu_base)
-{
-	__raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base);
-	__raw_writel(PPMU_ENABLE_CYCLE  |
-		     PPMU_ENABLE_COUNT0 |
-		     PPMU_ENABLE_COUNT1 |
-		     PPMU_ENABLE_COUNT2 |
-		     PPMU_ENABLE_COUNT3,
-		     ppmu_base + PPMU_CNTENS);
-}
-
-void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch,
-			unsigned int evt)
-{
-	__raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch));
-}
-
-void exynos_ppmu_start(void __iomem *ppmu_base)
-{
-	__raw_writel(PPMU_ENABLE, ppmu_base);
-}
-
-void exynos_ppmu_stop(void __iomem *ppmu_base)
-{
-	__raw_writel(PPMU_DISABLE, ppmu_base);
-}
-
-unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch)
-{
-	unsigned int total;
-
-	if (ch == PPMU_PMNCNT3)
-		total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) |
-			  __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1)));
-	else
-		total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch));
-
-	return total;
-}
-
-void busfreq_mon_reset(struct busfreq_ppmu_data *ppmu_data)
-{
-	unsigned int i;
-
-	for (i = 0; i < ppmu_data->ppmu_end; i++) {
-		void __iomem *ppmu_base = ppmu_data->ppmu[i].hw_base;
-
-		/* Reset the performance and cycle counters */
-		exynos_ppmu_reset(ppmu_base);
-
-		/* Setup count registers to monitor read/write transactions */
-		ppmu_data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT;
-		exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3,
-					ppmu_data->ppmu[i].event[PPMU_PMNCNT3]);
-
-		exynos_ppmu_start(ppmu_base);
-	}
-}
-EXPORT_SYMBOL(busfreq_mon_reset);
-
-void exynos_read_ppmu(struct busfreq_ppmu_data *ppmu_data)
-{
-	int i, j;
-
-	for (i = 0; i < ppmu_data->ppmu_end; i++) {
-		void __iomem *ppmu_base = ppmu_data->ppmu[i].hw_base;
-
-		exynos_ppmu_stop(ppmu_base);
-
-		/* Update local data from PPMU */
-		ppmu_data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT);
-
-		for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
-			if (ppmu_data->ppmu[i].event[j] == 0)
-				ppmu_data->ppmu[i].count[j] = 0;
-			else
-				ppmu_data->ppmu[i].count[j] =
-					exynos_ppmu_read(ppmu_base, j);
-		}
-	}
-
-	busfreq_mon_reset(ppmu_data);
-}
-EXPORT_SYMBOL(exynos_read_ppmu);
-
-int exynos_get_busier_ppmu(struct busfreq_ppmu_data *ppmu_data)
-{
-	unsigned int count = 0;
-	int i, j, busy = 0;
-
-	for (i = 0; i < ppmu_data->ppmu_end; i++) {
-		for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) {
-			if (ppmu_data->ppmu[i].count[j] > count) {
-				count = ppmu_data->ppmu[i].count[j];
-				busy = i;
-			}
-		}
-	}
-
-	return busy;
-}
-EXPORT_SYMBOL(exynos_get_busier_ppmu);
diff --git a/drivers/devfreq/exynos/exynos_ppmu.h b/drivers/devfreq/exynos/exynos_ppmu.h
deleted file mode 100644
index 71f17ba3563c..000000000000
--- a/drivers/devfreq/exynos/exynos_ppmu.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com/
- *
- * EXYNOS PPMU header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __DEVFREQ_EXYNOS_PPMU_H
-#define __DEVFREQ_EXYNOS_PPMU_H __FILE__
-
-#include <linux/ktime.h>
-
-/* For PPMU Control */
-#define PPMU_ENABLE             BIT(0)
-#define PPMU_DISABLE            0x0
-#define PPMU_CYCLE_RESET        BIT(1)
-#define PPMU_COUNTER_RESET      BIT(2)
-
-#define PPMU_ENABLE_COUNT0      BIT(0)
-#define PPMU_ENABLE_COUNT1      BIT(1)
-#define PPMU_ENABLE_COUNT2      BIT(2)
-#define PPMU_ENABLE_COUNT3      BIT(3)
-#define PPMU_ENABLE_CYCLE       BIT(31)
-
-#define PPMU_CNTENS		0x10
-#define PPMU_FLAG		0x50
-#define PPMU_CCNT_OVERFLOW	BIT(31)
-#define PPMU_CCNT		0x100
-
-#define PPMU_PMCNT0		0x110
-#define PPMU_PMCNT_OFFSET	0x10
-#define PMCNT_OFFSET(x)		(PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x))
-
-#define PPMU_BEVT0SEL		0x1000
-#define PPMU_BEVTSEL_OFFSET	0x100
-#define PPMU_BEVTSEL(x)		(PPMU_BEVT0SEL + (ch * PPMU_BEVTSEL_OFFSET))
-
-/* For Event Selection */
-#define RD_DATA_COUNT		0x5
-#define WR_DATA_COUNT		0x6
-#define RDWR_DATA_COUNT		0x7
-
-enum ppmu_counter {
-	PPMU_PMNCNT0,
-	PPMU_PMCCNT1,
-	PPMU_PMNCNT2,
-	PPMU_PMNCNT3,
-	PPMU_PMNCNT_MAX,
-};
-
-struct bus_opp_table {
-	unsigned int idx;
-	unsigned long clk;
-	unsigned long volt;
-};
-
-struct exynos_ppmu {
-	void __iomem *hw_base;
-	unsigned int ccnt;
-	unsigned int event[PPMU_PMNCNT_MAX];
-	unsigned int count[PPMU_PMNCNT_MAX];
-	unsigned long long ns;
-	ktime_t reset_time;
-	bool ccnt_overflow;
-	bool count_overflow[PPMU_PMNCNT_MAX];
-};
-
-struct busfreq_ppmu_data {
-	struct exynos_ppmu *ppmu;
-	int ppmu_end;
-};
-
-void exynos_ppmu_reset(void __iomem *ppmu_base);
-void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch,
-			unsigned int evt);
-void exynos_ppmu_start(void __iomem *ppmu_base);
-void exynos_ppmu_stop(void __iomem *ppmu_base);
-unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch);
-void busfreq_mon_reset(struct busfreq_ppmu_data *ppmu_data);
-void exynos_read_ppmu(struct busfreq_ppmu_data *ppmu_data);
-int exynos_get_busier_ppmu(struct busfreq_ppmu_data *ppmu_data);
-#endif /* __DEVFREQ_EXYNOS_PPMU_H */
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (10 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 11/19] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  2:09   ` Krzysztof Kozlowski
  2015-12-09  4:08 ` [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi
                   ` (8 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
Exynos3250 has following AXI buses to translate data between
DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK400 clock for MCUISP
- ACLK266 clock for ISP
- ACLK200 clock for FSYS
- ACLK160 clock for LCD0
- ACLK100 clock for PERIL
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 160 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 7214c5e42150..46dee1951ec1 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -721,6 +721,166 @@
 				opp-microvolt = <875000>;
 			};
 		};
+
+		bus_leftbus: bus_leftbus {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_GDL>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_rightbus: bus_rightbus {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_GDR>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_lcd0: bus_lcd0 {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_160>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_fsys: bus_fsys {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_200>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_mcuisp: bus_mcuisp {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_mcuisp_opp_table>;
+			status = "disabled";
+		};
+
+		bus_isp: bus_isp {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_266>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_isp_opp_table>;
+			status = "disabled";
+		};
+
+		bus_peril: bus_peril {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_100>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_peril_opp_table>;
+			status = "disabled";
+		};
+
+		bus_mfc: bus_mfc {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_SCLK_MFC>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_leftbus_opp_table: opp_table2 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp00 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <900000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <80000000>;
+				opp-microvolt = <900000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp03 {
+				opp-hz = /bits/ 64 <134000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp04 {
+				opp-hz = /bits/ 64 <200000000>;
+				opp-microvolt = <1000000>;
+			};
+		};
+
+		bus_mcuisp_opp_table: opp_table3 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp00 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <900000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <80000000>;
+				opp-microvolt = <900000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp03 {
+				opp-hz = /bits/ 64 <200000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp04 {
+				opp-hz = /bits/ 64 <400000000>;
+				opp-microvolt = <1000000>;
+			};
+		};
+
+		bus_isp_opp_table: opp_table4 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp00 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <900000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <80000000>;
+				opp-microvolt = <900000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp03 {
+				opp-hz = /bits/ 64 <200000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp04 {
+				opp-hz = /bits/ 64 <300000000>;
+				opp-microvolt = <1000000>;
+			};
+		};
+
+		bus_peril_opp_table: opp_table5 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp00 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <900000>;
+			};
+			opp01 {
+				opp-hz = /bits/ 64 <80000000>;
+				opp-microvolt = <900000>;
+			};
+			opp02 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <1000000>;
+			};
+		};
 	};
 };
 
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (11 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  3:17   ` Krzysztof Kozlowski
  2015-12-09  4:08 ` [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT " Chanwoo Choi
                   ` (7 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index b77dac61ffb5..3bcf0939755e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -282,6 +282,78 @@
 		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
 		#iommu-cells = <0>;
 	};
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_acp: bus_acp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_ACP>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_acp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_c2c: bus_c2c {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_C2C>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <900000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <950000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	bus_acp_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <900000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <950000>;
+		};
+	};
 };
 
 &combiner {
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (12 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  5:57   ` Krzysztof Kozlowski
  2015-12-09  4:08 ` [PATCH v2 15/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Chanwoo Choi
                   ` (6 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data between
DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD
: The minimum clock of ACLK160 should be over 160MHz.
  When drop the clock under 160MHz, show the broken image.
- ACLK133 clock for FSYS
- GDL clock for LEFTBUS
- GDR clock for RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 3bcf0939755e..8bc4aee156b5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -354,6 +354,118 @@
 			opp-microvolt = <950000>;
 		};
 	};
+
+	bus_leftbus: bus_leftbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_rightbus: bus_rightbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDR>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_display: bus_display {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK160>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_display_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys: bus_fsys {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK133>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys_opp_table>;
+		status = "disabled";
+	};
+
+	bus_peri: bus_peri {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK100>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_peri_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mfc: bus_mfc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_SCLK_MFC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_leftbus_opp_table: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <925000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <950000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+	bus_display_opp_table: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <950000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+	bus_fsys_opp_table: opp_table5 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <925000>;
+		};
+	};
+
+	bus_peri_opp_table: opp_table6 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <50000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <925000>;
+		};
+	};
 };
 
 &combiner {
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 15/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (13 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT " Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-09  4:08 ` [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3 Chanwoo Choi
                   ` (5 subsequent siblings)
  20 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
one power line for all buses to translate data between DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- DMC/ACP clock for DMC (Dynamic Memory Controller)
- ACLK200 clock for LCD0
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD0/LCD1
- ACLK133 clock for FSYS/GPS
- GDL/GDR clock for LEFTBUS/RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4210.dtsi | 172 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 172 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 3e5ba665d200..658c5a1fe03c 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,178 @@
 		power-domains = <&pd_lcd1>;
 		#iommu-cells = <0>;
 	};
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_acp: bus_acp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_ACP>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_acp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_peri: bus_peri {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK100>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_peri_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys: bus_fsys {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK133>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys_opp_table>;
+		status = "disabled";
+	};
+
+	bus_display: bus_display {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK160>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_display_opp_table>;
+		status = "disabled";
+	};
+
+	bus_lcd0: bus_lcd0 {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK200>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_leftbus: bus_leftbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_rightbus: bus_rightbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDR>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mfc: bus_mfc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_SCLK_MFC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <267000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1150000>;
+		};
+	};
+
+	bus_acp_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1150000>;
+		};
+	};
+
+	bus_peri_opp_table: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <5000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	bus_fsys_opp_table: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <10000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	bus_display_opp_table: opp_table5 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <1150000>;
+		};
+	};
+
+	bus_leftbus_opp_table: opp_table6 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1150000>;
+		};
+	};
 };
 
 &gic {
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (14 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 15/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  6:44   ` Krzysztof Kozlowski
  2015-12-09  4:08 ` [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato Chanwoo Choi
                   ` (4 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
exynos4412-odroidu3 board. Each PPMU dt node includes one event of
'PPMU Count3'.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40 +++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index edf0fc8db6ff..90800a6da14b 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -504,3 +504,43 @@
 &watchdog {
 	status = "okay";
 };
+
+&ppmu_dmc0 {
+	status = "okay";
+
+	events {
+		ppmu_dmc0_3: ppmu-event3-dmc0 {
+			event-name = "ppmu-event3-dmc0";
+		};
+	};
+};
+
+&ppmu_dmc1 {
+	status = "okay";
+
+	events {
+		ppmu_dmc1_3: ppmu-event3-dmc1 {
+			event-name = "ppmu-event3-dmc1";
+		};
+	};
+};
+
+&ppmu_leftbus {
+	status = "okay";
+
+	events {
+		ppmu_leftbus_3: ppmu-event3-leftbus {
+			event-name = "ppmu-event3-leftbus";
+		};
+	};
+};
+
+&ppmu_rightbus {
+	status = "okay";
+
+	events {
+		ppmu_rightbus_3: ppmu-event3-rightbus {
+			event-name = "ppmu-event3-rightbus";
+		};
+	};
+};
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (15 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3 Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  6:58   ` Krzysztof Kozlowski
  2015-12-09  4:08 ` [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 Chanwoo Choi
                   ` (3 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch adds the bus device-tree node of INT (internal) block
to enable the bus frequency. The following sub-blocks share
the VDD_INT power source:
- LEFTBUS (parent device)
- RIGHTBUS
- PERIL
- LCD0
- FSYS
- MCUISP / ISP
- MFC

The LEFTBUS is parent device with devfreq ondemand governor
and the rest devices has the dependency on LEFTBUS bus.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos3250-rinato.dts | 41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 61477943015b..3a6ca68b68c3 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -681,6 +681,47 @@
 	status = "okay";
 };
 
+&bus_leftbus {
+	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+	vdd-supply = <&buck3_reg>;
+	status = "okay";
+};
+
+&bus_rightbus {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_lcd0 {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mcuisp {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_isp {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_peril {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
 &xusbxti {
 	clock-frequency = <24000000>;
 };
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (16 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  7:02     ` Krzysztof Kozlowski
  2015-12-09  4:08 ` [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3 Chanwoo Choi
                   ` (2 subsequent siblings)
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

This patch expands the voltage range of buck1/3 regulator due to as following:
- MIF (Memory Interface) bus frequency needs the 90000uV ~ 1050000uV V.
- INT (Internal) bus frequency needs 90000uV ~ 1000000uV.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 90800a6da14b..171dea1e3e4a 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -359,8 +359,8 @@
 
 			buck1_reg: BUCK1 {
 				regulator-name = "vdd_mif";
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1050000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
@@ -375,7 +375,7 @@
 
 			buck3_reg: BUCK3 {
 				regulator-name = "vdd_int";
-				regulator-min-microvolt = <1000000>;
+				regulator-min-microvolt = <900000>;
 				regulator-max-microvolt = <1000000>;
 				regulator-always-on;
 				regulator-boot-on;
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (17 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 Chanwoo Choi
@ 2015-12-09  4:08 ` Chanwoo Choi
  2015-12-10  7:08   ` Krzysztof Kozlowski
  2015-12-09 19:05 ` [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Anand Moon
  2015-12-10  0:57 ` Krzysztof Kozlowski
  20 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-09  4:08 UTC (permalink / raw)
  To: myungjoo.ham, k.kozlowski, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, cw00.choi, linux-kernel,
	linux-pm, linux-samsung-soc, devicetree

THis patch adds the bus device tree nodes for both MIF (Memory) and INT
(Internal) block to enable the bus frequency.

The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
bus is parent device in INT block using VDD_INT.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47 +++++++++++++++++++++++++
 arch/arm/boot/dts/exynos4412-trats2.dts         | 47 +++++++++++++++++++++++++
 2 files changed, 94 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 171dea1e3e4a..12d08242a179 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -544,3 +544,50 @@
 		};
 	};
 };
+
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
+&bus_acp {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_c2c {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_leftbus {
+	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+	vdd-supply = <&buck3_reg>;
+	status = "okay";
+};
+
+&bus_rightbus {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_display {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_peri {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 40a474c4374b..aecd545803ad 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -1286,3 +1286,50 @@
 	vtmu-supply = <&ldo10_reg>;
 	status = "okay";
 };
+
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
+&bus_acp {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_c2c {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_leftbus {
+	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+	vdd-supply = <&buck3_reg>;
+	status = "okay";
+};
+
+&bus_rightbus {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_display {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_peri {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (18 preceding siblings ...)
  2015-12-09  4:08 ` [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3 Chanwoo Choi
@ 2015-12-09 19:05 ` Anand Moon
  2015-12-10  0:12   ` Chanwoo Choi
  2015-12-10  0:57 ` Krzysztof Kozlowski
  20 siblings, 1 reply; 72+ messages in thread
From: Anand Moon @ 2015-12-09 19:05 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King, Tobias Jakobi,
	Linux Kernel, Linux PM list, linux-samsung-soc, devicetree

Hi Chanwoo Choi,

On 9 December 2015 at 09:37, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch-set includes the two features as following. The generic exynos bus
> frequency driver is able to support almost Exynos SoCs for bus frequency
> scaling. And the new passive governor is able to make the dependency on
> between devices for frequency/voltage scaling. I had posted the patch-set[1]
> with the similiar concept. This is is revised version for exynos bus frequency.
> - Generic exynos bus frequency driver
> - New passive governor of DEVFREQ framework
>
> Depends on:
> - This patch-set is based on devfreq.git[2].
> [1] https://lkml.org/lkml/2015/1/7/872
>    : [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch: for-rafael)
>
> Changes from v1:
> (https://lkml.org/lkml/2015/11/26/260)
> - Check whether the instance of regulator is NULL or not
>   when executing regulator_disable() because of only parent
>   devfreq device has the regulator instance. After fixing it,
>   the wake-up from suspend state is well working. (patch1)
> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>   after calling devm_clk_get() (on patch1)
> - Update the documentation to remove the description about
>   DEVFREQ-EVENT subsystem (on patch2)
> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
> - Modify the detailed correlation of buses for Exynos3250
>   on documentation (patch2)
> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
> - Add the PPMU node for exynos4412-odroidu3
> - Add the support of bus frequency for exynos4412-odroidu3
>
> Detailed descirption for patch-set:
> 1. Add generic exynos bus frequency driver
> : This patch-set adds the generic exynos bus frequency driver for AXI bus
> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
> architecture for bus between DRAM and sub-blocks in SoC.
>
>  There are the different buses according to Exynos SoC because Exynos SoC
> has the differnt sub-blocks and bus speed. In spite of this difference
> among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
> unique data of each bus in the devicetree file.
>
>  In devicetree, each bus node has a bus clock, regulator, operation-point
> and devfreq-event devices which measure the utilization of each bus block.
>
> For example,
> - The bus of DMC block in exynos3250.dtsi are listed below:
>
>         bus_dmc: bus_dmc {
>                 compatible = "samsung,exynos-bus";
>                 clocks = <&cmu_dmc CLK_DIV_DMC>;
>                 clock-names = "bus";
>                 operating-points-v2 = <&bus_dmc_opp_table>;
>                 status = "disabled";
>         };
>
>         bus_dmc_opp_table: opp_table0 {
>                 compatible = "operating-points-v2";
>                 opp-shared;
>
>                 opp00 {
>                         opp-hz = /bits/ 64 <50000000>;
>                         opp-microvolt = <800000>;
>                 };
>                 opp01 {
>                         opp-hz = /bits/ 64 <100000000>;
>                         opp-microvolt = <800000>;
>                 };
>                 opp02 {
>                         opp-hz = /bits/ 64 <134000000>;
>                         opp-microvolt = <800000>;
>                 };
>                 opp03 {
>                         opp-hz = /bits/ 64 <200000000>;
>                         opp-microvolt = <800000>;
>                 };
>                 opp04 {
>                         opp-hz = /bits/ 64 <400000000>;
>                         opp-microvolt = <875000>;
>                 };
>         };
>
> - Usage case to handle the frequency and voltage of bus on runtime
>   in exynos3250-rinato.dts are listed below:
>
>         &bus_dmc {
>                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
>                 status = "okay";
>         };
>
> 2. Add new passive governor of DEVFREQ framework (patch5-patch7)
> : This patch-set add the new passive governor for DEVFREQ framework.
> The existing governors (ondemand, performance and so on) are used for DVFS
> (Dynamic Voltage and Frequency Scaling) drivers. The existing governors
> are independently used for specific device driver which don't give the
> influence to other device drviers and also don't receive the effect from
> other device drivers.
>
>  The passive governor depends on operation of parent driver with existing
> governors(ondemand, performance and so on) extremely and is not able to
> decide the new frequency by oneself. According to the decided new frequency
> of parent driver with governor, the passive governor uses it to decide
> the appropriate frequency for own device driver. The passive governor
> must need the following information from device tree:
>
> For exameple,
>  There are one more bus device drivers in Exynos3250 which need to
> change their source clock according to their utilization on runtime.
> But, they share the same power line (e.g., regulator). So, LEFTBUS bus
> driver is operated as parent with ondemand governor and then the rest
> device driver with passive governor.
>
>  The buses of Internal block in exynos3250.dtsi are listed below:
> When LEFTBUS bus driver (parent) changes the bus frequency with
> ondemand governor on runtime, the rest bus devices which sharing
> the same power line (VDD_INT) will change the each bus frequency
> according to the decision of LEFTBUS bus driver (parent).
>
> - INT (Internal) block
>         : VDD_INT |--- LEFTBUS
>                   |--- PERIL
>                   |--- MFC
>                   |--- G3D
>                   |--- RIGHTBUS
>                   |--- FSYS
>                   |--- LCD0
>                   |--- PERIR
>                   |--- ISP
>                   |--- CAM
>
> - The buss of INT block in exynos3250.dtsi are listed below:
>         bus_leftbus: bus_leftbus {
>                 compatible = "samsung,exynos-bus";
>                 clocks = <&cmu CLK_DIV_GDL>;
>                 clock-names = "bus";
>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>                 status = "disabled";
>         };
>
>         bus_rightbus: bus_rightbus {
>                 compatible = "samsung,exynos-bus";
>                 clocks = <&cmu CLK_DIV_GDR>;
>                 clock-names = "bus";
>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>                 status = "disabled";
>         };
>
>         (Omit the rest bus dt node)
>
> - Usage case to handle the frequency and voltage of bus on runtime
>   in exynos3250-rinato.dts are listed below:
>         /* Parent bus device of VDD_INT */
>         &bus_leftbus {
>                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>                 vdd-supply = <&buck3_reg>;
>                 status = "okay";
>         };
>
>         /* Passive bus device depend on LEFTBUS bus. */
>         &bus_rightbus {
>                 devfreq = <&bus_leftbus>; /* 'devfreq' property indicates
>                                              the phandle of parent device. */
>                 status = "okay";
>         };
>
>         (Omit the rest bus dt node)
>
> Chanwoo Choi (19):
>   PM / devfreq: exynos: Add generic exynos bus frequency driver
>   PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
>   ARM: dts: Add DMC bus node for Exynos3250
>   ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
>   PM / devfreq: Add new passive governor
>   PM / devfreq: Add devfreq_get_devfreq_by_phandle()
>   PM / devfreq: Show the related information according to governor type
>   PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
>   PM / devfreq: exynos: Update documentation for bus devices using passive governor
>   PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
>   PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
>   ARM: dts: Add bus nodes using VDD_INT for Exynos3250
>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
>   ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
>   ARM: dts: Add PPMU node for exynos4412-odroidu3
>   ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
>   ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
>   ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
>
>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>  drivers/devfreq/Kconfig                            |   37 +-
>  drivers/devfreq/Makefile                           |    2 +
>  drivers/devfreq/devfreq.c                          |  120 ++-
>  drivers/devfreq/exynos/Makefile                    |    3 +-
>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>  drivers/devfreq/governor.h                         |    7 +
>  drivers/devfreq/governor_passive.c                 |  109 ++
>  drivers/devfreq/governor_performance.c             |    1 +
>  drivers/devfreq/governor_powersave.c               |    1 +
>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>  drivers/devfreq/governor_userspace.c               |    1 +
>  include/linux/devfreq.h                            |   28 +
>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>  create mode 100644 drivers/devfreq/governor_passive.c
>
> --
> 1.9.1
>

I could not get this series to work with my Odroid U3.

[    4.602768] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    4.605527] devfreq bus_leftbus: Couldn't update frequency
transition information.
[    4.607319] devfreq bus_dmc: Couldn't update frequency transition
information.
[    4.625096] usb 1-3: New USB device found, idVendor=0424, idProduct=3503

-Anand Moon

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
  2015-12-09 19:05 ` [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Anand Moon
@ 2015-12-10  0:12   ` Chanwoo Choi
  2015-12-10  4:14       ` Anand Moon
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  0:12 UTC (permalink / raw)
  To: Anand Moon
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King, Tobias Jakobi,
	Linux Kernel, Linux PM list, linux-samsung-soc, devicetree

Hi Anand,

First of all, thanks for trying to test this series.

On 2015년 12월 10일 04:05, Anand Moon wrote:
> Hi Chanwoo Choi,
> 
> On 9 December 2015 at 09:37, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch-set includes the two features as following. The generic exynos bus
>> frequency driver is able to support almost Exynos SoCs for bus frequency
>> scaling. And the new passive governor is able to make the dependency on
>> between devices for frequency/voltage scaling. I had posted the patch-set[1]
>> with the similiar concept. This is is revised version for exynos bus frequency.
>> - Generic exynos bus frequency driver
>> - New passive governor of DEVFREQ framework
>>
>> Depends on:
>> - This patch-set is based on devfreq.git[2].
>> [1] https://lkml.org/lkml/2015/1/7/872
>>    : [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
>> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch: for-rafael)
>>
>> Changes from v1:
>> (https://lkml.org/lkml/2015/11/26/260)
>> - Check whether the instance of regulator is NULL or not
>>   when executing regulator_disable() because of only parent
>>   devfreq device has the regulator instance. After fixing it,
>>   the wake-up from suspend state is well working. (patch1)
>> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>>   after calling devm_clk_get() (on patch1)
>> - Update the documentation to remove the description about
>>   DEVFREQ-EVENT subsystem (on patch2)
>> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
>> - Modify the detailed correlation of buses for Exynos3250
>>   on documentation (patch2)
>> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
>> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
>> - Add the PPMU node for exynos4412-odroidu3
>> - Add the support of bus frequency for exynos4412-odroidu3
>>
>> Detailed descirption for patch-set:
>> 1. Add generic exynos bus frequency driver
>> : This patch-set adds the generic exynos bus frequency driver for AXI bus
>> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
>> architecture for bus between DRAM and sub-blocks in SoC.
>>
>>  There are the different buses according to Exynos SoC because Exynos SoC
>> has the differnt sub-blocks and bus speed. In spite of this difference
>> among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
>> unique data of each bus in the devicetree file.
>>
>>  In devicetree, each bus node has a bus clock, regulator, operation-point
>> and devfreq-event devices which measure the utilization of each bus block.
>>
>> For example,
>> - The bus of DMC block in exynos3250.dtsi are listed below:
>>
>>         bus_dmc: bus_dmc {
>>                 compatible = "samsung,exynos-bus";
>>                 clocks = <&cmu_dmc CLK_DIV_DMC>;
>>                 clock-names = "bus";
>>                 operating-points-v2 = <&bus_dmc_opp_table>;
>>                 status = "disabled";
>>         };
>>
>>         bus_dmc_opp_table: opp_table0 {
>>                 compatible = "operating-points-v2";
>>                 opp-shared;
>>
>>                 opp00 {
>>                         opp-hz = /bits/ 64 <50000000>;
>>                         opp-microvolt = <800000>;
>>                 };
>>                 opp01 {
>>                         opp-hz = /bits/ 64 <100000000>;
>>                         opp-microvolt = <800000>;
>>                 };
>>                 opp02 {
>>                         opp-hz = /bits/ 64 <134000000>;
>>                         opp-microvolt = <800000>;
>>                 };
>>                 opp03 {
>>                         opp-hz = /bits/ 64 <200000000>;
>>                         opp-microvolt = <800000>;
>>                 };
>>                 opp04 {
>>                         opp-hz = /bits/ 64 <400000000>;
>>                         opp-microvolt = <875000>;
>>                 };
>>         };
>>
>> - Usage case to handle the frequency and voltage of bus on runtime
>>   in exynos3250-rinato.dts are listed below:
>>
>>         &bus_dmc {
>>                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>>                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
>>                 status = "okay";
>>         };
>>
>> 2. Add new passive governor of DEVFREQ framework (patch5-patch7)
>> : This patch-set add the new passive governor for DEVFREQ framework.
>> The existing governors (ondemand, performance and so on) are used for DVFS
>> (Dynamic Voltage and Frequency Scaling) drivers. The existing governors
>> are independently used for specific device driver which don't give the
>> influence to other device drviers and also don't receive the effect from
>> other device drivers.
>>
>>  The passive governor depends on operation of parent driver with existing
>> governors(ondemand, performance and so on) extremely and is not able to
>> decide the new frequency by oneself. According to the decided new frequency
>> of parent driver with governor, the passive governor uses it to decide
>> the appropriate frequency for own device driver. The passive governor
>> must need the following information from device tree:
>>
>> For exameple,
>>  There are one more bus device drivers in Exynos3250 which need to
>> change their source clock according to their utilization on runtime.
>> But, they share the same power line (e.g., regulator). So, LEFTBUS bus
>> driver is operated as parent with ondemand governor and then the rest
>> device driver with passive governor.
>>
>>  The buses of Internal block in exynos3250.dtsi are listed below:
>> When LEFTBUS bus driver (parent) changes the bus frequency with
>> ondemand governor on runtime, the rest bus devices which sharing
>> the same power line (VDD_INT) will change the each bus frequency
>> according to the decision of LEFTBUS bus driver (parent).
>>
>> - INT (Internal) block
>>         : VDD_INT |--- LEFTBUS
>>                   |--- PERIL
>>                   |--- MFC
>>                   |--- G3D
>>                   |--- RIGHTBUS
>>                   |--- FSYS
>>                   |--- LCD0
>>                   |--- PERIR
>>                   |--- ISP
>>                   |--- CAM
>>
>> - The buss of INT block in exynos3250.dtsi are listed below:
>>         bus_leftbus: bus_leftbus {
>>                 compatible = "samsung,exynos-bus";
>>                 clocks = <&cmu CLK_DIV_GDL>;
>>                 clock-names = "bus";
>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>                 status = "disabled";
>>         };
>>
>>         bus_rightbus: bus_rightbus {
>>                 compatible = "samsung,exynos-bus";
>>                 clocks = <&cmu CLK_DIV_GDR>;
>>                 clock-names = "bus";
>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>                 status = "disabled";
>>         };
>>
>>         (Omit the rest bus dt node)
>>
>> - Usage case to handle the frequency and voltage of bus on runtime
>>   in exynos3250-rinato.dts are listed below:
>>         /* Parent bus device of VDD_INT */
>>         &bus_leftbus {
>>                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>>                 vdd-supply = <&buck3_reg>;
>>                 status = "okay";
>>         };
>>
>>         /* Passive bus device depend on LEFTBUS bus. */
>>         &bus_rightbus {
>>                 devfreq = <&bus_leftbus>; /* 'devfreq' property indicates
>>                                              the phandle of parent device. */
>>                 status = "okay";
>>         };
>>
>>         (Omit the rest bus dt node)
>>
>> Chanwoo Choi (19):
>>   PM / devfreq: exynos: Add generic exynos bus frequency driver
>>   PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
>>   ARM: dts: Add DMC bus node for Exynos3250
>>   ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
>>   PM / devfreq: Add new passive governor
>>   PM / devfreq: Add devfreq_get_devfreq_by_phandle()
>>   PM / devfreq: Show the related information according to governor type
>>   PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
>>   PM / devfreq: exynos: Update documentation for bus devices using passive governor
>>   PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
>>   PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
>>   ARM: dts: Add bus nodes using VDD_INT for Exynos3250
>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
>>   ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
>>   ARM: dts: Add PPMU node for exynos4412-odroidu3
>>   ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
>>   ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
>>   ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
>>
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
>>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>>  drivers/devfreq/Kconfig                            |   37 +-
>>  drivers/devfreq/Makefile                           |    2 +
>>  drivers/devfreq/devfreq.c                          |  120 ++-
>>  drivers/devfreq/exynos/Makefile                    |    3 +-
>>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>>  drivers/devfreq/governor.h                         |    7 +
>>  drivers/devfreq/governor_passive.c                 |  109 ++
>>  drivers/devfreq/governor_performance.c             |    1 +
>>  drivers/devfreq/governor_powersave.c               |    1 +
>>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>>  drivers/devfreq/governor_userspace.c               |    1 +
>>  include/linux/devfreq.h                            |   28 +
>>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>>  create mode 100644 drivers/devfreq/governor_passive.c
>>
>> --
>> 1.9.1
>>
> 
> I could not get this series to work with my Odroid U3.
> 
> [    4.602768] input: gpio_keys as /devices/platform/gpio_keys/input/input0
> [    4.605527] devfreq bus_leftbus: Couldn't update frequency
> transition information.
> [    4.607319] devfreq bus_dmc: Couldn't update frequency transition
> information.
> [    4.625096] usb 1-3: New USB device found, idVendor=0424, idProduct=3503

This log indicates the problem of 'trats_stat' sysfs entry of devfreq framework
during kernel booting. But, this log don't affect the behavior of bus frequency
on Odroid-U3.

After completing kernel and platform booting, you can check the operation
of Bus frequency with follwoing sysfs entry:

root@localhost:~# ls -al /sys/class/devfreq
total 0
drwxr-xr-x  2 root root 0 Dec 31 17:00 .
drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_acp -> ../../devices/platform/bus_acp/devfreq/bus_acp
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_c2c -> ../../devices/platform/bus_c2c/devfreq/bus_c2c
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_dmc -> ../../devices/platform/bus_dmc/devfreq/bus_dmc
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus

root@localhost:~# cat /sys/class/devfreq/bus_leftbus/trans_stat 
     From  :   To
           : 100000000 134000000 160000000 200000000   time(ms)
  100000000:         0         0         0        24      2020
  134000000:         0         0         0        10      1190
  160000000:         0         0         0         0         0
* 200000000:        24        10         0         0    118160
Total transition : 68

Also, when changing the frequency of each bus, exynos-bus.c show
the debug message. If you need more detailed information,
you could check this log message.

Regards,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
  2015-12-09  4:07 ` [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for " Chanwoo Choi
@ 2015-12-10  0:39   ` Krzysztof Kozlowski
  2015-12-10  0:49       ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  0:39 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the documentation for generic exynos bus frequency
> driver.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 94 ++++++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> new file mode 100644
> index 000000000000..54a1f9c46c88
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -0,0 +1,94 @@
> +* Generic Exynos Bus frequency device
> +
> +The Samsung Exynos SoC have many buses for data transfer between DRAM
> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture
> +for buses. Generally, the each bus of Exynos SoC includes the source clock
> +and power line and then is able to change the clock according to the usage
> +of each buses on runtime. When gathering the usage of each buses on runtime,
> +thie driver uses the PPMU (Platform Performance Monitoring Unit) which

s/thie/the/

> +is able to measure the current load of sub-blocks.
> +
> +There are a little different composition among Exynos SoC because each Exynos
> +SoC has the different sub-blocks. So, this difference should be specified
> +in devicetree file instead of each device driver. In result, this driver
> +is able to support the bus frequency for all Exynos SoCs.
> +
> +Required properties for bus device:
> +- compatible: Should be "samsung,exynos-bus".
> +- clock-names : the name of clock used by the bus, "bus".
> +- clocks : phandles for clock specified in "clock-names" property.
> +- #clock-cells: should be 1.

This is a clock consumer, right? So the clock-cells is not valid here.

> +- operating-points-v2: the OPP table including frequency/voltage information
> +  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
> +- vdd-supply: the regulator to provide the buses with the voltage.
> +- devfreq-events: the devfreq-event device to monitor the curret utilization

s/curret/current/

> +  of buses.
> +
> +Optional properties for bus device:
> +- exynos,saturation-ratio: the percentage value which is used to calibrate
> +                   the performance count againt total cycle count.

s/againt/against/

> +
> +Example1:
> +	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
> +	power line (regulator). The MIF (Memory Interface) AXI bus is used to
> +	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
> +
> +	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
> +
> +	- MIF bus's frequency/voltage table
> +	-----------------------
> +	|Lv| Freq   | Voltage |
> +	-----------------------
> +	|L1| 50000  |800000   |
> +	|L2| 100000 |800000   |
> +	|L3| 134000 |800000   |
> +	|L4| 200000 |800000   |
> +	|L5| 400000 |875000   |
> +	-----------------------
> +
> +Example2 :
> +	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
> +	are listed below:

s/are/is/ (one bus is listed)

> +
> +	bus_dmc: bus_dmc {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu_dmc CLK_DIV_DMC>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_dmc_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_dmc_opp_table: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {

Maybe use convention with frequency, like:
	opp@50000000
This also used in opp.txt examples.


> +			opp-hz = /bits/ 64 <50000000>;
> +			opp-microvolt = <800000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			opp-microvolt = <800000>;
> +		};
> +		opp02 {
> +			opp-hz = /bits/ 64 <134000000>;
> +			opp-microvolt = <800000>;
> +		};
> +		opp03 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <800000>;
> +		};
> +		opp04 {
> +			opp-hz = /bits/ 64 <400000000>;
> +			opp-microvolt = <875000>;
> +		};
> +	};
> +
> +	Usage case to handle the frequency and voltage of bus on runtime
> +	in exynos3250-rinato.dts are listed below:

s/are/is/

> +
> +	&bus_dmc {
> +		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> +		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
> +		status = "okay";
> +	};
> 


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-09  4:07 ` [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250 Chanwoo Choi
@ 2015-12-10  0:44   ` Krzysztof Kozlowski
  2015-12-10  1:09     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  0:44 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
> block.
> 
> Following list specifies the detailed relation between the clock and DMC block:
> - The source clock of DMC block : div_dmc
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 2f30d632f1cc..7214c5e42150 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -687,6 +687,40 @@
>  			clock-names = "ppmu";
>  			status = "disabled";
>  		};
> +
> +		bus_dmc: bus_dmc {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_dmc_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_dmc_opp_table: opp_table1 {

This is the firsy opp_table, right? So:
s/opp_table1/opp_table0/

> +			compatible = "operating-points-v2";
> +			opp-shared;
> +
> +			opp00 {
> +				opp-hz = /bits/ 64 <50000000>;
> +				opp-microvolt = <800000>;
> +			};
> +			opp01 {
> +				opp-hz = /bits/ 64 <100000000>;
> +				opp-microvolt = <800000>;
> +			};
> +			opp02 {
> +				opp-hz = /bits/ 64 <134000000>;
> +				opp-microvolt = <800000>;

Why 134, not 133 MHz?

> +			};
> +			opp03 {
> +				opp-hz = /bits/ 64 <200000000>;
> +				opp-microvolt = <800000>;

Shouldn't this be 825 mV, not 800? I think we used previously that value
for our devices.

Best regards,
Krzysztof


> +			};
> +			opp04 {
> +				opp-hz = /bits/ 64 <400000000>;
> +				opp-microvolt = <875000>;
> +			};
> +		};
>  	};
>  };
>  
> 


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
@ 2015-12-10  0:49       ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  0:49 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

Hi,

On 2015년 12월 10일 09:39, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the documentation for generic exynos bus frequency
>> driver.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 94 ++++++++++++++++++++++
>>  1 file changed, 94 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> new file mode 100644
>> index 000000000000..54a1f9c46c88
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -0,0 +1,94 @@
>> +* Generic Exynos Bus frequency device
>> +
>> +The Samsung Exynos SoC have many buses for data transfer between DRAM
>> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture
>> +for buses. Generally, the each bus of Exynos SoC includes the source clock
>> +and power line and then is able to change the clock according to the usage
>> +of each buses on runtime. When gathering the usage of each buses on runtime,
>> +thie driver uses the PPMU (Platform Performance Monitoring Unit) which
> 
> s/thie/the/

OK.

> 
>> +is able to measure the current load of sub-blocks.
>> +
>> +There are a little different composition among Exynos SoC because each Exynos
>> +SoC has the different sub-blocks. So, this difference should be specified
>> +in devicetree file instead of each device driver. In result, this driver
>> +is able to support the bus frequency for all Exynos SoCs.
>> +
>> +Required properties for bus device:
>> +- compatible: Should be "samsung,exynos-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- #clock-cells: should be 1.
> 
> This is a clock consumer, right? So the clock-cells is not valid here.

You're right. I'll remove '#clock-cells'.

> 
>> +- operating-points-v2: the OPP table including frequency/voltage information
>> +  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +- vdd-supply: the regulator to provide the buses with the voltage.
>> +- devfreq-events: the devfreq-event device to monitor the curret utilization
> 
> s/curret/current/
> 
>> +  of buses.
>> +
>> +Optional properties for bus device:
>> +- exynos,saturation-ratio: the percentage value which is used to calibrate
>> +                   the performance count againt total cycle count.
> 
> s/againt/against/

OK.

> 
>> +
>> +Example1:
>> +	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
>> +	power line (regulator). The MIF (Memory Interface) AXI bus is used to
>> +	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>> +
>> +	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>> +
>> +	- MIF bus's frequency/voltage table
>> +	-----------------------
>> +	|Lv| Freq   | Voltage |
>> +	-----------------------
>> +	|L1| 50000  |800000   |
>> +	|L2| 100000 |800000   |
>> +	|L3| 134000 |800000   |
>> +	|L4| 200000 |800000   |
>> +	|L5| 400000 |875000   |
>> +	-----------------------
>> +
>> +Example2 :
>> +	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
>> +	are listed below:
> 
> s/are/is/ (one bus is listed)

OK.

> 
>> +
>> +	bus_dmc: bus_dmc {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu_dmc CLK_DIV_DMC>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_dmc_opp_table: opp_table0 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
> 
> Maybe use convention with frequency, like:
> 	opp@50000000
> This also used in opp.txt examples.

In the Documentations/devicetree/bindings/opp/opp.txt,
the example uses the 'opp@0x'. I check the opp.txt of Linux 4.4-rc4.

> 
> 
>> +			opp-hz = /bits/ 64 <50000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp02 {
>> +			opp-hz = /bits/ 64 <134000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp03 {
>> +			opp-hz = /bits/ 64 <200000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp04 {
>> +			opp-hz = /bits/ 64 <400000000>;
>> +			opp-microvolt = <875000>;
>> +		};
>> +	};
>> +
>> +	Usage case to handle the frequency and voltage of bus on runtime
>> +	in exynos3250-rinato.dts are listed below:
> 
> s/are/is/

OK.

> 
>> +
>> +	&bus_dmc {
>> +		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>> +		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
>> +		status = "okay";
>> +	};

Thanks for your review.

Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
@ 2015-12-10  0:49       ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  0:49 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ,
	kgene-DgEjT+Ai2ygdnm+yROfE0A
  Cc: kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	tjakobi-o02PS0xoJP9W0yFyLvAVXMxlOr/tl8fh,
	linux.amoon-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-pm-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA

Hi,

On 2015년 12월 10일 09:39, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the documentation for generic exynos bus frequency
>> driver.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> ---
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 94 ++++++++++++++++++++++
>>  1 file changed, 94 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> new file mode 100644
>> index 000000000000..54a1f9c46c88
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -0,0 +1,94 @@
>> +* Generic Exynos Bus frequency device
>> +
>> +The Samsung Exynos SoC have many buses for data transfer between DRAM
>> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture
>> +for buses. Generally, the each bus of Exynos SoC includes the source clock
>> +and power line and then is able to change the clock according to the usage
>> +of each buses on runtime. When gathering the usage of each buses on runtime,
>> +thie driver uses the PPMU (Platform Performance Monitoring Unit) which
> 
> s/thie/the/

OK.

> 
>> +is able to measure the current load of sub-blocks.
>> +
>> +There are a little different composition among Exynos SoC because each Exynos
>> +SoC has the different sub-blocks. So, this difference should be specified
>> +in devicetree file instead of each device driver. In result, this driver
>> +is able to support the bus frequency for all Exynos SoCs.
>> +
>> +Required properties for bus device:
>> +- compatible: Should be "samsung,exynos-bus".
>> +- clock-names : the name of clock used by the bus, "bus".
>> +- clocks : phandles for clock specified in "clock-names" property.
>> +- #clock-cells: should be 1.
> 
> This is a clock consumer, right? So the clock-cells is not valid here.

You're right. I'll remove '#clock-cells'.

> 
>> +- operating-points-v2: the OPP table including frequency/voltage information
>> +  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +- vdd-supply: the regulator to provide the buses with the voltage.
>> +- devfreq-events: the devfreq-event device to monitor the curret utilization
> 
> s/curret/current/
> 
>> +  of buses.
>> +
>> +Optional properties for bus device:
>> +- exynos,saturation-ratio: the percentage value which is used to calibrate
>> +                   the performance count againt total cycle count.
> 
> s/againt/against/

OK.

> 
>> +
>> +Example1:
>> +	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
>> +	power line (regulator). The MIF (Memory Interface) AXI bus is used to
>> +	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>> +
>> +	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>> +
>> +	- MIF bus's frequency/voltage table
>> +	-----------------------
>> +	|Lv| Freq   | Voltage |
>> +	-----------------------
>> +	|L1| 50000  |800000   |
>> +	|L2| 100000 |800000   |
>> +	|L3| 134000 |800000   |
>> +	|L4| 200000 |800000   |
>> +	|L5| 400000 |875000   |
>> +	-----------------------
>> +
>> +Example2 :
>> +	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
>> +	are listed below:
> 
> s/are/is/ (one bus is listed)

OK.

> 
>> +
>> +	bus_dmc: bus_dmc {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu_dmc CLK_DIV_DMC>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_dmc_opp_table: opp_table0 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
> 
> Maybe use convention with frequency, like:
> 	opp@50000000
> This also used in opp.txt examples.

In the Documentations/devicetree/bindings/opp/opp.txt,
the example uses the 'opp@0x'. I check the opp.txt of Linux 4.4-rc4.

> 
> 
>> +			opp-hz = /bits/ 64 <50000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp02 {
>> +			opp-hz = /bits/ 64 <134000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp03 {
>> +			opp-hz = /bits/ 64 <200000000>;
>> +			opp-microvolt = <800000>;
>> +		};
>> +		opp04 {
>> +			opp-hz = /bits/ 64 <400000000>;
>> +			opp-microvolt = <875000>;
>> +		};
>> +	};
>> +
>> +	Usage case to handle the frequency and voltage of bus on runtime
>> +	in exynos3250-rinato.dts are listed below:
> 
> s/are/is/

OK.

> 
>> +
>> +	&bus_dmc {
>> +		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>> +		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
>> +		status = "okay";
>> +	};

Thanks for your review.

Regards,
Chanwoo Choi

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^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
  2015-12-09  4:07 ` [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk Chanwoo Choi
@ 2015-12-10  0:53   ` Krzysztof Kozlowski
  2015-12-10  0:56     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  0:53 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:07, Chanwoo Choi wrote:
> This patch adds the DMC (Dynamic Memory Controller) bus frequency node
> which includes the devfreq-events and regulator properties. The bus
> frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
> with ondemand governor.
> 
> The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
> on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
> the DMC block.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos3250-monk.dts   | 6 ++++++
>  arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
> index 443a35085846..d982586a6533 100644
> --- a/arch/arm/boot/dts/exynos3250-monk.dts
> +++ b/arch/arm/boot/dts/exynos3250-monk.dts
> @@ -498,6 +498,12 @@
>  	};
>  };
>  
> +&bus_dmc {
> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> +	vdd-supply = <&buck1_reg>;
> +	status = "okay";
> +};
> +
>  &xusbxti {
>  	clock-frequency = <24000000>;
>  };
> diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
> index 3e64d5dcdd60..61477943015b 100644
> --- a/arch/arm/boot/dts/exynos3250-rinato.dts
> +++ b/arch/arm/boot/dts/exynos3250-rinato.dts
> @@ -675,6 +675,12 @@
>  	};
>  };
>  
> +&bus_dmc {
> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> +	vdd-supply = <&buck1_reg>;
> +	status = "okay";
> +};

I would prefer to put this in alphabetical order... which could be
tricky because the nodes are not entirely sorted. Maybe after the "&adc"
node?

Anyway the change looks good:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof



^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
  2015-12-10  0:53   ` Krzysztof Kozlowski
@ 2015-12-10  0:56     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  0:56 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 09:53, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the DMC (Dynamic Memory Controller) bus frequency node
>> which includes the devfreq-events and regulator properties. The bus
>> frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature
>> with ondemand governor.
>>
>> The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus
>> on runtime and the buck1_reg (VDD_MIF power line) supplies the power to
>> the DMC block.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos3250-monk.dts   | 6 ++++++
>>  arch/arm/boot/dts/exynos3250-rinato.dts | 6 ++++++
>>  2 files changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
>> index 443a35085846..d982586a6533 100644
>> --- a/arch/arm/boot/dts/exynos3250-monk.dts
>> +++ b/arch/arm/boot/dts/exynos3250-monk.dts
>> @@ -498,6 +498,12 @@
>>  	};
>>  };
>>  
>> +&bus_dmc {
>> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>> +	vdd-supply = <&buck1_reg>;
>> +	status = "okay";
>> +};
>> +
>>  &xusbxti {
>>  	clock-frequency = <24000000>;
>>  };
>> diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
>> index 3e64d5dcdd60..61477943015b 100644
>> --- a/arch/arm/boot/dts/exynos3250-rinato.dts
>> +++ b/arch/arm/boot/dts/exynos3250-rinato.dts
>> @@ -675,6 +675,12 @@
>>  	};
>>  };
>>  
>> +&bus_dmc {
>> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>> +	vdd-supply = <&buck1_reg>;
>> +	status = "okay";
>> +};
> 
> I would prefer to put this in alphabetical order... which could be
> tricky because the nodes are not entirely sorted. Maybe after the "&adc"
> node?

OK. I'll move it.

> 
> Anyway the change looks good:
> 
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks for your review.

Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
  2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
                   ` (19 preceding siblings ...)
  2015-12-09 19:05 ` [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Anand Moon
@ 2015-12-10  0:57 ` Krzysztof Kozlowski
  2015-12-10  1:22   ` Krzysztof Kozlowski
  20 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  0:57 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:07, Chanwoo Choi wrote:

(...)

>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++

How about adding this file to the MAINTAINERS to devfreq exynos entry?
Unfortunately, in current linux-next, I can find the entry for devfreq
exynos. However I saw patches adding such entries... aren't they merged
to linux-next?

Best regards,
Krzysztof

>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>  drivers/devfreq/Kconfig                            |   37 +-
>  drivers/devfreq/Makefile                           |    2 +
>  drivers/devfreq/devfreq.c                          |  120 ++-
>  drivers/devfreq/exynos/Makefile                    |    3 +-
>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>  drivers/devfreq/governor.h                         |    7 +
>  drivers/devfreq/governor_passive.c                 |  109 ++
>  drivers/devfreq/governor_performance.c             |    1 +
>  drivers/devfreq/governor_powersave.c               |    1 +
>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>  drivers/devfreq/governor_userspace.c               |    1 +
>  include/linux/devfreq.h                            |   28 +
>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>  create mode 100644 drivers/devfreq/governor_passive.c
> 


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-10  0:44   ` Krzysztof Kozlowski
@ 2015-12-10  1:09     ` Chanwoo Choi
  2015-12-10  1:20       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  1:09 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>> block.
>>
>> Following list specifies the detailed relation between the clock and DMC block:
>> - The source clock of DMC block : div_dmc
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>> index 2f30d632f1cc..7214c5e42150 100644
>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -687,6 +687,40 @@
>>  			clock-names = "ppmu";
>>  			status = "disabled";
>>  		};
>> +
>> +		bus_dmc: bus_dmc {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_dmc_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_dmc_opp_table: opp_table1 {
> 
> This is the firsy opp_table, right? So:
> s/opp_table1/opp_table0/

Right. It is first opp_table in exynos3250.dtsi.
But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.

> 
>> +			compatible = "operating-points-v2";
>> +			opp-shared;
>> +
>> +			opp00 {
>> +				opp-hz = /bits/ 64 <50000000>;
>> +				opp-microvolt = <800000>;
>> +			};
>> +			opp01 {
>> +				opp-hz = /bits/ 64 <100000000>;
>> +				opp-microvolt = <800000>;
>> +			};
>> +			opp02 {
>> +				opp-hz = /bits/ 64 <134000000>;
>> +				opp-microvolt = <800000>;
> 
> Why 134, not 133 MHz?

When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz.
I add following test result on exynos3250-rinato board.

Case1.
When I use the 134 MHz, the source clock is changed to 133MHz
: exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334)

Case2.
When I use the 133 MHz, the source clock is changed to 100MHz
: exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000)

> 
>> +			};
>> +			opp03 {
>> +				opp-hz = /bits/ 64 <200000000>;
>> +				opp-microvolt = <800000>;
> 
> Shouldn't this be 825 mV, not 800? I think we used previously that value
> for our devices.

OK. I'll modify it.

Regards,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-10  1:09     ` Chanwoo Choi
@ 2015-12-10  1:20       ` Krzysztof Kozlowski
  2015-12-10  2:00         ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  1:20 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 10:09, Chanwoo Choi wrote:
> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>>> block.
>>>
>>> Following list specifies the detailed relation between the clock and DMC block:
>>> - The source clock of DMC block : div_dmc
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> ---
>>>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>>>  1 file changed, 34 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>>> index 2f30d632f1cc..7214c5e42150 100644
>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>> @@ -687,6 +687,40 @@
>>>  			clock-names = "ppmu";
>>>  			status = "disabled";
>>>  		};
>>> +
>>> +		bus_dmc: bus_dmc {
>>> +			compatible = "samsung,exynos-bus";
>>> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
>>> +			clock-names = "bus";
>>> +			operating-points-v2 = <&bus_dmc_opp_table>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		bus_dmc_opp_table: opp_table1 {
>>
>> This is the firsy opp_table, right? So:
>> s/opp_table1/opp_table0/
> 
> Right. It is first opp_table in exynos3250.dtsi.
> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.

Ok

> 
>>
>>> +			compatible = "operating-points-v2";
>>> +			opp-shared;
>>> +
>>> +			opp00 {
>>> +				opp-hz = /bits/ 64 <50000000>;
>>> +				opp-microvolt = <800000>;
>>> +			};
>>> +			opp01 {
>>> +				opp-hz = /bits/ 64 <100000000>;
>>> +				opp-microvolt = <800000>;
>>> +			};
>>> +			opp02 {
>>> +				opp-hz = /bits/ 64 <134000000>;
>>> +				opp-microvolt = <800000>;
>>
>> Why 134, not 133 MHz?
> 
> When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz.
> I add following test result on exynos3250-rinato board.
> 
> Case1.
> When I use the 134 MHz, the source clock is changed to 133MHz
> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334)
> 
> Case2.
> When I use the 133 MHz, the source clock is changed to 100MHz
> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000)

Now I remember that issue. You could use here directly 133333334 but
that also would look a little bit weird... so 134 is ok for me. Could
just add a comment that desired frequency is actually "133 MHz"?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
  2015-12-10  0:57 ` Krzysztof Kozlowski
@ 2015-12-10  1:22   ` Krzysztof Kozlowski
  2015-12-10  2:16     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  1:22 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 09:57, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:07, Chanwoo Choi wrote:
> 
> (...)
> 
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
> 
> How about adding this file to the MAINTAINERS to devfreq exynos entry?
> Unfortunately, in current linux-next, I can find the entry for devfreq

D'oh! I meant:                        ^ I cannot find the entry for...

BR,
Krzysztof

> exynos. However I saw patches adding such entries... aren't they merged
> to linux-next?
> 
> Best regards,
> Krzysztof
> 
>>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>>  drivers/devfreq/Kconfig                            |   37 +-
>>  drivers/devfreq/Makefile                           |    2 +
>>  drivers/devfreq/devfreq.c                          |  120 ++-
>>  drivers/devfreq/exynos/Makefile                    |    3 +-
>>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>>  drivers/devfreq/governor.h                         |    7 +
>>  drivers/devfreq/governor_passive.c                 |  109 ++
>>  drivers/devfreq/governor_performance.c             |    1 +
>>  drivers/devfreq/governor_powersave.c               |    1 +
>>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>>  drivers/devfreq/governor_userspace.c               |    1 +
>>  include/linux/devfreq.h                            |   28 +
>>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>>  create mode 100644 drivers/devfreq/governor_passive.c
>>
> 
> 


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
  2015-12-10  0:49       ` Chanwoo Choi
  (?)
@ 2015-12-10  1:25       ` Krzysztof Kozlowski
  2015-12-10  1:33         ` Chanwoo Choi
  -1 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  1:25 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 09:49, Chanwoo Choi wrote:
> Hi,
> 
(...)

>>
>>> +
>>> +	bus_dmc: bus_dmc {
>>> +		compatible = "samsung,exynos-bus";
>>> +		clocks = <&cmu_dmc CLK_DIV_DMC>;
>>> +		clock-names = "bus";
>>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>>> +		status = "disabled";
>>> +	};
>>> +
>>> +	bus_dmc_opp_table: opp_table0 {
>>> +		compatible = "operating-points-v2";
>>> +		opp-shared;
>>> +
>>> +		opp00 {
>>
>> Maybe use convention with frequency, like:
>> 	opp@50000000
>> This also used in opp.txt examples.
> 
> In the Documentations/devicetree/bindings/opp/opp.txt,
> the example uses the 'opp@0x'. I check the opp.txt of Linux 4.4-rc4.

Yes, it was changed by Viresh in "PM / OPP: Rename OPP nodes as
opp@<opp-hz>". You can find the most actual bindings in linux-next.

Best regards,
Krzysztof




^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-09  4:08 ` [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices " Chanwoo Choi
@ 2015-12-10  1:31   ` Krzysztof Kozlowski
  2015-12-10  1:36     ` Chanwoo Choi
  2015-12-10 14:21   ` Rob Herring
  1 sibling, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  1:31 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch updates the documentation for passive bus devices and adds the
> detailed example of Exynos3250.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
>  1 file changed, 241 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> index 54a1f9c46c88..c4fdc70f8eac 100644
> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
>  in devicetree file instead of each device driver. In result, this driver
>  is able to support the bus frequency for all Exynos SoCs.
>  
> -Required properties for bus device:
> +Required properties for all bus devices:
>  - compatible: Should be "samsung,exynos-bus".
>  - clock-names : the name of clock used by the bus, "bus".
>  - clocks : phandles for clock specified in "clock-names" property.
>  - #clock-cells: should be 1.
>  - operating-points-v2: the OPP table including frequency/voltage information
>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
> +
> +Required properties for only parent bus device:

Maybe:
"Required properties only for parent bus devices:"

In this binding documentation file the idea of "parent" is not
explained. I now it is related to passive devfreq governor but looking
at the binding itself it is a new idea, not covered here.

>  - vdd-supply: the regulator to provide the buses with the voltage.
>  - devfreq-events: the devfreq-event device to monitor the curret utilization
>    of buses.
>  
> -Optional properties for bus device:
> +Required properties for only passive bus device:

"Required properties only for passive bus devices:"

> +- devfreq: the parent bus device.
> +
> +Optional properties for only parent bus device:
>  - exynos,saturation-ratio: the percentage value which is used to calibrate
>                     the performance count againt total cycle count.
>  
> @@ -33,7 +38,20 @@ Example1:
>  	power line (regulator). The MIF (Memory Interface) AXI bus is used to
>  	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>  
> -	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
> +	- MIF (Memory Interface) block
> +	: VDD_MIF |--- DMC (Dynamic Memory Controller)
> +
> +	- INT (Internal) block
> +	: VDD_INT |--- LEFTBUS (parent device)
> +		  |--- PERIL
> +		  |--- MFC
> +		  |--- G3D
> +		  |--- RIGHTBUS
> +		  |--- FSYS
> +		  |--- LCD0
> +		  |--- PERIR
> +		  |--- ISP
> +		  |--- CAM
>  
>  	- MIF bus's frequency/voltage table
>  	-----------------------
> @@ -46,6 +64,24 @@ Example1:
>  	|L5| 400000 |875000   |
>  	-----------------------
>  
> +	- INT bus's frequency/voltage table
> +	----------------------------------------------------------
> +	|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
> +	| name|       |LCD0    |       |       |       ||        |
> +	|     |       |FSYS    |       |       |       ||        |
> +	|     |       |MFC     |       |       |       ||        |
> +	----------------------------------------------------------
> +	|Mode |*parent|passive |passive|passive|passive||        |
> +	----------------------------------------------------------
> +	|Lv   |Frequency                               ||Voltage |
> +	----------------------------------------------------------
> +	|L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
> +	|L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
> +	|L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
> +	|L4   |134000 |134000  |200000 |200000 |       ||1000000 |
> +	|L5   |200000 |200000  |400000 |300000 |       ||1000000 |
> +	----------------------------------------------------------
> +
>  Example2 :
>  	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
>  	are listed below:
> @@ -84,6 +120,167 @@ Example2 :
>  		};
>  	};
>  
> +	bus_leftbus: bus_leftbus {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu CLK_DIV_GDL>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_rightbus: bus_rightbus {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu CLK_DIV_GDR>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_lcd0: bus_lcd0 {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu CLK_DIV_ACLK_160>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_fsys: bus_fsys {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu CLK_DIV_ACLK_200>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_mcuisp: bus_mcuisp {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_mcuisp_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_isp: bus_isp {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&cmu CLK_DIV_ACLK_266>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_isp_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_peril: bus_perir {


Peril or perir?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
  2015-12-10  1:25       ` Krzysztof Kozlowski
@ 2015-12-10  1:33         ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  1:33 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 10:25, Krzysztof Kozlowski wrote:
> On 10.12.2015 09:49, Chanwoo Choi wrote:
>> Hi,
>>
> (...)
> 
>>>
>>>> +
>>>> +	bus_dmc: bus_dmc {
>>>> +		compatible = "samsung,exynos-bus";
>>>> +		clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>> +		clock-names = "bus";
>>>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>>>> +		status = "disabled";
>>>> +	};
>>>> +
>>>> +	bus_dmc_opp_table: opp_table0 {
>>>> +		compatible = "operating-points-v2";
>>>> +		opp-shared;
>>>> +
>>>> +		opp00 {
>>>
>>> Maybe use convention with frequency, like:
>>> 	opp@50000000
>>> This also used in opp.txt examples.
>>
>> In the Documentations/devicetree/bindings/opp/opp.txt,
>> the example uses the 'opp@0x'. I check the opp.txt of Linux 4.4-rc4.
> 
> Yes, it was changed by Viresh in "PM / OPP: Rename OPP nodes as
> opp@<opp-hz>". You can find the most actual bindings in linux-next.

OK. I'll.

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-10  1:31   ` Krzysztof Kozlowski
@ 2015-12-10  1:36     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  1:36 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 10:31, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch updates the documentation for passive bus devices and adds the
>> detailed example of Exynos3250.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
>>  1 file changed, 241 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> index 54a1f9c46c88..c4fdc70f8eac 100644
>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
>>  in devicetree file instead of each device driver. In result, this driver
>>  is able to support the bus frequency for all Exynos SoCs.
>>  
>> -Required properties for bus device:
>> +Required properties for all bus devices:
>>  - compatible: Should be "samsung,exynos-bus".
>>  - clock-names : the name of clock used by the bus, "bus".
>>  - clocks : phandles for clock specified in "clock-names" property.
>>  - #clock-cells: should be 1.
>>  - operating-points-v2: the OPP table including frequency/voltage information
>>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +
>> +Required properties for only parent bus device:
> 
> Maybe:
> "Required properties only for parent bus devices:"

OK. I'll modify it.

> 
> In this binding documentation file the idea of "parent" is not
> explained. I now it is related to passive devfreq governor but looking
> at the binding itself it is a new idea, not covered here.

OK. I'll add the detailed description of 'parent' and
correlation between 'parent' and 'passive' device.

> 
>>  - vdd-supply: the regulator to provide the buses with the voltage.
>>  - devfreq-events: the devfreq-event device to monitor the curret utilization
>>    of buses.
>>  
>> -Optional properties for bus device:
>> +Required properties for only passive bus device:
> 
> "Required properties only for passive bus devices:"

OK. I'll modify it.

> 
>> +- devfreq: the parent bus device.
>> +
>> +Optional properties for only parent bus device:
>>  - exynos,saturation-ratio: the percentage value which is used to calibrate
>>                     the performance count againt total cycle count.
>>  
>> @@ -33,7 +38,20 @@ Example1:
>>  	power line (regulator). The MIF (Memory Interface) AXI bus is used to
>>  	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>>  
>> -	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>> +	- MIF (Memory Interface) block
>> +	: VDD_MIF |--- DMC (Dynamic Memory Controller)
>> +
>> +	- INT (Internal) block
>> +	: VDD_INT |--- LEFTBUS (parent device)
>> +		  |--- PERIL
>> +		  |--- MFC
>> +		  |--- G3D
>> +		  |--- RIGHTBUS
>> +		  |--- FSYS
>> +		  |--- LCD0
>> +		  |--- PERIR
>> +		  |--- ISP
>> +		  |--- CAM
>>  
>>  	- MIF bus's frequency/voltage table
>>  	-----------------------
>> @@ -46,6 +64,24 @@ Example1:
>>  	|L5| 400000 |875000   |
>>  	-----------------------
>>  
>> +	- INT bus's frequency/voltage table
>> +	----------------------------------------------------------
>> +	|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
>> +	| name|       |LCD0    |       |       |       ||        |
>> +	|     |       |FSYS    |       |       |       ||        |
>> +	|     |       |MFC     |       |       |       ||        |
>> +	----------------------------------------------------------
>> +	|Mode |*parent|passive |passive|passive|passive||        |
>> +	----------------------------------------------------------
>> +	|Lv   |Frequency                               ||Voltage |
>> +	----------------------------------------------------------
>> +	|L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
>> +	|L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
>> +	|L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
>> +	|L4   |134000 |134000  |200000 |200000 |       ||1000000 |
>> +	|L5   |200000 |200000  |400000 |300000 |       ||1000000 |
>> +	----------------------------------------------------------
>> +
>>  Example2 :
>>  	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
>>  	are listed below:
>> @@ -84,6 +120,167 @@ Example2 :
>>  		};
>>  	};
>>  
>> +	bus_leftbus: bus_leftbus {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu CLK_DIV_GDL>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_rightbus: bus_rightbus {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu CLK_DIV_GDR>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_lcd0: bus_lcd0 {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu CLK_DIV_ACLK_160>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_fsys: bus_fsys {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu CLK_DIV_ACLK_200>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_mcuisp: bus_mcuisp {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_mcuisp_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_isp: bus_isp {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&cmu CLK_DIV_ACLK_266>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_isp_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_peril: bus_perir {
> 
> 
> Peril or perir?

peril is correct. I'll fix it.

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-10  1:20       ` Krzysztof Kozlowski
@ 2015-12-10  2:00         ` Chanwoo Choi
  2015-12-10  2:04           ` Krzysztof Kozlowski
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  2:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
> On 10.12.2015 10:09, Chanwoo Choi wrote:
>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>>>> block.
>>>>
>>>> Following list specifies the detailed relation between the clock and DMC block:
>>>> - The source clock of DMC block : div_dmc
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> ---
>>>>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>>>>  1 file changed, 34 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>>>> index 2f30d632f1cc..7214c5e42150 100644
>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>>> @@ -687,6 +687,40 @@
>>>>  			clock-names = "ppmu";
>>>>  			status = "disabled";
>>>>  		};
>>>> +
>>>> +		bus_dmc: bus_dmc {
>>>> +			compatible = "samsung,exynos-bus";
>>>> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>> +			clock-names = "bus";
>>>> +			operating-points-v2 = <&bus_dmc_opp_table>;
>>>> +			status = "disabled";
>>>> +		};
>>>> +
>>>> +		bus_dmc_opp_table: opp_table1 {
>>>
>>> This is the firsy opp_table, right? So:
>>> s/opp_table1/opp_table0/
>>
>> Right. It is first opp_table in exynos3250.dtsi.
>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
>> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.
> 
> Ok
> 
>>
>>>
>>>> +			compatible = "operating-points-v2";
>>>> +			opp-shared;
>>>> +
>>>> +			opp00 {
>>>> +				opp-hz = /bits/ 64 <50000000>;
>>>> +				opp-microvolt = <800000>;
>>>> +			};
>>>> +			opp01 {
>>>> +				opp-hz = /bits/ 64 <100000000>;
>>>> +				opp-microvolt = <800000>;
>>>> +			};
>>>> +			opp02 {
>>>> +				opp-hz = /bits/ 64 <134000000>;
>>>> +				opp-microvolt = <800000>;
>>>
>>> Why 134, not 133 MHz?
>>
>> When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz.
>> I add following test result on exynos3250-rinato board.
>>
>> Case1.
>> When I use the 134 MHz, the source clock is changed to 133MHz
>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334)
>>
>> Case2.
>> When I use the 133 MHz, the source clock is changed to 100MHz
>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000)
> 
> Now I remember that issue. You could use here directly 133333334 but
> that also would look a little bit weird... so 134 is ok for me. Could
> just add a comment that desired frequency is actually "133 MHz"?

Do you prefer among following example?

Example1.
	opp02 {
		/* The desired frequency is 133MHz because
		 * clock change has the dependency on clock driver.
		 * When set rate as 134MHz, the clock driver would
		 * change the 133MHz actually instead of 134MHz.
		 */
		opp-hz = /bits/ 64 <134000000>;
		opp-microvolt = <800000>;
	};

Example2.
	opp02 {
		opp-hz = /bits/ 64 <133333334>;
		opp-microvolt = <800000>;
	};

Best Regards,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-10  2:00         ` Chanwoo Choi
@ 2015-12-10  2:04           ` Krzysztof Kozlowski
  2015-12-10  2:17             ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  2:04 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 11:00, Chanwoo Choi wrote:
> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
>> On 10.12.2015 10:09, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
>>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>>>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>>>>> block.
>>>>>
>>>>> Following list specifies the detailed relation between the clock and DMC block:
>>>>> - The source clock of DMC block : div_dmc
>>>>>
>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>> ---
>>>>>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>>>>>  1 file changed, 34 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>>>>> index 2f30d632f1cc..7214c5e42150 100644
>>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>>>> @@ -687,6 +687,40 @@
>>>>>  			clock-names = "ppmu";
>>>>>  			status = "disabled";
>>>>>  		};
>>>>> +
>>>>> +		bus_dmc: bus_dmc {
>>>>> +			compatible = "samsung,exynos-bus";
>>>>> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>>> +			clock-names = "bus";
>>>>> +			operating-points-v2 = <&bus_dmc_opp_table>;
>>>>> +			status = "disabled";
>>>>> +		};
>>>>> +
>>>>> +		bus_dmc_opp_table: opp_table1 {
>>>>
>>>> This is the firsy opp_table, right? So:
>>>> s/opp_table1/opp_table0/
>>>
>>> Right. It is first opp_table in exynos3250.dtsi.
>>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
>>> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.
>>
>> Ok
>>
>>>
>>>>
>>>>> +			compatible = "operating-points-v2";
>>>>> +			opp-shared;
>>>>> +
>>>>> +			opp00 {
>>>>> +				opp-hz = /bits/ 64 <50000000>;
>>>>> +				opp-microvolt = <800000>;
>>>>> +			};
>>>>> +			opp01 {
>>>>> +				opp-hz = /bits/ 64 <100000000>;
>>>>> +				opp-microvolt = <800000>;
>>>>> +			};
>>>>> +			opp02 {
>>>>> +				opp-hz = /bits/ 64 <134000000>;
>>>>> +				opp-microvolt = <800000>;
>>>>
>>>> Why 134, not 133 MHz?
>>>
>>> When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz.
>>> I add following test result on exynos3250-rinato board.
>>>
>>> Case1.
>>> When I use the 134 MHz, the source clock is changed to 133MHz
>>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334)
>>>
>>> Case2.
>>> When I use the 133 MHz, the source clock is changed to 100MHz
>>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000)
>>
>> Now I remember that issue. You could use here directly 133333334 but
>> that also would look a little bit weird... so 134 is ok for me. Could
>> just add a comment that desired frequency is actually "133 MHz"?
> 
> Do you prefer among following example?
> 
> Example1.
> 	opp02 {
> 		/* The desired frequency is 133MHz because
> 		 * clock change has the dependency on clock driver.
> 		 * When set rate as 134MHz, the clock driver would
> 		 * change the 133MHz actually instead of 134MHz.
> 		 */
> 		opp-hz = /bits/ 64 <134000000>;
> 		opp-microvolt = <800000>;
> 	};
> 
> Example2.
> 	opp02 {
> 		opp-hz = /bits/ 64 <133333334>;
> 		opp-microvolt = <800000>;
> 	};

I would prefer the second one (133333334) but I don't have strong
feelings about it.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
  2015-12-09  4:08 ` [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Chanwoo Choi
@ 2015-12-10  2:09   ` Krzysztof Kozlowski
  2015-12-10  2:30     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  2:09 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
> Exynos3250 has following AXI buses to translate data between
> DRAM and sub-blocks.
> 
> Following list specifies the detailed relation between DRAM and sub-blocks:
> - ACLK400 clock for MCUISP
> - ACLK266 clock for ISP
> - ACLK200 clock for FSYS
> - ACLK160 clock for LCD0
> - ACLK100 clock for PERIL
> - GDL clock for LEFTBUS
> - GDR clock for RIGHTBUS
> - SCLK_MFC clock for MFC
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 160 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
> index 7214c5e42150..46dee1951ec1 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -721,6 +721,166 @@
>  				opp-microvolt = <875000>;
>  			};
>  		};
> +
> +		bus_leftbus: bus_leftbus {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_GDL>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_leftbus_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_rightbus: bus_rightbus {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_GDR>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_leftbus_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_lcd0: bus_lcd0 {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_ACLK_160>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_leftbus_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_fsys: bus_fsys {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_ACLK_200>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_leftbus_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_mcuisp: bus_mcuisp {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_mcuisp_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_isp: bus_isp {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_ACLK_266>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_isp_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_peril: bus_peril {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_DIV_ACLK_100>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_peril_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_mfc: bus_mfc {
> +			compatible = "samsung,exynos-bus";
> +			clocks = <&cmu CLK_SCLK_MFC>;
> +			clock-names = "bus";
> +			operating-points-v2 = <&bus_leftbus_opp_table>;
> +			status = "disabled";
> +		};
> +
> +		bus_leftbus_opp_table: opp_table2 {
> +			compatible = "operating-points-v2";
> +			opp-shared;
> +
> +			opp00 {
> +				opp-hz = /bits/ 64 <50000000>;
> +				opp-microvolt = <900000>;
> +			};
> +			opp01 {
> +				opp-hz = /bits/ 64 <80000000>;
> +				opp-microvolt = <900000>;
> +			};
> +			opp02 {
> +				opp-hz = /bits/ 64 <100000000>;
> +				opp-microvolt = <1000000>;
> +			};
> +			opp03 {
> +				opp-hz = /bits/ 64 <134000000>;
> +				opp-microvolt = <1000000>;
> +			};
> +			opp04 {
> +				opp-hz = /bits/ 64 <200000000>;
> +				opp-microvolt = <1000000>;
> +			};
> +		};
> +
> +		bus_mcuisp_opp_table: opp_table3 {
> +			compatible = "operating-points-v2";
> +			opp-shared;
> +
> +			opp00 {
> +				opp-hz = /bits/ 64 <50000000>;
> +				opp-microvolt = <900000>;

The voltages for all these INT-block tables have exactly the same value
which of course makes sense because this is the same regulator. However
the opp-microvolt property is an optional property. Do you have to
provide it in each OPP?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
  2015-12-10  1:22   ` Krzysztof Kozlowski
@ 2015-12-10  2:16     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  2:16 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 10:22, Krzysztof Kozlowski wrote:
> On 10.12.2015 09:57, Krzysztof Kozlowski wrote:
>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>
>> (...)
>>
>>>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
>>
>> How about adding this file to the MAINTAINERS to devfreq exynos entry?

OK. I'll add new entry for 'devfreq exynos' as following:
 
+SAMSUNG BUS DEVICE FREQUENCY SUPPORT
+M:     Chanwoo Choi <cw00.choi@samsung.com>
+L:     linux-pm@vger.kernel.org
+L:     linux-samsung-soc@vger.kernel.org
+T:     git git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git
+S:     Supported
+F:     drivers/devfreq/exynos/exynos-bus.c
+F:     Documentation/devicetree/bindings/devfreq/exynos-bus.txt

>> Unfortunately, in current linux-next, I can find the entry for devfreq
> 
> D'oh! I meant:                        ^ I cannot find the entry for...
> 
> BR,
> Krzysztof
> 
>> exynos. However I saw patches adding such entries... aren't they merged
>> to linux-next?

Yes, it is not merged to linux-next because any git repository
don't apply this patchset. To merge the devfreq patchset to linux-next,
devfreq maintainer should send the request mail to Stephen Rothwell.

[snip]

Best Regards,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-10  2:04           ` Krzysztof Kozlowski
@ 2015-12-10  2:17             ` Chanwoo Choi
  2015-12-10  2:21               ` Krzysztof Kozlowski
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  2:17 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 11:04, Krzysztof Kozlowski wrote:
> On 10.12.2015 11:00, Chanwoo Choi wrote:
>> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 10:09, Chanwoo Choi wrote:
>>>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
>>>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>>>>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>>>>>> block.
>>>>>>
>>>>>> Following list specifies the detailed relation between the clock and DMC block:
>>>>>> - The source clock of DMC block : div_dmc
>>>>>>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>> ---
>>>>>>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>>>>>>  1 file changed, 34 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> index 2f30d632f1cc..7214c5e42150 100644
>>>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>>>>> @@ -687,6 +687,40 @@
>>>>>>  			clock-names = "ppmu";
>>>>>>  			status = "disabled";
>>>>>>  		};
>>>>>> +
>>>>>> +		bus_dmc: bus_dmc {
>>>>>> +			compatible = "samsung,exynos-bus";
>>>>>> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>>>> +			clock-names = "bus";
>>>>>> +			operating-points-v2 = <&bus_dmc_opp_table>;
>>>>>> +			status = "disabled";
>>>>>> +		};
>>>>>> +
>>>>>> +		bus_dmc_opp_table: opp_table1 {
>>>>>
>>>>> This is the firsy opp_table, right? So:
>>>>> s/opp_table1/opp_table0/
>>>>
>>>> Right. It is first opp_table in exynos3250.dtsi.
>>>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
>>>> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.
>>>
>>> Ok
>>>
>>>>
>>>>>
>>>>>> +			compatible = "operating-points-v2";
>>>>>> +			opp-shared;
>>>>>> +
>>>>>> +			opp00 {
>>>>>> +				opp-hz = /bits/ 64 <50000000>;
>>>>>> +				opp-microvolt = <800000>;
>>>>>> +			};
>>>>>> +			opp01 {
>>>>>> +				opp-hz = /bits/ 64 <100000000>;
>>>>>> +				opp-microvolt = <800000>;
>>>>>> +			};
>>>>>> +			opp02 {
>>>>>> +				opp-hz = /bits/ 64 <134000000>;
>>>>>> +				opp-microvolt = <800000>;
>>>>>
>>>>> Why 134, not 133 MHz?
>>>>
>>>> When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz.
>>>> I add following test result on exynos3250-rinato board.
>>>>
>>>> Case1.
>>>> When I use the 134 MHz, the source clock is changed to 133MHz
>>>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334)
>>>>
>>>> Case2.
>>>> When I use the 133 MHz, the source clock is changed to 100MHz
>>>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000)
>>>
>>> Now I remember that issue. You could use here directly 133333334 but
>>> that also would look a little bit weird... so 134 is ok for me. Could
>>> just add a comment that desired frequency is actually "133 MHz"?
>>
>> Do you prefer among following example?
>>
>> Example1.
>> 	opp02 {
>> 		/* The desired frequency is 133MHz because
>> 		 * clock change has the dependency on clock driver.
>> 		 * When set rate as 134MHz, the clock driver would
>> 		 * change the 133MHz actually instead of 134MHz.
>> 		 */
>> 		opp-hz = /bits/ 64 <134000000>;
>> 		opp-microvolt = <800000>;
>> 	};
>>
>> Example2.
>> 	opp02 {
>> 		opp-hz = /bits/ 64 <133333334>;
>> 		opp-microvolt = <800000>;
>> 	};
> 
> I would prefer the second one (133333334) but I don't have strong
> feelings about it.

If you ok, I want to maintain the original approach as following:

	opp02 {
		opp-hz = /bits/ 64 <134000000>;
		opp-microvolt = <800000>;
	};

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250
  2015-12-10  2:17             ` Chanwoo Choi
@ 2015-12-10  2:21               ` Krzysztof Kozlowski
  0 siblings, 0 replies; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  2:21 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 11:17, Chanwoo Choi wrote:
> On 2015년 12월 10일 11:04, Krzysztof Kozlowski wrote:
>> On 10.12.2015 11:00, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote:
>>>> On 10.12.2015 10:09, Chanwoo Choi wrote:
>>>>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote:
>>>>>> On 09.12.2015 13:07, Chanwoo Choi wrote:
>>>>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC.
>>>>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard
>>>>>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC
>>>>>>> block.
>>>>>>>
>>>>>>> Following list specifies the detailed relation between the clock and DMC block:
>>>>>>> - The source clock of DMC block : div_dmc
>>>>>>>
>>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>>> ---
>>>>>>>  arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++
>>>>>>>  1 file changed, 34 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>>>>>>> index 2f30d632f1cc..7214c5e42150 100644
>>>>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>>>>>>> @@ -687,6 +687,40 @@
>>>>>>>  			clock-names = "ppmu";
>>>>>>>  			status = "disabled";
>>>>>>>  		};
>>>>>>> +
>>>>>>> +		bus_dmc: bus_dmc {
>>>>>>> +			compatible = "samsung,exynos-bus";
>>>>>>> +			clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>>>>> +			clock-names = "bus";
>>>>>>> +			operating-points-v2 = <&bus_dmc_opp_table>;
>>>>>>> +			status = "disabled";
>>>>>>> +		};
>>>>>>> +
>>>>>>> +		bus_dmc_opp_table: opp_table1 {
>>>>>>
>>>>>> This is the firsy opp_table, right? So:
>>>>>> s/opp_table1/opp_table0/
>>>>>
>>>>> Right. It is first opp_table in exynos3250.dtsi.
>>>>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0.
>>>>> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU.
>>>>
>>>> Ok
>>>>
>>>>>
>>>>>>
>>>>>>> +			compatible = "operating-points-v2";
>>>>>>> +			opp-shared;
>>>>>>> +
>>>>>>> +			opp00 {
>>>>>>> +				opp-hz = /bits/ 64 <50000000>;
>>>>>>> +				opp-microvolt = <800000>;
>>>>>>> +			};
>>>>>>> +			opp01 {
>>>>>>> +				opp-hz = /bits/ 64 <100000000>;
>>>>>>> +				opp-microvolt = <800000>;
>>>>>>> +			};
>>>>>>> +			opp02 {
>>>>>>> +				opp-hz = /bits/ 64 <134000000>;
>>>>>>> +				opp-microvolt = <800000>;
>>>>>>
>>>>>> Why 134, not 133 MHz?
>>>>>
>>>>> When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz.
>>>>> I add following test result on exynos3250-rinato board.
>>>>>
>>>>> Case1.
>>>>> When I use the 134 MHz, the source clock is changed to 133MHz
>>>>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334)
>>>>>
>>>>> Case2.
>>>>> When I use the 133 MHz, the source clock is changed to 100MHz
>>>>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000)
>>>>
>>>> Now I remember that issue. You could use here directly 133333334 but
>>>> that also would look a little bit weird... so 134 is ok for me. Could
>>>> just add a comment that desired frequency is actually "133 MHz"?
>>>
>>> Do you prefer among following example?
>>>
>>> Example1.
>>> 	opp02 {
>>> 		/* The desired frequency is 133MHz because
>>> 		 * clock change has the dependency on clock driver.
>>> 		 * When set rate as 134MHz, the clock driver would
>>> 		 * change the 133MHz actually instead of 134MHz.
>>> 		 */
>>> 		opp-hz = /bits/ 64 <134000000>;
>>> 		opp-microvolt = <800000>;
>>> 	};
>>>
>>> Example2.
>>> 	opp02 {
>>> 		opp-hz = /bits/ 64 <133333334>;
>>> 		opp-microvolt = <800000>;
>>> 	};
>>
>> I would prefer the second one (133333334) but I don't have strong
>> feelings about it.
> 
> If you ok, I want to maintain the original approach as following:
> 
> 	opp02 {
> 		opp-hz = /bits/ 64 <134000000>;
> 		opp-microvolt = <800000>;
> 	};

OK

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250
  2015-12-10  2:09   ` Krzysztof Kozlowski
@ 2015-12-10  2:30     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  2:30 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 11:09, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus nodes using VDD_INT for Exynos3250 SoC.
>> Exynos3250 has following AXI buses to translate data between
>> DRAM and sub-blocks.
>>
>> Following list specifies the detailed relation between DRAM and sub-blocks:
>> - ACLK400 clock for MCUISP
>> - ACLK266 clock for ISP
>> - ACLK200 clock for FSYS
>> - ACLK160 clock for LCD0
>> - ACLK100 clock for PERIL
>> - GDL clock for LEFTBUS
>> - GDR clock for RIGHTBUS
>> - SCLK_MFC clock for MFC
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 160 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
>> index 7214c5e42150..46dee1951ec1 100644
>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -721,6 +721,166 @@
>>  				opp-microvolt = <875000>;
>>  			};
>>  		};
>> +
>> +		bus_leftbus: bus_leftbus {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_GDL>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_leftbus_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_rightbus: bus_rightbus {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_GDR>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_leftbus_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_lcd0: bus_lcd0 {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_ACLK_160>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_leftbus_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_fsys: bus_fsys {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_ACLK_200>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_leftbus_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_mcuisp: bus_mcuisp {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_mcuisp_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_isp: bus_isp {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_ACLK_266>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_isp_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_peril: bus_peril {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_DIV_ACLK_100>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_peril_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_mfc: bus_mfc {
>> +			compatible = "samsung,exynos-bus";
>> +			clocks = <&cmu CLK_SCLK_MFC>;
>> +			clock-names = "bus";
>> +			operating-points-v2 = <&bus_leftbus_opp_table>;
>> +			status = "disabled";
>> +		};
>> +
>> +		bus_leftbus_opp_table: opp_table2 {
>> +			compatible = "operating-points-v2";
>> +			opp-shared;
>> +
>> +			opp00 {
>> +				opp-hz = /bits/ 64 <50000000>;
>> +				opp-microvolt = <900000>;
>> +			};
>> +			opp01 {
>> +				opp-hz = /bits/ 64 <80000000>;
>> +				opp-microvolt = <900000>;
>> +			};
>> +			opp02 {
>> +				opp-hz = /bits/ 64 <100000000>;
>> +				opp-microvolt = <1000000>;
>> +			};
>> +			opp03 {
>> +				opp-hz = /bits/ 64 <134000000>;
>> +				opp-microvolt = <1000000>;
>> +			};
>> +			opp04 {
>> +				opp-hz = /bits/ 64 <200000000>;
>> +				opp-microvolt = <1000000>;
>> +			};
>> +		};
>> +
>> +		bus_mcuisp_opp_table: opp_table3 {
>> +			compatible = "operating-points-v2";
>> +			opp-shared;
>> +
>> +			opp00 {
>> +				opp-hz = /bits/ 64 <50000000>;
>> +				opp-microvolt = <900000>;
> 
> The voltages for all these INT-block tables have exactly the same value
> which of course makes sense because this is the same regulator. However
> the opp-microvolt property is an optional property. Do you have to
> provide it in each OPP?

I couldn't check whether opp-microvolt property is optional or not.
You're right. Except for the opp-microvolt property of parent device,
I'll remove it on dts file.

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
  2015-12-09  4:08 ` [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi
@ 2015-12-10  3:17   ` Krzysztof Kozlowski
  2015-12-10  4:21     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  3:17 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.

s/noes/nodes/

> Exynos4x12 has the following AXI buses to translate data
> between DRAM and DMC/ACP/C2C.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index b77dac61ffb5..3bcf0939755e 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -282,6 +282,78 @@
>  		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
>  		#iommu-cells = <0>;
>  	};
> +
> +	bus_dmc: bus_dmc {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_DMC>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_dmc_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_acp: bus_acp {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_ACP>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_acp_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_c2c: bus_c2c {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_C2C>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_dmc_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_dmc_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <134000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp02 {
> +			opp-hz = /bits/ 64 <160000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp03 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <950000>;

The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
@ 2015-12-10  4:14       ` Anand Moon
  0 siblings, 0 replies; 72+ messages in thread
From: Anand Moon @ 2015-12-10  4:14 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King, Tobias Jakobi,
	Linux Kernel, Linux PM list, linux-samsung-soc, devicetree

Hi Chanwoo Choi,

On 10 December 2015 at 05:42, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> Hi Anand,
>
> First of all, thanks for trying to test this series.
>
> On 2015년 12월 10일 04:05, Anand Moon wrote:
>> Hi Chanwoo Choi,
>>
>> On 9 December 2015 at 09:37, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patch-set includes the two features as following. The generic exynos bus
>>> frequency driver is able to support almost Exynos SoCs for bus frequency
>>> scaling. And the new passive governor is able to make the dependency on
>>> between devices for frequency/voltage scaling. I had posted the patch-set[1]
>>> with the similiar concept. This is is revised version for exynos bus frequency.
>>> - Generic exynos bus frequency driver
>>> - New passive governor of DEVFREQ framework
>>>
>>> Depends on:
>>> - This patch-set is based on devfreq.git[2].
>>> [1] https://lkml.org/lkml/2015/1/7/872
>>>    : [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
>>> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch: for-rafael)
>>>
>>> Changes from v1:
>>> (https://lkml.org/lkml/2015/11/26/260)
>>> - Check whether the instance of regulator is NULL or not
>>>   when executing regulator_disable() because of only parent
>>>   devfreq device has the regulator instance. After fixing it,
>>>   the wake-up from suspend state is well working. (patch1)
>>> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>>>   after calling devm_clk_get() (on patch1)
>>> - Update the documentation to remove the description about
>>>   DEVFREQ-EVENT subsystem (on patch2)
>>> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
>>> - Modify the detailed correlation of buses for Exynos3250
>>>   on documentation (patch2)
>>> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
>>> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
>>> - Add the PPMU node for exynos4412-odroidu3
>>> - Add the support of bus frequency for exynos4412-odroidu3
>>>
>>> Detailed descirption for patch-set:
>>> 1. Add generic exynos bus frequency driver
>>> : This patch-set adds the generic exynos bus frequency driver for AXI bus
>>> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
>>> architecture for bus between DRAM and sub-blocks in SoC.
>>>
>>>  There are the different buses according to Exynos SoC because Exynos SoC
>>> has the differnt sub-blocks and bus speed. In spite of this difference
>>> among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
>>> unique data of each bus in the devicetree file.
>>>
>>>  In devicetree, each bus node has a bus clock, regulator, operation-point
>>> and devfreq-event devices which measure the utilization of each bus block.
>>>
>>> For example,
>>> - The bus of DMC block in exynos3250.dtsi are listed below:
>>>
>>>         bus_dmc: bus_dmc {
>>>                 compatible = "samsung,exynos-bus";
>>>                 clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>                 clock-names = "bus";
>>>                 operating-points-v2 = <&bus_dmc_opp_table>;
>>>                 status = "disabled";
>>>         };
>>>
>>>         bus_dmc_opp_table: opp_table0 {
>>>                 compatible = "operating-points-v2";
>>>                 opp-shared;
>>>
>>>                 opp00 {
>>>                         opp-hz = /bits/ 64 <50000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp01 {
>>>                         opp-hz = /bits/ 64 <100000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp02 {
>>>                         opp-hz = /bits/ 64 <134000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp03 {
>>>                         opp-hz = /bits/ 64 <200000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp04 {
>>>                         opp-hz = /bits/ 64 <400000000>;
>>>                         opp-microvolt = <875000>;
>>>                 };
>>>         };
>>>
>>> - Usage case to handle the frequency and voltage of bus on runtime
>>>   in exynos3250-rinato.dts are listed below:
>>>
>>>         &bus_dmc {
>>>                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>>>                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
>>>                 status = "okay";
>>>         };
>>>
>>> 2. Add new passive governor of DEVFREQ framework (patch5-patch7)
>>> : This patch-set add the new passive governor for DEVFREQ framework.
>>> The existing governors (ondemand, performance and so on) are used for DVFS
>>> (Dynamic Voltage and Frequency Scaling) drivers. The existing governors
>>> are independently used for specific device driver which don't give the
>>> influence to other device drviers and also don't receive the effect from
>>> other device drivers.
>>>
>>>  The passive governor depends on operation of parent driver with existing
>>> governors(ondemand, performance and so on) extremely and is not able to
>>> decide the new frequency by oneself. According to the decided new frequency
>>> of parent driver with governor, the passive governor uses it to decide
>>> the appropriate frequency for own device driver. The passive governor
>>> must need the following information from device tree:
>>>
>>> For exameple,
>>>  There are one more bus device drivers in Exynos3250 which need to
>>> change their source clock according to their utilization on runtime.
>>> But, they share the same power line (e.g., regulator). So, LEFTBUS bus
>>> driver is operated as parent with ondemand governor and then the rest
>>> device driver with passive governor.
>>>
>>>  The buses of Internal block in exynos3250.dtsi are listed below:
>>> When LEFTBUS bus driver (parent) changes the bus frequency with
>>> ondemand governor on runtime, the rest bus devices which sharing
>>> the same power line (VDD_INT) will change the each bus frequency
>>> according to the decision of LEFTBUS bus driver (parent).
>>>
>>> - INT (Internal) block
>>>         : VDD_INT |--- LEFTBUS
>>>                   |--- PERIL
>>>                   |--- MFC
>>>                   |--- G3D
>>>                   |--- RIGHTBUS
>>>                   |--- FSYS
>>>                   |--- LCD0
>>>                   |--- PERIR
>>>                   |--- ISP
>>>                   |--- CAM
>>>
>>> - The buss of INT block in exynos3250.dtsi are listed below:
>>>         bus_leftbus: bus_leftbus {
>>>                 compatible = "samsung,exynos-bus";
>>>                 clocks = <&cmu CLK_DIV_GDL>;
>>>                 clock-names = "bus";
>>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>>                 status = "disabled";
>>>         };
>>>
>>>         bus_rightbus: bus_rightbus {
>>>                 compatible = "samsung,exynos-bus";
>>>                 clocks = <&cmu CLK_DIV_GDR>;
>>>                 clock-names = "bus";
>>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>>                 status = "disabled";
>>>         };
>>>
>>>         (Omit the rest bus dt node)
>>>
>>> - Usage case to handle the frequency and voltage of bus on runtime
>>>   in exynos3250-rinato.dts are listed below:
>>>         /* Parent bus device of VDD_INT */
>>>         &bus_leftbus {
>>>                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>>>                 vdd-supply = <&buck3_reg>;
>>>                 status = "okay";
>>>         };
>>>
>>>         /* Passive bus device depend on LEFTBUS bus. */
>>>         &bus_rightbus {
>>>                 devfreq = <&bus_leftbus>; /* 'devfreq' property indicates
>>>                                              the phandle of parent device. */
>>>                 status = "okay";
>>>         };
>>>
>>>         (Omit the rest bus dt node)
>>>
>>> Chanwoo Choi (19):
>>>   PM / devfreq: exynos: Add generic exynos bus frequency driver
>>>   PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
>>>   ARM: dts: Add DMC bus node for Exynos3250
>>>   ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
>>>   PM / devfreq: Add new passive governor
>>>   PM / devfreq: Add devfreq_get_devfreq_by_phandle()
>>>   PM / devfreq: Show the related information according to governor type
>>>   PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
>>>   PM / devfreq: exynos: Update documentation for bus devices using passive governor
>>>   PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
>>>   PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
>>>   ARM: dts: Add bus nodes using VDD_INT for Exynos3250
>>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
>>>   ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
>>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
>>>   ARM: dts: Add PPMU node for exynos4412-odroidu3
>>>   ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
>>>   ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
>>>   ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
>>>
>>>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
>>>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>>>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>>>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>>>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>>>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>>>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>>>  drivers/devfreq/Kconfig                            |   37 +-
>>>  drivers/devfreq/Makefile                           |    2 +
>>>  drivers/devfreq/devfreq.c                          |  120 ++-
>>>  drivers/devfreq/exynos/Makefile                    |    3 +-
>>>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>>>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>>>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>>>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>>>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>>>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>>>  drivers/devfreq/governor.h                         |    7 +
>>>  drivers/devfreq/governor_passive.c                 |  109 ++
>>>  drivers/devfreq/governor_performance.c             |    1 +
>>>  drivers/devfreq/governor_powersave.c               |    1 +
>>>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>>>  drivers/devfreq/governor_userspace.c               |    1 +
>>>  include/linux/devfreq.h                            |   28 +
>>>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>>>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>>>  create mode 100644 drivers/devfreq/governor_passive.c
>>>
>>> --
>>> 1.9.1
>>>
>>
>> I could not get this series to work with my Odroid U3.
>>
>> [    4.602768] input: gpio_keys as /devices/platform/gpio_keys/input/input0
>> [    4.605527] devfreq bus_leftbus: Couldn't update frequency
>> transition information.
>> [    4.607319] devfreq bus_dmc: Couldn't update frequency transition
>> information.
>> [    4.625096] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
>
> This log indicates the problem of 'trats_stat' sysfs entry of devfreq framework
> during kernel booting. But, this log don't affect the behavior of bus frequency
> on Odroid-U3.
>
> After completing kernel and platform booting, you can check the operation
> of Bus frequency with follwoing sysfs entry:
>
> root@localhost:~# ls -al /sys/class/devfreq
> total 0
> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_acp -> ../../devices/platform/bus_acp/devfreq/bus_acp
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_c2c -> ../../devices/platform/bus_c2c/devfreq/bus_c2c
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_dmc -> ../../devices/platform/bus_dmc/devfreq/bus_dmc
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus
>
> root@localhost:~# cat /sys/class/devfreq/bus_leftbus/trans_stat
>      From  :   To
>            : 100000000 134000000 160000000 200000000   time(ms)
>   100000000:         0         0         0        24      2020
>   134000000:         0         0         0        10      1190
>   160000000:         0         0         0         0         0
> * 200000000:        24        10         0         0    118160
> Total transition : 68
>
> Also, when changing the frequency of each bus, exynos-bus.c show
> the debug message. If you need more detailed information,
> you could check this log message.
>
> Regards,
> Chanwoo Choi

Thanks for you input. It seem to be working I have see the counter increment.
Sorry for the noise.

root@odroidu3:~# cat /sys/class/devfreq/bus_dmc/trans_stat
     From  :   To
           : 100000000 134000000 160000000 200000000 400000000   time(ms)
  100000000:         0         0         0         0         2       560
  134000000:         0         0         0         0         1       190
  160000000:         0         0         0         0         0         0
  200000000:         0         0         0         0         2       310
* 400000000:         2         1         0         2         0    332400
Total transition : 10
root@odroidu3:~# cat /sys/class/devfreq/bus_rightbus/trans_stat
Not Supported.
root@odroidu3:~#

Tested on Odroid U3
Tested-by: Anand Moon <linux.amoon@gmail.com>

-Anand Moon

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
@ 2015-12-10  4:14       ` Anand Moon
  0 siblings, 0 replies; 72+ messages in thread
From: Anand Moon @ 2015-12-10  4:14 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ, Krzysztof Kozłowski,
	Kukjin Kim, Kyungmin Park, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King, Tobias Jakobi,
	Linux Kernel, Linux PM list,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, devicetree

Hi Chanwoo Choi,

On 10 December 2015 at 05:42, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> Hi Anand,
>
> First of all, thanks for trying to test this series.
>
> On 2015년 12월 10일 04:05, Anand Moon wrote:
>> Hi Chanwoo Choi,
>>
>> On 9 December 2015 at 09:37, Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>>> This patch-set includes the two features as following. The generic exynos bus
>>> frequency driver is able to support almost Exynos SoCs for bus frequency
>>> scaling. And the new passive governor is able to make the dependency on
>>> between devices for frequency/voltage scaling. I had posted the patch-set[1]
>>> with the similiar concept. This is is revised version for exynos bus frequency.
>>> - Generic exynos bus frequency driver
>>> - New passive governor of DEVFREQ framework
>>>
>>> Depends on:
>>> - This patch-set is based on devfreq.git[2].
>>> [1] https://lkml.org/lkml/2015/1/7/872
>>>    : [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
>>> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch: for-rafael)
>>>
>>> Changes from v1:
>>> (https://lkml.org/lkml/2015/11/26/260)
>>> - Check whether the instance of regulator is NULL or not
>>>   when executing regulator_disable() because of only parent
>>>   devfreq device has the regulator instance. After fixing it,
>>>   the wake-up from suspend state is well working. (patch1)
>>> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>>>   after calling devm_clk_get() (on patch1)
>>> - Update the documentation to remove the description about
>>>   DEVFREQ-EVENT subsystem (on patch2)
>>> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
>>> - Modify the detailed correlation of buses for Exynos3250
>>>   on documentation (patch2)
>>> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
>>> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
>>> - Add the PPMU node for exynos4412-odroidu3
>>> - Add the support of bus frequency for exynos4412-odroidu3
>>>
>>> Detailed descirption for patch-set:
>>> 1. Add generic exynos bus frequency driver
>>> : This patch-set adds the generic exynos bus frequency driver for AXI bus
>>> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
>>> architecture for bus between DRAM and sub-blocks in SoC.
>>>
>>>  There are the different buses according to Exynos SoC because Exynos SoC
>>> has the differnt sub-blocks and bus speed. In spite of this difference
>>> among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
>>> unique data of each bus in the devicetree file.
>>>
>>>  In devicetree, each bus node has a bus clock, regulator, operation-point
>>> and devfreq-event devices which measure the utilization of each bus block.
>>>
>>> For example,
>>> - The bus of DMC block in exynos3250.dtsi are listed below:
>>>
>>>         bus_dmc: bus_dmc {
>>>                 compatible = "samsung,exynos-bus";
>>>                 clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>                 clock-names = "bus";
>>>                 operating-points-v2 = <&bus_dmc_opp_table>;
>>>                 status = "disabled";
>>>         };
>>>
>>>         bus_dmc_opp_table: opp_table0 {
>>>                 compatible = "operating-points-v2";
>>>                 opp-shared;
>>>
>>>                 opp00 {
>>>                         opp-hz = /bits/ 64 <50000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp01 {
>>>                         opp-hz = /bits/ 64 <100000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp02 {
>>>                         opp-hz = /bits/ 64 <134000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp03 {
>>>                         opp-hz = /bits/ 64 <200000000>;
>>>                         opp-microvolt = <800000>;
>>>                 };
>>>                 opp04 {
>>>                         opp-hz = /bits/ 64 <400000000>;
>>>                         opp-microvolt = <875000>;
>>>                 };
>>>         };
>>>
>>> - Usage case to handle the frequency and voltage of bus on runtime
>>>   in exynos3250-rinato.dts are listed below:
>>>
>>>         &bus_dmc {
>>>                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>>>                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
>>>                 status = "okay";
>>>         };
>>>
>>> 2. Add new passive governor of DEVFREQ framework (patch5-patch7)
>>> : This patch-set add the new passive governor for DEVFREQ framework.
>>> The existing governors (ondemand, performance and so on) are used for DVFS
>>> (Dynamic Voltage and Frequency Scaling) drivers. The existing governors
>>> are independently used for specific device driver which don't give the
>>> influence to other device drviers and also don't receive the effect from
>>> other device drivers.
>>>
>>>  The passive governor depends on operation of parent driver with existing
>>> governors(ondemand, performance and so on) extremely and is not able to
>>> decide the new frequency by oneself. According to the decided new frequency
>>> of parent driver with governor, the passive governor uses it to decide
>>> the appropriate frequency for own device driver. The passive governor
>>> must need the following information from device tree:
>>>
>>> For exameple,
>>>  There are one more bus device drivers in Exynos3250 which need to
>>> change their source clock according to their utilization on runtime.
>>> But, they share the same power line (e.g., regulator). So, LEFTBUS bus
>>> driver is operated as parent with ondemand governor and then the rest
>>> device driver with passive governor.
>>>
>>>  The buses of Internal block in exynos3250.dtsi are listed below:
>>> When LEFTBUS bus driver (parent) changes the bus frequency with
>>> ondemand governor on runtime, the rest bus devices which sharing
>>> the same power line (VDD_INT) will change the each bus frequency
>>> according to the decision of LEFTBUS bus driver (parent).
>>>
>>> - INT (Internal) block
>>>         : VDD_INT |--- LEFTBUS
>>>                   |--- PERIL
>>>                   |--- MFC
>>>                   |--- G3D
>>>                   |--- RIGHTBUS
>>>                   |--- FSYS
>>>                   |--- LCD0
>>>                   |--- PERIR
>>>                   |--- ISP
>>>                   |--- CAM
>>>
>>> - The buss of INT block in exynos3250.dtsi are listed below:
>>>         bus_leftbus: bus_leftbus {
>>>                 compatible = "samsung,exynos-bus";
>>>                 clocks = <&cmu CLK_DIV_GDL>;
>>>                 clock-names = "bus";
>>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>>                 status = "disabled";
>>>         };
>>>
>>>         bus_rightbus: bus_rightbus {
>>>                 compatible = "samsung,exynos-bus";
>>>                 clocks = <&cmu CLK_DIV_GDR>;
>>>                 clock-names = "bus";
>>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>>                 status = "disabled";
>>>         };
>>>
>>>         (Omit the rest bus dt node)
>>>
>>> - Usage case to handle the frequency and voltage of bus on runtime
>>>   in exynos3250-rinato.dts are listed below:
>>>         /* Parent bus device of VDD_INT */
>>>         &bus_leftbus {
>>>                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>>>                 vdd-supply = <&buck3_reg>;
>>>                 status = "okay";
>>>         };
>>>
>>>         /* Passive bus device depend on LEFTBUS bus. */
>>>         &bus_rightbus {
>>>                 devfreq = <&bus_leftbus>; /* 'devfreq' property indicates
>>>                                              the phandle of parent device. */
>>>                 status = "okay";
>>>         };
>>>
>>>         (Omit the rest bus dt node)
>>>
>>> Chanwoo Choi (19):
>>>   PM / devfreq: exynos: Add generic exynos bus frequency driver
>>>   PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
>>>   ARM: dts: Add DMC bus node for Exynos3250
>>>   ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
>>>   PM / devfreq: Add new passive governor
>>>   PM / devfreq: Add devfreq_get_devfreq_by_phandle()
>>>   PM / devfreq: Show the related information according to governor type
>>>   PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
>>>   PM / devfreq: exynos: Update documentation for bus devices using passive governor
>>>   PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
>>>   PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
>>>   ARM: dts: Add bus nodes using VDD_INT for Exynos3250
>>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
>>>   ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
>>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
>>>   ARM: dts: Add PPMU node for exynos4412-odroidu3
>>>   ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
>>>   ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
>>>   ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
>>>
>>>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
>>>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>>>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>>>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>>>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>>>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>>>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>>>  drivers/devfreq/Kconfig                            |   37 +-
>>>  drivers/devfreq/Makefile                           |    2 +
>>>  drivers/devfreq/devfreq.c                          |  120 ++-
>>>  drivers/devfreq/exynos/Makefile                    |    3 +-
>>>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>>>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>>>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>>>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>>>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>>>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>>>  drivers/devfreq/governor.h                         |    7 +
>>>  drivers/devfreq/governor_passive.c                 |  109 ++
>>>  drivers/devfreq/governor_performance.c             |    1 +
>>>  drivers/devfreq/governor_powersave.c               |    1 +
>>>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>>>  drivers/devfreq/governor_userspace.c               |    1 +
>>>  include/linux/devfreq.h                            |   28 +
>>>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>>>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>>>  create mode 100644 drivers/devfreq/governor_passive.c
>>>
>>> --
>>> 1.9.1
>>>
>>
>> I could not get this series to work with my Odroid U3.
>>
>> [    4.602768] input: gpio_keys as /devices/platform/gpio_keys/input/input0
>> [    4.605527] devfreq bus_leftbus: Couldn't update frequency
>> transition information.
>> [    4.607319] devfreq bus_dmc: Couldn't update frequency transition
>> information.
>> [    4.625096] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
>
> This log indicates the problem of 'trats_stat' sysfs entry of devfreq framework
> during kernel booting. But, this log don't affect the behavior of bus frequency
> on Odroid-U3.
>
> After completing kernel and platform booting, you can check the operation
> of Bus frequency with follwoing sysfs entry:
>
> root@localhost:~# ls -al /sys/class/devfreq
> total 0
> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_acp -> ../../devices/platform/bus_acp/devfreq/bus_acp
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_c2c -> ../../devices/platform/bus_c2c/devfreq/bus_c2c
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_dmc -> ../../devices/platform/bus_dmc/devfreq/bus_dmc
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus
>
> root@localhost:~# cat /sys/class/devfreq/bus_leftbus/trans_stat
>      From  :   To
>            : 100000000 134000000 160000000 200000000   time(ms)
>   100000000:         0         0         0        24      2020
>   134000000:         0         0         0        10      1190
>   160000000:         0         0         0         0         0
> * 200000000:        24        10         0         0    118160
> Total transition : 68
>
> Also, when changing the frequency of each bus, exynos-bus.c show
> the debug message. If you need more detailed information,
> you could check this log message.
>
> Regards,
> Chanwoo Choi

Thanks for you input. It seem to be working I have see the counter increment.
Sorry for the noise.

root@odroidu3:~# cat /sys/class/devfreq/bus_dmc/trans_stat
     From  :   To
           : 100000000 134000000 160000000 200000000 400000000   time(ms)
  100000000:         0         0         0         0         2       560
  134000000:         0         0         0         0         1       190
  160000000:         0         0         0         0         0         0
  200000000:         0         0         0         0         2       310
* 400000000:         2         1         0         2         0    332400
Total transition : 10
root@odroidu3:~# cat /sys/class/devfreq/bus_rightbus/trans_stat
Not Supported.
root@odroidu3:~#

Tested on Odroid U3
Tested-by: Anand Moon <linux.amoon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

-Anand Moon
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^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor
  2015-12-10  4:14       ` Anand Moon
  (?)
@ 2015-12-10  4:20       ` Chanwoo Choi
  -1 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  4:20 UTC (permalink / raw)
  To: Anand Moon
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King, Tobias Jakobi,
	Linux Kernel, Linux PM list, linux-samsung-soc, devicetree

Hi Anand,

On 2015년 12월 10일 13:14, Anand Moon wrote:
> Hi Chanwoo Choi,
> 
> On 10 December 2015 at 05:42, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> Hi Anand,
>>
>> First of all, thanks for trying to test this series.
>>
>> On 2015년 12월 10일 04:05, Anand Moon wrote:
>>> Hi Chanwoo Choi,
>>>
>>> On 9 December 2015 at 09:37, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>>> This patch-set includes the two features as following. The generic exynos bus
>>>> frequency driver is able to support almost Exynos SoCs for bus frequency
>>>> scaling. And the new passive governor is able to make the dependency on
>>>> between devices for frequency/voltage scaling. I had posted the patch-set[1]
>>>> with the similiar concept. This is is revised version for exynos bus frequency.
>>>> - Generic exynos bus frequency driver
>>>> - New passive governor of DEVFREQ framework
>>>>
>>>> Depends on:
>>>> - This patch-set is based on devfreq.git[2].
>>>> [1] https://lkml.org/lkml/2015/1/7/872
>>>>    : [PATCHv3 0/8] devfreq: Add generic exynos memory-bus frequency driver
>>>> [2] https://git.kernel.org/cgit/linux/kernel/git/mzx/devfreq.git/ (branch: for-rafael)
>>>>
>>>> Changes from v1:
>>>> (https://lkml.org/lkml/2015/11/26/260)
>>>> - Check whether the instance of regulator is NULL or not
>>>>   when executing regulator_disable() because of only parent
>>>>   devfreq device has the regulator instance. After fixing it,
>>>>   the wake-up from suspend state is well working. (patch1)
>>>> - Fix bug which checks 'bus-clk' instead of 'bus->regulator'
>>>>   after calling devm_clk_get() (on patch1)
>>>> - Update the documentation to remove the description about
>>>>   DEVFREQ-EVENT subsystem (on patch2)
>>>> - Add the full name of DMC (Dynamic Memory Controller) (on patch2)
>>>> - Modify the detailed correlation of buses for Exynos3250
>>>>   on documentation (patch2)
>>>> - Add the MFC bus node for Exynos3250 (on patch11, patch12)
>>>> - Fix the duplicate frequency of bus_display on Exynos4x12.dtsi
>>>> - Add the PPMU node for exynos4412-odroidu3
>>>> - Add the support of bus frequency for exynos4412-odroidu3
>>>>
>>>> Detailed descirption for patch-set:
>>>> 1. Add generic exynos bus frequency driver
>>>> : This patch-set adds the generic exynos bus frequency driver for AXI bus
>>>> of sub-blocks in exynos SoC. The Samsung Exynos SoC have the common
>>>> architecture for bus between DRAM and sub-blocks in SoC.
>>>>
>>>>  There are the different buses according to Exynos SoC because Exynos SoC
>>>> has the differnt sub-blocks and bus speed. In spite of this difference
>>>> among Exynos SoCs, this driver is able to support almost Exynos SoC by adding
>>>> unique data of each bus in the devicetree file.
>>>>
>>>>  In devicetree, each bus node has a bus clock, regulator, operation-point
>>>> and devfreq-event devices which measure the utilization of each bus block.
>>>>
>>>> For example,
>>>> - The bus of DMC block in exynos3250.dtsi are listed below:
>>>>
>>>>         bus_dmc: bus_dmc {
>>>>                 compatible = "samsung,exynos-bus";
>>>>                 clocks = <&cmu_dmc CLK_DIV_DMC>;
>>>>                 clock-names = "bus";
>>>>                 operating-points-v2 = <&bus_dmc_opp_table>;
>>>>                 status = "disabled";
>>>>         };
>>>>
>>>>         bus_dmc_opp_table: opp_table0 {
>>>>                 compatible = "operating-points-v2";
>>>>                 opp-shared;
>>>>
>>>>                 opp00 {
>>>>                         opp-hz = /bits/ 64 <50000000>;
>>>>                         opp-microvolt = <800000>;
>>>>                 };
>>>>                 opp01 {
>>>>                         opp-hz = /bits/ 64 <100000000>;
>>>>                         opp-microvolt = <800000>;
>>>>                 };
>>>>                 opp02 {
>>>>                         opp-hz = /bits/ 64 <134000000>;
>>>>                         opp-microvolt = <800000>;
>>>>                 };
>>>>                 opp03 {
>>>>                         opp-hz = /bits/ 64 <200000000>;
>>>>                         opp-microvolt = <800000>;
>>>>                 };
>>>>                 opp04 {
>>>>                         opp-hz = /bits/ 64 <400000000>;
>>>>                         opp-microvolt = <875000>;
>>>>                 };
>>>>         };
>>>>
>>>> - Usage case to handle the frequency and voltage of bus on runtime
>>>>   in exynos3250-rinato.dts are listed below:
>>>>
>>>>         &bus_dmc {
>>>>                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>>>>                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
>>>>                 status = "okay";
>>>>         };
>>>>
>>>> 2. Add new passive governor of DEVFREQ framework (patch5-patch7)
>>>> : This patch-set add the new passive governor for DEVFREQ framework.
>>>> The existing governors (ondemand, performance and so on) are used for DVFS
>>>> (Dynamic Voltage and Frequency Scaling) drivers. The existing governors
>>>> are independently used for specific device driver which don't give the
>>>> influence to other device drviers and also don't receive the effect from
>>>> other device drivers.
>>>>
>>>>  The passive governor depends on operation of parent driver with existing
>>>> governors(ondemand, performance and so on) extremely and is not able to
>>>> decide the new frequency by oneself. According to the decided new frequency
>>>> of parent driver with governor, the passive governor uses it to decide
>>>> the appropriate frequency for own device driver. The passive governor
>>>> must need the following information from device tree:
>>>>
>>>> For exameple,
>>>>  There are one more bus device drivers in Exynos3250 which need to
>>>> change their source clock according to their utilization on runtime.
>>>> But, they share the same power line (e.g., regulator). So, LEFTBUS bus
>>>> driver is operated as parent with ondemand governor and then the rest
>>>> device driver with passive governor.
>>>>
>>>>  The buses of Internal block in exynos3250.dtsi are listed below:
>>>> When LEFTBUS bus driver (parent) changes the bus frequency with
>>>> ondemand governor on runtime, the rest bus devices which sharing
>>>> the same power line (VDD_INT) will change the each bus frequency
>>>> according to the decision of LEFTBUS bus driver (parent).
>>>>
>>>> - INT (Internal) block
>>>>         : VDD_INT |--- LEFTBUS
>>>>                   |--- PERIL
>>>>                   |--- MFC
>>>>                   |--- G3D
>>>>                   |--- RIGHTBUS
>>>>                   |--- FSYS
>>>>                   |--- LCD0
>>>>                   |--- PERIR
>>>>                   |--- ISP
>>>>                   |--- CAM
>>>>
>>>> - The buss of INT block in exynos3250.dtsi are listed below:
>>>>         bus_leftbus: bus_leftbus {
>>>>                 compatible = "samsung,exynos-bus";
>>>>                 clocks = <&cmu CLK_DIV_GDL>;
>>>>                 clock-names = "bus";
>>>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>                 status = "disabled";
>>>>         };
>>>>
>>>>         bus_rightbus: bus_rightbus {
>>>>                 compatible = "samsung,exynos-bus";
>>>>                 clocks = <&cmu CLK_DIV_GDR>;
>>>>                 clock-names = "bus";
>>>>                 operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>                 status = "disabled";
>>>>         };
>>>>
>>>>         (Omit the rest bus dt node)
>>>>
>>>> - Usage case to handle the frequency and voltage of bus on runtime
>>>>   in exynos3250-rinato.dts are listed below:
>>>>         /* Parent bus device of VDD_INT */
>>>>         &bus_leftbus {
>>>>                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>>>>                 vdd-supply = <&buck3_reg>;
>>>>                 status = "okay";
>>>>         };
>>>>
>>>>         /* Passive bus device depend on LEFTBUS bus. */
>>>>         &bus_rightbus {
>>>>                 devfreq = <&bus_leftbus>; /* 'devfreq' property indicates
>>>>                                              the phandle of parent device. */
>>>>                 status = "okay";
>>>>         };
>>>>
>>>>         (Omit the rest bus dt node)
>>>>
>>>> Chanwoo Choi (19):
>>>>   PM / devfreq: exynos: Add generic exynos bus frequency driver
>>>>   PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver
>>>>   ARM: dts: Add DMC bus node for Exynos3250
>>>>   ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk
>>>>   PM / devfreq: Add new passive governor
>>>>   PM / devfreq: Add devfreq_get_devfreq_by_phandle()
>>>>   PM / devfreq: Show the related information according to governor type
>>>>   PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor
>>>>   PM / devfreq: exynos: Update documentation for bus devices using passive governor
>>>>   PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line
>>>>   PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver
>>>>   ARM: dts: Add bus nodes using VDD_INT for Exynos3250
>>>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
>>>>   ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
>>>>   ARM: dts: Add bus nodes using VDD_MIF for Exynos4210
>>>>   ARM: dts: Add PPMU node for exynos4412-odroidu3
>>>>   ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
>>>>   ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
>>>>   ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
>>>>
>>>>  .../devicetree/bindings/devfreq/exynos-bus.txt     |  383 +++++++
>>>>  arch/arm/boot/dts/exynos3250-monk.dts              |    6 +
>>>>  arch/arm/boot/dts/exynos3250-rinato.dts            |   47 +
>>>>  arch/arm/boot/dts/exynos3250.dtsi                  |  194 ++++
>>>>  arch/arm/boot/dts/exynos4210.dtsi                  |  172 ++++
>>>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi    |   93 +-
>>>>  arch/arm/boot/dts/exynos4412-trats2.dts            |   47 +
>>>>  arch/arm/boot/dts/exynos4x12.dtsi                  |  184 ++++
>>>>  drivers/devfreq/Kconfig                            |   37 +-
>>>>  drivers/devfreq/Makefile                           |    2 +
>>>>  drivers/devfreq/devfreq.c                          |  120 ++-
>>>>  drivers/devfreq/exynos/Makefile                    |    3 +-
>>>>  drivers/devfreq/exynos/exynos-bus.c                |  549 ++++++++++
>>>>  drivers/devfreq/exynos/exynos4_bus.c               | 1055 --------------------
>>>>  drivers/devfreq/exynos/exynos4_bus.h               |  110 --
>>>>  drivers/devfreq/exynos/exynos5_bus.c               |  431 --------
>>>>  drivers/devfreq/exynos/exynos_ppmu.c               |  119 ---
>>>>  drivers/devfreq/exynos/exynos_ppmu.h               |   86 --
>>>>  drivers/devfreq/governor.h                         |    7 +
>>>>  drivers/devfreq/governor_passive.c                 |  109 ++
>>>>  drivers/devfreq/governor_performance.c             |    1 +
>>>>  drivers/devfreq/governor_powersave.c               |    1 +
>>>>  drivers/devfreq/governor_simpleondemand.c          |    1 +
>>>>  drivers/devfreq/governor_userspace.c               |    1 +
>>>>  include/linux/devfreq.h                            |   28 +
>>>>  25 files changed, 1958 insertions(+), 1828 deletions(-)
>>>>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>>  create mode 100644 drivers/devfreq/exynos/exynos-bus.c
>>>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.c
>>>>  delete mode 100644 drivers/devfreq/exynos/exynos4_bus.h
>>>>  delete mode 100644 drivers/devfreq/exynos/exynos5_bus.c
>>>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.c
>>>>  delete mode 100644 drivers/devfreq/exynos/exynos_ppmu.h
>>>>  create mode 100644 drivers/devfreq/governor_passive.c
>>>>
>>>> --
>>>> 1.9.1
>>>>
>>>
>>> I could not get this series to work with my Odroid U3.
>>>
>>> [    4.602768] input: gpio_keys as /devices/platform/gpio_keys/input/input0
>>> [    4.605527] devfreq bus_leftbus: Couldn't update frequency
>>> transition information.
>>> [    4.607319] devfreq bus_dmc: Couldn't update frequency transition
>>> information.
>>> [    4.625096] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
>>
>> This log indicates the problem of 'trats_stat' sysfs entry of devfreq framework
>> during kernel booting. But, this log don't affect the behavior of bus frequency
>> on Odroid-U3.
>>
>> After completing kernel and platform booting, you can check the operation
>> of Bus frequency with follwoing sysfs entry:
>>
>> root@localhost:~# ls -al /sys/class/devfreq
>> total 0
>> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
>> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_acp -> ../../devices/platform/bus_acp/devfreq/bus_acp
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_c2c -> ../../devices/platform/bus_c2c/devfreq/bus_c2c
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_dmc -> ../../devices/platform/bus_dmc/devfreq/bus_dmc
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus
>>
>> root@localhost:~# cat /sys/class/devfreq/bus_leftbus/trans_stat
>>      From  :   To
>>            : 100000000 134000000 160000000 200000000   time(ms)
>>   100000000:         0         0         0        24      2020
>>   134000000:         0         0         0        10      1190
>>   160000000:         0         0         0         0         0
>> * 200000000:        24        10         0         0    118160
>> Total transition : 68
>>
>> Also, when changing the frequency of each bus, exynos-bus.c show
>> the debug message. If you need more detailed information,
>> you could check this log message.
>>
>> Regards,
>> Chanwoo Choi
> 
> Thanks for you input. It seem to be working I have see the counter increment.
> Sorry for the noise.

No problem.

> 
> root@odroidu3:~# cat /sys/class/devfreq/bus_dmc/trans_stat
>      From  :   To
>            : 100000000 134000000 160000000 200000000 400000000   time(ms)
>   100000000:         0         0         0         0         2       560
>   134000000:         0         0         0         0         1       190
>   160000000:         0         0         0         0         0         0
>   200000000:         0         0         0         0         2       310
> * 400000000:         2         1         0         2         0    332400
> Total transition : 10
> root@odroidu3:~# cat /sys/class/devfreq/bus_rightbus/trans_stat
> Not Supported.
> root@odroidu3:~#
> 
> Tested on Odroid U3
> Tested-by: Anand Moon <linux.amoon@gmail.com>

Thanks for your test.

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
  2015-12-10  3:17   ` Krzysztof Kozlowski
@ 2015-12-10  4:21     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  4:21 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 12:17, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
> 
> s/noes/nodes/

OK.

> 
>> Exynos4x12 has the following AXI buses to translate data
>> between DRAM and DMC/ACP/C2C.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 72 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>> index b77dac61ffb5..3bcf0939755e 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -282,6 +282,78 @@
>>  		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
>>  		#iommu-cells = <0>;
>>  	};
>> +
>> +	bus_dmc: bus_dmc {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_DMC>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_acp: bus_acp {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_ACP>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_acp_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_c2c: bus_c2c {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_C2C>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_dmc_opp_table: opp_table1 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <134000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp02 {
>> +			opp-hz = /bits/ 64 <160000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp03 {
>> +			opp-hz = /bits/ 64 <200000000>;
>> +			opp-microvolt = <950000>;
> 
> The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?

There is no special reason.
I'll change it (200MHz -> 267MHz).

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-09  4:08 ` [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT " Chanwoo Choi
@ 2015-12-10  5:57   ` Krzysztof Kozlowski
  2015-12-10  6:08     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  5:57 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
> Exynos4x12 has the following AXI buses to translate data between
> DRAM and sub-blocks.
> 
> Following list specifies the detailed relation between DRAM and sub-blocks:
> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock for CAM/TV/LCD
> : The minimum clock of ACLK160 should be over 160MHz.
>   When drop the clock under 160MHz, show the broken image.
> - ACLK133 clock for FSYS
> - GDL clock for LEFTBUS
> - GDR clock for RIGHTBUS
> - SCLK_MFC clock for MFC
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 112 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index 3bcf0939755e..8bc4aee156b5 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -354,6 +354,118 @@
>  			opp-microvolt = <950000>;
>  		};
>  	};
> +
> +	bus_leftbus: bus_leftbus {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_GDL>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_rightbus: bus_rightbus {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_GDR>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};

These two nodes are symmetrical. The MFC below and other buses in other
DTS share opps. How about changing the binding so multiple clocks could
be specified at once ("bus0", "bus1")? I think there is no need for a
bus device for each clock.

Best regards,
Krzysztof

> +
> +	bus_display: bus_display {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_ACLK160>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_display_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_fsys: bus_fsys {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_ACLK133>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_fsys_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_peri: bus_peri {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_ACLK100>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_peri_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_mfc: bus_mfc {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_SCLK_MFC>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_leftbus_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_leftbus_opp_table: opp_table3 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <134000000>;
> +			opp-microvolt = <925000>;
> +		};
> +		opp02 {
> +			opp-hz = /bits/ 64 <160000000>;
> +			opp-microvolt = <950000>;
> +		};
> +		opp03 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <1000000>;
> +		};
> +	};
> +
> +	bus_display_opp_table: opp_table4 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <160000000>;
> +			opp-microvolt = <950000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <1000000>;
> +		};
> +	};
> +
> +	bus_fsys_opp_table: opp_table5 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <134000000>;
> +			opp-microvolt = <925000>;
> +		};
> +	};
> +
> +	bus_peri_opp_table: opp_table6 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <50000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			opp-microvolt = <925000>;
> +		};
> +	};
>  };
>  
>  &combiner {
> 


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  5:57   ` Krzysztof Kozlowski
@ 2015-12-10  6:08     ` Chanwoo Choi
  2015-12-10  6:32       ` Krzysztof Kozlowski
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  6:08 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>> Exynos4x12 has the following AXI buses to translate data between
>> DRAM and sub-blocks.
>>
>> Following list specifies the detailed relation between DRAM and sub-blocks:
>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>> - ACLK160 clock for CAM/TV/LCD
>> : The minimum clock of ACLK160 should be over 160MHz.
>>   When drop the clock under 160MHz, show the broken image.
>> - ACLK133 clock for FSYS
>> - GDL clock for LEFTBUS
>> - GDR clock for RIGHTBUS
>> - SCLK_MFC clock for MFC
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 112 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>> index 3bcf0939755e..8bc4aee156b5 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -354,6 +354,118 @@
>>  			opp-microvolt = <950000>;
>>  		};
>>  	};
>> +
>> +	bus_leftbus: bus_leftbus {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_GDL>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_rightbus: bus_rightbus {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_GDR>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
> 
> These two nodes are symmetrical. The MFC below and other buses in other
> DTS share opps. How about changing the binding so multiple clocks could
> be specified at once ("bus0", "bus1")? I think there is no need for a
> bus device for each clock.

The your commented method is possible.

But, I focus on implementing the generic bus frequency driver.

If specific bus device-tree node includes the one more clocks,
when adding the new Exynos SoC, the exynos-bus.c should be added
for new Exynos SoC. Because, each Exynos SoC has the different
set of bus device.

If we use my approach, we don't need to modify the exynos-bus.c
driver to support for the bus frequency of new Exynos SoC.

Best Regards,
Chanwoo Choi

> 
> Best regards,
> Krzysztof
> 
>> +
>> +	bus_display: bus_display {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_ACLK160>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_display_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_fsys: bus_fsys {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_ACLK133>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_fsys_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_peri: bus_peri {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_ACLK100>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_peri_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_mfc: bus_mfc {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_SCLK_MFC>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_leftbus_opp_table: opp_table3 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <134000000>;
>> +			opp-microvolt = <925000>;
>> +		};
>> +		opp02 {
>> +			opp-hz = /bits/ 64 <160000000>;
>> +			opp-microvolt = <950000>;
>> +		};
>> +		opp03 {
>> +			opp-hz = /bits/ 64 <200000000>;
>> +			opp-microvolt = <1000000>;
>> +		};
>> +	};
>> +
>> +	bus_display_opp_table: opp_table4 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
>> +			opp-hz = /bits/ 64 <160000000>;
>> +			opp-microvolt = <950000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <200000000>;
>> +			opp-microvolt = <1000000>;
>> +		};
>> +	};
>> +
>> +	bus_fsys_opp_table: opp_table5 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <134000000>;
>> +			opp-microvolt = <925000>;
>> +		};
>> +	};
>> +
>> +	bus_peri_opp_table: opp_table6 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
>> +			opp-hz = /bits/ 64 <50000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <925000>;
>> +		};
>> +	};
>>  };
>>  
>>  &combiner {
>>
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  6:08     ` Chanwoo Choi
@ 2015-12-10  6:32       ` Krzysztof Kozlowski
  2015-12-10  6:43         ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  6:32 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 15:08, Chanwoo Choi wrote:
> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>> Exynos4x12 has the following AXI buses to translate data between
>>> DRAM and sub-blocks.
>>>
>>> Following list specifies the detailed relation between DRAM and sub-blocks:
>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>> - ACLK160 clock for CAM/TV/LCD
>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>   When drop the clock under 160MHz, show the broken image.
>>> - ACLK133 clock for FSYS
>>> - GDL clock for LEFTBUS
>>> - GDR clock for RIGHTBUS
>>> - SCLK_MFC clock for MFC
>>>
>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> ---
>>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 112 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>>> index 3bcf0939755e..8bc4aee156b5 100644
>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>> @@ -354,6 +354,118 @@
>>>  			opp-microvolt = <950000>;
>>>  		};
>>>  	};
>>> +
>>> +	bus_leftbus: bus_leftbus {
>>> +		compatible = "samsung,exynos-bus";
>>> +		clocks = <&clock CLK_DIV_GDL>;
>>> +		clock-names = "bus";
>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>> +		status = "disabled";
>>> +	};
>>> +
>>> +	bus_rightbus: bus_rightbus {
>>> +		compatible = "samsung,exynos-bus";
>>> +		clocks = <&clock CLK_DIV_GDR>;
>>> +		clock-names = "bus";
>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>> +		status = "disabled";
>>> +	};
>>
>> These two nodes are symmetrical. The MFC below and other buses in other
>> DTS share opps. How about changing the binding so multiple clocks could
>> be specified at once ("bus0", "bus1")? I think there is no need for a
>> bus device for each clock.
> 
> The your commented method is possible.
> 
> But, I focus on implementing the generic bus frequency driver.
> 
> If specific bus device-tree node includes the one more clocks,
> when adding the new Exynos SoC, the exynos-bus.c should be added
> for new Exynos SoC. Because, each Exynos SoC has the different
> set of bus device.
> 
> If we use my approach, we don't need to modify the exynos-bus.c
> driver to support for the bus frequency of new Exynos SoC.

This won't change. The driver will just support from 1 to N clocks for
given bus device and set the same OPP to all of them. This will only
limit the number of duplicated entries. This won't affect the generic
approach of driver itself.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  6:32       ` Krzysztof Kozlowski
@ 2015-12-10  6:43         ` Chanwoo Choi
  2015-12-10  6:53           ` Krzysztof Kozlowski
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  6:43 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
> On 10.12.2015 15:08, Chanwoo Choi wrote:
>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>> Exynos4x12 has the following AXI buses to translate data between
>>>> DRAM and sub-blocks.
>>>>
>>>> Following list specifies the detailed relation between DRAM and sub-blocks:
>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>> - ACLK160 clock for CAM/TV/LCD
>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>   When drop the clock under 160MHz, show the broken image.
>>>> - ACLK133 clock for FSYS
>>>> - GDL clock for LEFTBUS
>>>> - GDR clock for RIGHTBUS
>>>> - SCLK_MFC clock for MFC
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> ---
>>>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>>>  1 file changed, 112 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>> @@ -354,6 +354,118 @@
>>>>  			opp-microvolt = <950000>;
>>>>  		};
>>>>  	};
>>>> +
>>>> +	bus_leftbus: bus_leftbus {
>>>> +		compatible = "samsung,exynos-bus";
>>>> +		clocks = <&clock CLK_DIV_GDL>;
>>>> +		clock-names = "bus";
>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>> +		status = "disabled";
>>>> +	};
>>>> +
>>>> +	bus_rightbus: bus_rightbus {
>>>> +		compatible = "samsung,exynos-bus";
>>>> +		clocks = <&clock CLK_DIV_GDR>;
>>>> +		clock-names = "bus";
>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>> +		status = "disabled";
>>>> +	};
>>>
>>> These two nodes are symmetrical. The MFC below and other buses in other
>>> DTS share opps. How about changing the binding so multiple clocks could
>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>> bus device for each clock.
>>
>> The your commented method is possible.
>>
>> But, I focus on implementing the generic bus frequency driver.
>>
>> If specific bus device-tree node includes the one more clocks,
>> when adding the new Exynos SoC, the exynos-bus.c should be added
>> for new Exynos SoC. Because, each Exynos SoC has the different
>> set of bus device.
>>
>> If we use my approach, we don't need to modify the exynos-bus.c
>> driver to support for the bus frequency of new Exynos SoC.
> 
> This won't change. The driver will just support from 1 to N clocks for
> given bus device and set the same OPP to all of them. This will only
> limit the number of duplicated entries. This won't affect the generic
> approach of driver itself.

You're right aspect of only implementation of device driver.

But,
If we use your commented approach, we can show the information
of only parent device through sysfs. We cannot see the information
of passive device. The some information includes the current
frequency and correlation of parent device. (But, current patchset
don' include the topology information between parent device and
passive device. I'll do it on later patches).

For example, 
We can see the following bus device through /sys/class/devfreq.

drwxr-xr-x  2 root root 0 Dec 31 17:00 .
drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri


We don't see the following bus device because of following bus device
has the same frequency table with bus_leftbus device.
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus

Best Regards,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3
  2015-12-09  4:08 ` [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3 Chanwoo Choi
@ 2015-12-10  6:44   ` Krzysztof Kozlowski
  2015-12-11  2:27     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  6:44 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
> exynos4412-odroidu3 board. Each PPMU dt node includes one event of
> 'PPMU Count3'.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40 +++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 

The patch itself is good but now I see that it is duplicated with
Rinato, Monk and Trats2. Probably for all other Exynos4 and
one-cluster-Exynos5 boards this would be exactly the same as well.

How about making a DTSI file with common PPMU events configuration?

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  6:43         ` Chanwoo Choi
@ 2015-12-10  6:53           ` Krzysztof Kozlowski
  2015-12-10  7:07             ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  6:53 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 15:43, Chanwoo Choi wrote:
> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>>> Exynos4x12 has the following AXI buses to translate data between
>>>>> DRAM and sub-blocks.
>>>>>
>>>>> Following list specifies the detailed relation between DRAM and sub-blocks:
>>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>>> - ACLK160 clock for CAM/TV/LCD
>>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>>   When drop the clock under 160MHz, show the broken image.
>>>>> - ACLK133 clock for FSYS
>>>>> - GDL clock for LEFTBUS
>>>>> - GDR clock for RIGHTBUS
>>>>> - SCLK_MFC clock for MFC
>>>>>
>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>> ---
>>>>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>>>>  1 file changed, 112 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>> @@ -354,6 +354,118 @@
>>>>>  			opp-microvolt = <950000>;
>>>>>  		};
>>>>>  	};
>>>>> +
>>>>> +	bus_leftbus: bus_leftbus {
>>>>> +		compatible = "samsung,exynos-bus";
>>>>> +		clocks = <&clock CLK_DIV_GDL>;
>>>>> +		clock-names = "bus";
>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>> +		status = "disabled";
>>>>> +	};
>>>>> +
>>>>> +	bus_rightbus: bus_rightbus {
>>>>> +		compatible = "samsung,exynos-bus";
>>>>> +		clocks = <&clock CLK_DIV_GDR>;
>>>>> +		clock-names = "bus";
>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>> +		status = "disabled";
>>>>> +	};
>>>>
>>>> These two nodes are symmetrical. The MFC below and other buses in other
>>>> DTS share opps. How about changing the binding so multiple clocks could
>>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>>> bus device for each clock.
>>>
>>> The your commented method is possible.
>>>
>>> But, I focus on implementing the generic bus frequency driver.
>>>
>>> If specific bus device-tree node includes the one more clocks,
>>> when adding the new Exynos SoC, the exynos-bus.c should be added
>>> for new Exynos SoC. Because, each Exynos SoC has the different
>>> set of bus device.
>>>
>>> If we use my approach, we don't need to modify the exynos-bus.c
>>> driver to support for the bus frequency of new Exynos SoC.
>>
>> This won't change. The driver will just support from 1 to N clocks for
>> given bus device and set the same OPP to all of them. This will only
>> limit the number of duplicated entries. This won't affect the generic
>> approach of driver itself.
> 
> You're right aspect of only implementation of device driver.
> 
> But,
> If we use your commented approach, we can show the information
> of only parent device through sysfs. We cannot see the information
> of passive device. The some information includes the current
> frequency and correlation of parent device. (But, current patchset
> don' include the topology information between parent device and
> passive device. I'll do it on later patches).
> 
> For example, 
> We can see the following bus device through /sys/class/devfreq.
> 
> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
> 
> 
> We don't see the following bus device because of following bus device
> has the same frequency table with bus_leftbus device.
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus

Right, but why do you want to see these bus devices? AFAIU, they will
always behave exactly the same as LEFTBUS. Their PPMU counters will be
the same... or not? The MFC does not have its own PPMU counter. There
are separate counters for left and right bus... but they are attached to
the "&bus_leftbus" node. The "&bus_rightbus" does not use the PPMU
counter and it follows the parent governor decisions... so this is
purely an artificial creation just to handle one clock.

I just can't see the benefit of such additional bus device.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
  2015-12-09  4:08 ` [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato Chanwoo Choi
@ 2015-12-10  6:58   ` Krzysztof Kozlowski
  2015-12-10  7:24     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  6:58 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus device-tree node of INT (internal) block
> to enable the bus frequency. The following sub-blocks share

"to enable the bus frequency scaling"

> the VDD_INT power source:
> - LEFTBUS (parent device)
> - RIGHTBUS
> - PERIL
> - LCD0
> - FSYS
> - MCUISP / ISP
> - MFC
> 
> The LEFTBUS is parent device with devfreq ondemand governor
> and the rest devices has the dependency on LEFTBUS bus.

How about:
"and the rest of devices depend on the LEFTBUS device."
?

The patch is good:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
@ 2015-12-10  7:02     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  7:02 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch expands the voltage range of buck1/3 regulator due to as following:
> - MIF (Memory Interface) bus frequency needs the 90000uV ~ 1050000uV V.
> - INT (Internal) bus frequency needs 90000uV ~ 1000000uV.

90000->900000 and duplicated "uV V". Maybe just:
900 - 1050 mV
900 - 1000 mV
?

> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 

For the contents of patch:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof



^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
@ 2015-12-10  7:02     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  7:02 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ,
	kgene-DgEjT+Ai2ygdnm+yROfE0A
  Cc: kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	tjakobi-o02PS0xoJP9W0yFyLvAVXMxlOr/tl8fh,
	linux.amoon-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-pm-u79uwXL29TY76Z2rM5mHXA,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA

On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch expands the voltage range of buck1/3 regulator due to as following:
> - MIF (Memory Interface) bus frequency needs the 90000uV ~ 1050000uV V.
> - INT (Internal) bus frequency needs 90000uV ~ 1000000uV.

90000->900000 and duplicated "uV V". Maybe just:
900 - 1050 mV
900 - 1000 mV
?

> 
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 

For the contents of patch:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Best regards,
Krzysztof


--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  6:53           ` Krzysztof Kozlowski
@ 2015-12-10  7:07             ` Chanwoo Choi
  2015-12-10  7:12               ` Krzysztof Kozlowski
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  7:07 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
> On 10.12.2015 15:43, Chanwoo Choi wrote:
>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>>>> Exynos4x12 has the following AXI buses to translate data between
>>>>>> DRAM and sub-blocks.
>>>>>>
>>>>>> Following list specifies the detailed relation between DRAM and sub-blocks:
>>>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>>>> - ACLK160 clock for CAM/TV/LCD
>>>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>>>   When drop the clock under 160MHz, show the broken image.
>>>>>> - ACLK133 clock for FSYS
>>>>>> - GDL clock for LEFTBUS
>>>>>> - GDR clock for RIGHTBUS
>>>>>> - SCLK_MFC clock for MFC
>>>>>>
>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>> ---
>>>>>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>>>>>  1 file changed, 112 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>> @@ -354,6 +354,118 @@
>>>>>>  			opp-microvolt = <950000>;
>>>>>>  		};
>>>>>>  	};
>>>>>> +
>>>>>> +	bus_leftbus: bus_leftbus {
>>>>>> +		compatible = "samsung,exynos-bus";
>>>>>> +		clocks = <&clock CLK_DIV_GDL>;
>>>>>> +		clock-names = "bus";
>>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>>> +		status = "disabled";
>>>>>> +	};
>>>>>> +
>>>>>> +	bus_rightbus: bus_rightbus {
>>>>>> +		compatible = "samsung,exynos-bus";
>>>>>> +		clocks = <&clock CLK_DIV_GDR>;
>>>>>> +		clock-names = "bus";
>>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>>> +		status = "disabled";
>>>>>> +	};
>>>>>
>>>>> These two nodes are symmetrical. The MFC below and other buses in other
>>>>> DTS share opps. How about changing the binding so multiple clocks could
>>>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>>>> bus device for each clock.
>>>>
>>>> The your commented method is possible.
>>>>
>>>> But, I focus on implementing the generic bus frequency driver.
>>>>
>>>> If specific bus device-tree node includes the one more clocks,
>>>> when adding the new Exynos SoC, the exynos-bus.c should be added
>>>> for new Exynos SoC. Because, each Exynos SoC has the different
>>>> set of bus device.
>>>>
>>>> If we use my approach, we don't need to modify the exynos-bus.c
>>>> driver to support for the bus frequency of new Exynos SoC.
>>>
>>> This won't change. The driver will just support from 1 to N clocks for
>>> given bus device and set the same OPP to all of them. This will only
>>> limit the number of duplicated entries. This won't affect the generic
>>> approach of driver itself.
>>
>> You're right aspect of only implementation of device driver.
>>
>> But,
>> If we use your commented approach, we can show the information
>> of only parent device through sysfs. We cannot see the information
>> of passive device. The some information includes the current
>> frequency and correlation of parent device. (But, current patchset
>> don' include the topology information between parent device and
>> passive device. I'll do it on later patches).
>>
>> For example, 
>> We can see the following bus device through /sys/class/devfreq.
>>
>> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
>> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
>>
>>
>> We don't see the following bus device because of following bus device
>> has the same frequency table with bus_leftbus device.
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus
> 
> Right, but why do you want to see these bus devices? AFAIU, they will

I think that the framework should show the accurate information of H/w device
through sysfs. On the exynos-bus.c driver, it is important the show the
accurate set of handled bus devices which are included in Exynos SoC.

> always behave exactly the same as LEFTBUS. Their PPMU counters will be
> the same... or not? The MFC does not have its own PPMU counter. There
> are separate counters for left and right bus... but they are attached to
> the "&bus_leftbus" node. The "&bus_rightbus" does not use the PPMU
> counter and it follows the parent governor decisions... so this is
> purely an artificial creation just to handle one clock.
> 
> I just can't see the benefit of such additional bus device.

I agree about the behavior. Your description is right.
There is no difference and benefit about behavior both your and my approach.

But, We can provide the accurate information of handled bus devices
to the user-space. I think that it is important information.

Also, I have the plan that devfreq framework would show
the topology about the correlation of bus devices as following:

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
  2015-12-09  4:08 ` [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3 Chanwoo Choi
@ 2015-12-10  7:08   ` Krzysztof Kozlowski
  2015-12-10  7:23     ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  7:08 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 09.12.2015 13:08, Chanwoo Choi wrote:
> THis patch adds the bus device tree nodes for both MIF (Memory) and INT
> (Internal) block to enable the bus frequency.
> 
> The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
> bus is parent device in INT block using VDD_INT.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47 +++++++++++++++++++++++++
>  arch/arm/boot/dts/exynos4412-trats2.dts         | 47 +++++++++++++++++++++++++
>  2 files changed, 94 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
> index 171dea1e3e4a..12d08242a179 100644
> --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
> +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
> @@ -544,3 +544,50 @@
>  		};
>  	};
>  };
> +
> +&bus_dmc {
> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> +	vdd-supply = <&buck1_reg>;
> +	status = "okay";
> +};
> +
> +&bus_acp {
> +	devfreq = <&bus_dmc>;
> +	status = "okay";
> +};
> +
> +&bus_c2c {
> +	devfreq = <&bus_dmc>;
> +	status = "okay";
> +};
> +
> +&bus_leftbus {
> +	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
> +	vdd-supply = <&buck3_reg>;
> +	status = "okay";
> +};
> +
> +&bus_rightbus {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_display {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_fsys {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_peri {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_mfc {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
> index 40a474c4374b..aecd545803ad 100644
> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
> @@ -1286,3 +1286,50 @@
>  	vtmu-supply = <&ldo10_reg>;
>  	status = "okay";
>  };
> +
> +&bus_dmc {
> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
> +	vdd-supply = <&buck1_reg>;
> +	status = "okay";
> +};
> +
> +&bus_acp {
> +	devfreq = <&bus_dmc>;
> +	status = "okay";
> +};
> +
> +&bus_c2c {
> +	devfreq = <&bus_dmc>;
> +	status = "okay";
> +};
> +
> +&bus_leftbus {
> +	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
> +	vdd-supply = <&buck3_reg>;
> +	status = "okay";
> +};
> +
> +&bus_rightbus {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_display {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_fsys {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_peri {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};
> +
> +&bus_mfc {
> +	devfreq = <&bus_leftbus>;
> +	status = "okay";
> +};

The nodes in both files are mostly sorted alphabetically. Could you
place them in such order as well?

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  7:07             ` Chanwoo Choi
@ 2015-12-10  7:12               ` Krzysztof Kozlowski
  2015-12-10  7:18                 ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-10  7:12 UTC (permalink / raw)
  To: Chanwoo Choi, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 10.12.2015 16:07, Chanwoo Choi wrote:
> On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
>> On 10.12.2015 15:43, Chanwoo Choi wrote:
>>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>>>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>>>>> Exynos4x12 has the following AXI buses to translate data between
>>>>>>> DRAM and sub-blocks.
>>>>>>>
>>>>>>> Following list specifies the detailed relation between DRAM and sub-blocks:
>>>>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>>>>> - ACLK160 clock for CAM/TV/LCD
>>>>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>>>>   When drop the clock under 160MHz, show the broken image.
>>>>>>> - ACLK133 clock for FSYS
>>>>>>> - GDL clock for LEFTBUS
>>>>>>> - GDR clock for RIGHTBUS
>>>>>>> - SCLK_MFC clock for MFC
>>>>>>>
>>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>>> ---
>>>>>>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>>>>>>  1 file changed, 112 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>> @@ -354,6 +354,118 @@
>>>>>>>  			opp-microvolt = <950000>;
>>>>>>>  		};
>>>>>>>  	};
>>>>>>> +
>>>>>>> +	bus_leftbus: bus_leftbus {
>>>>>>> +		compatible = "samsung,exynos-bus";
>>>>>>> +		clocks = <&clock CLK_DIV_GDL>;
>>>>>>> +		clock-names = "bus";
>>>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>>>> +		status = "disabled";
>>>>>>> +	};
>>>>>>> +
>>>>>>> +	bus_rightbus: bus_rightbus {
>>>>>>> +		compatible = "samsung,exynos-bus";
>>>>>>> +		clocks = <&clock CLK_DIV_GDR>;
>>>>>>> +		clock-names = "bus";
>>>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>>>> +		status = "disabled";
>>>>>>> +	};
>>>>>>
>>>>>> These two nodes are symmetrical. The MFC below and other buses in other
>>>>>> DTS share opps. How about changing the binding so multiple clocks could
>>>>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>>>>> bus device for each clock.
>>>>>
>>>>> The your commented method is possible.
>>>>>
>>>>> But, I focus on implementing the generic bus frequency driver.
>>>>>
>>>>> If specific bus device-tree node includes the one more clocks,
>>>>> when adding the new Exynos SoC, the exynos-bus.c should be added
>>>>> for new Exynos SoC. Because, each Exynos SoC has the different
>>>>> set of bus device.
>>>>>
>>>>> If we use my approach, we don't need to modify the exynos-bus.c
>>>>> driver to support for the bus frequency of new Exynos SoC.
>>>>
>>>> This won't change. The driver will just support from 1 to N clocks for
>>>> given bus device and set the same OPP to all of them. This will only
>>>> limit the number of duplicated entries. This won't affect the generic
>>>> approach of driver itself.
>>>
>>> You're right aspect of only implementation of device driver.
>>>
>>> But,
>>> If we use your commented approach, we can show the information
>>> of only parent device through sysfs. We cannot see the information
>>> of passive device. The some information includes the current
>>> frequency and correlation of parent device. (But, current patchset
>>> don' include the topology information between parent device and
>>> passive device. I'll do it on later patches).
>>>
>>> For example, 
>>> We can see the following bus device through /sys/class/devfreq.
>>>
>>> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
>>> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
>>>
>>>
>>> We don't see the following bus device because of following bus device
>>> has the same frequency table with bus_leftbus device.
>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus
>>
>> Right, but why do you want to see these bus devices? AFAIU, they will
> 
> I think that the framework should show the accurate information of H/w device
> through sysfs. On the exynos-bus.c driver, it is important the show the
> accurate set of handled bus devices which are included in Exynos SoC.
> 
>> always behave exactly the same as LEFTBUS. Their PPMU counters will be
>> the same... or not? The MFC does not have its own PPMU counter. There
>> are separate counters for left and right bus... but they are attached to
>> the "&bus_leftbus" node. The "&bus_rightbus" does not use the PPMU
>> counter and it follows the parent governor decisions... so this is
>> purely an artificial creation just to handle one clock.
>>
>> I just can't see the benefit of such additional bus device.
> 
> I agree about the behavior. Your description is right.
> There is no difference and benefit about behavior both your and my approach.
> 
> But, We can provide the accurate information of handled bus devices
> to the user-space. I think that it is important information.
> 
> Also, I have the plan that devfreq framework would show
> the topology about the correlation of bus devices as following:

Hmmm.... okay, fair enough. From hardware point of view these are
separate AXI buses so I guess it is good to model them in DT.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12
  2015-12-10  7:12               ` Krzysztof Kozlowski
@ 2015-12-10  7:18                 ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  7:18 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 16:12, Krzysztof Kozlowski wrote:
> On 10.12.2015 16:07, Chanwoo Choi wrote:
>> On 2015년 12월 10일 15:53, Krzysztof Kozlowski wrote:
>>> On 10.12.2015 15:43, Chanwoo Choi wrote:
>>>> On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote:
>>>>> On 10.12.2015 15:08, Chanwoo Choi wrote:
>>>>>> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote:
>>>>>>> On 09.12.2015 13:08, Chanwoo Choi wrote:
>>>>>>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC.
>>>>>>>> Exynos4x12 has the following AXI buses to translate data between
>>>>>>>> DRAM and sub-blocks.
>>>>>>>>
>>>>>>>> Following list specifies the detailed relation between DRAM and sub-blocks:
>>>>>>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
>>>>>>>> - ACLK160 clock for CAM/TV/LCD
>>>>>>>> : The minimum clock of ACLK160 should be over 160MHz.
>>>>>>>>   When drop the clock under 160MHz, show the broken image.
>>>>>>>> - ACLK133 clock for FSYS
>>>>>>>> - GDL clock for LEFTBUS
>>>>>>>> - GDR clock for RIGHTBUS
>>>>>>>> - SCLK_MFC clock for MFC
>>>>>>>>
>>>>>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>>>>> ---
>>>>>>>>  arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++
>>>>>>>>  1 file changed, 112 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> index 3bcf0939755e..8bc4aee156b5 100644
>>>>>>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>>>>>>>> @@ -354,6 +354,118 @@
>>>>>>>>  			opp-microvolt = <950000>;
>>>>>>>>  		};
>>>>>>>>  	};
>>>>>>>> +
>>>>>>>> +	bus_leftbus: bus_leftbus {
>>>>>>>> +		compatible = "samsung,exynos-bus";
>>>>>>>> +		clocks = <&clock CLK_DIV_GDL>;
>>>>>>>> +		clock-names = "bus";
>>>>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>>>>> +		status = "disabled";
>>>>>>>> +	};
>>>>>>>> +
>>>>>>>> +	bus_rightbus: bus_rightbus {
>>>>>>>> +		compatible = "samsung,exynos-bus";
>>>>>>>> +		clocks = <&clock CLK_DIV_GDR>;
>>>>>>>> +		clock-names = "bus";
>>>>>>>> +		operating-points-v2 = <&bus_leftbus_opp_table>;
>>>>>>>> +		status = "disabled";
>>>>>>>> +	};
>>>>>>>
>>>>>>> These two nodes are symmetrical. The MFC below and other buses in other
>>>>>>> DTS share opps. How about changing the binding so multiple clocks could
>>>>>>> be specified at once ("bus0", "bus1")? I think there is no need for a
>>>>>>> bus device for each clock.
>>>>>>
>>>>>> The your commented method is possible.
>>>>>>
>>>>>> But, I focus on implementing the generic bus frequency driver.
>>>>>>
>>>>>> If specific bus device-tree node includes the one more clocks,
>>>>>> when adding the new Exynos SoC, the exynos-bus.c should be added
>>>>>> for new Exynos SoC. Because, each Exynos SoC has the different
>>>>>> set of bus device.
>>>>>>
>>>>>> If we use my approach, we don't need to modify the exynos-bus.c
>>>>>> driver to support for the bus frequency of new Exynos SoC.
>>>>>
>>>>> This won't change. The driver will just support from 1 to N clocks for
>>>>> given bus device and set the same OPP to all of them. This will only
>>>>> limit the number of duplicated entries. This won't affect the generic
>>>>> approach of driver itself.
>>>>
>>>> You're right aspect of only implementation of device driver.
>>>>
>>>> But,
>>>> If we use your commented approach, we can show the information
>>>> of only parent device through sysfs. We cannot see the information
>>>> of passive device. The some information includes the current
>>>> frequency and correlation of parent device. (But, current patchset
>>>> don' include the topology information between parent device and
>>>> passive device. I'll do it on later patches).
>>>>
>>>> For example, 
>>>> We can see the following bus device through /sys/class/devfreq.
>>>>
>>>> drwxr-xr-x  2 root root 0 Dec 31 17:00 .
>>>> drwxr-xr-x 44 root root 0 Dec 31 17:00 ..
>>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display
>>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys
>>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus
>>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri
>>>>
>>>>
>>>> We don't see the following bus device because of following bus device
>>>> has the same frequency table with bus_leftbus device.
>>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc
>>>> lrwxrwxrwx  1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus
>>>
>>> Right, but why do you want to see these bus devices? AFAIU, they will
>>
>> I think that the framework should show the accurate information of H/w device
>> through sysfs. On the exynos-bus.c driver, it is important the show the
>> accurate set of handled bus devices which are included in Exynos SoC.
>>
>>> always behave exactly the same as LEFTBUS. Their PPMU counters will be
>>> the same... or not? The MFC does not have its own PPMU counter. There
>>> are separate counters for left and right bus... but they are attached to
>>> the "&bus_leftbus" node. The "&bus_rightbus" does not use the PPMU
>>> counter and it follows the parent governor decisions... so this is
>>> purely an artificial creation just to handle one clock.
>>>
>>> I just can't see the benefit of such additional bus device.
>>
>> I agree about the behavior. Your description is right.
>> There is no difference and benefit about behavior both your and my approach.
>>
>> But, We can provide the accurate information of handled bus devices
>> to the user-space. I think that it is important information.
>>
>> Also, I have the plan that devfreq framework would show
>> the topology about the correlation of bus devices as following:
> 
> Hmmm.... okay, fair enough. From hardware point of view these are
> separate AXI buses so I guess it is good to model them in DT.

Thanks for your review.

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
  2015-12-10  7:02     ` Krzysztof Kozlowski
  (?)
@ 2015-12-10  7:19     ` Chanwoo Choi
  -1 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  7:19 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 16:02, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch expands the voltage range of buck1/3 regulator due to as following:
>> - MIF (Memory Interface) bus frequency needs the 90000uV ~ 1050000uV V.
>> - INT (Internal) bus frequency needs 90000uV ~ 1000000uV.
> 
> 90000->900000 and duplicated "uV V". Maybe just:
> 900 - 1050 mV
> 900 - 1000 mV
> ?

OK. I'll modify the patch description.

> 
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
> 
> For the contents of patch:
> 
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best Regards,
Chanwoo CHoi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3
  2015-12-10  7:08   ` Krzysztof Kozlowski
@ 2015-12-10  7:23     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  7:23 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 16:08, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> THis patch adds the bus device tree nodes for both MIF (Memory) and INT
>> (Internal) block to enable the bus frequency.
>>
>> The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS
>> bus is parent device in INT block using VDD_INT.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 47 +++++++++++++++++++++++++
>>  arch/arm/boot/dts/exynos4412-trats2.dts         | 47 +++++++++++++++++++++++++
>>  2 files changed, 94 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> index 171dea1e3e4a..12d08242a179 100644
>> --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
>> @@ -544,3 +544,50 @@
>>  		};
>>  	};
>>  };
>> +
>> +&bus_dmc {
>> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>> +	vdd-supply = <&buck1_reg>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_acp {
>> +	devfreq = <&bus_dmc>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_c2c {
>> +	devfreq = <&bus_dmc>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_leftbus {
>> +	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>> +	vdd-supply = <&buck3_reg>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_rightbus {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_display {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_fsys {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_peri {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_mfc {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
>> index 40a474c4374b..aecd545803ad 100644
>> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
>> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
>> @@ -1286,3 +1286,50 @@
>>  	vtmu-supply = <&ldo10_reg>;
>>  	status = "okay";
>>  };
>> +
>> +&bus_dmc {
>> +	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
>> +	vdd-supply = <&buck1_reg>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_acp {
>> +	devfreq = <&bus_dmc>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_c2c {
>> +	devfreq = <&bus_dmc>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_leftbus {
>> +	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
>> +	vdd-supply = <&buck3_reg>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_rightbus {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_display {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_fsys {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_peri {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
>> +
>> +&bus_mfc {
>> +	devfreq = <&bus_leftbus>;
>> +	status = "okay";
>> +};
> 
> The nodes in both files are mostly sorted alphabetically. Could you
> place them in such order as well?

Okay. I'll sort them alphabetically.

Best Regards,
Chanwoo Choi




^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato
  2015-12-10  6:58   ` Krzysztof Kozlowski
@ 2015-12-10  7:24     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10  7:24 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 15:58, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus device-tree node of INT (internal) block
>> to enable the bus frequency. The following sub-blocks share
> 
> "to enable the bus frequency scaling"
> 
>> the VDD_INT power source:
>> - LEFTBUS (parent device)
>> - RIGHTBUS
>> - PERIL
>> - LCD0
>> - FSYS
>> - MCUISP / ISP
>> - MFC
>>
>> The LEFTBUS is parent device with devfreq ondemand governor
>> and the rest devices has the dependency on LEFTBUS bus.
> 
> How about:
> "and the rest of devices depend on the LEFTBUS device."
> ?

OK, I'll modify it.

> 
> The patch is good:
> 
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Thanks for your review.

Best Regards,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-09  4:08 ` [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices " Chanwoo Choi
  2015-12-10  1:31   ` Krzysztof Kozlowski
@ 2015-12-10 14:21   ` Rob Herring
  2015-12-10 15:10     ` Chanwoo Choi
  1 sibling, 1 reply; 72+ messages in thread
From: Rob Herring @ 2015-12-10 14:21 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: myungjoo.ham, k.kozlowski, kgene, kyungmin.park, pawel.moll,
	mark.rutland, ijc+devicetree, galak, linux, tjakobi, linux.amoon,
	linux-kernel, linux-pm, linux-samsung-soc, devicetree

On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote:
> This patch updates the documentation for passive bus devices and adds the
> detailed example of Exynos3250.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
>  1 file changed, 241 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> index 54a1f9c46c88..c4fdc70f8eac 100644
> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
>  in devicetree file instead of each device driver. In result, this driver
>  is able to support the bus frequency for all Exynos SoCs.
>  
> -Required properties for bus device:
> +Required properties for all bus devices:
>  - compatible: Should be "samsung,exynos-bus".
>  - clock-names : the name of clock used by the bus, "bus".
>  - clocks : phandles for clock specified in "clock-names" property.
>  - #clock-cells: should be 1.
>  - operating-points-v2: the OPP table including frequency/voltage information
>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
> +
> +Required properties for only parent bus device:
>  - vdd-supply: the regulator to provide the buses with the voltage.
>  - devfreq-events: the devfreq-event device to monitor the curret utilization
>    of buses.
>  
> -Optional properties for bus device:
> +Required properties for only passive bus device:
> +- devfreq: the parent bus device.
> +
> +Optional properties for only parent bus device:
>  - exynos,saturation-ratio: the percentage value which is used to calibrate
>                     the performance count againt total cycle count.
>  
> @@ -33,7 +38,20 @@ Example1:
>  	power line (regulator). The MIF (Memory Interface) AXI bus is used to
>  	transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>  
> -	- power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
> +	- MIF (Memory Interface) block
> +	: VDD_MIF |--- DMC (Dynamic Memory Controller)
> +
> +	- INT (Internal) block
> +	: VDD_INT |--- LEFTBUS (parent device)
> +		  |--- PERIL
> +		  |--- MFC
> +		  |--- G3D
> +		  |--- RIGHTBUS
> +		  |--- FSYS
> +		  |--- LCD0
> +		  |--- PERIR
> +		  |--- ISP
> +		  |--- CAM

This still has the same problem as before. I would expect that the bus 
hierarchy in the dts match the hierarchy here. You just have flat nodes 
in the example below. So all IP blocks affected by frequency scaling 
should be under the bus node defining the OPPs. Something like this:

soc {
	compatible = "simple-bus";
	bus {
		compatible = "my-awesome-dvfs-bus"; /* simple-bus too if 
no setup needed first */
		reg = <0x0 0x0>; // Bus control registers
		clocks = <&ccm BUS_CLK>;
		operating-points-v2 = <&opp>;
		device@0 {
			compatible = "my-awesome-device-1";
		};
		device@1 {
			compatible = "my-awesome-device-2";
		};
	};
};

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-10 14:21   ` Rob Herring
@ 2015-12-10 15:10     ` Chanwoo Choi
  2015-12-11  3:24       ` Rob Herring
  0 siblings, 1 reply; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-10 15:10 UTC (permalink / raw)
  To: Rob Herring
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Pawel Moll, Mark Rutland, Ian Campbell,
	Kumar Gala, Russell King - ARM Linux, tjakobi, linux.amoon,
	linux-kernel, linux-pm, linux-samsung-soc, devicetree

On Thu, Dec 10, 2015 at 11:21 PM, Rob Herring <robh@kernel.org> wrote:
> On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote:
>> This patch updates the documentation for passive bus devices and adds the
>> detailed example of Exynos3250.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
>>  1 file changed, 241 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> index 54a1f9c46c88..c4fdc70f8eac 100644
>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
>>  in devicetree file instead of each device driver. In result, this driver
>>  is able to support the bus frequency for all Exynos SoCs.
>>
>> -Required properties for bus device:
>> +Required properties for all bus devices:
>>  - compatible: Should be "samsung,exynos-bus".
>>  - clock-names : the name of clock used by the bus, "bus".
>>  - clocks : phandles for clock specified in "clock-names" property.
>>  - #clock-cells: should be 1.
>>  - operating-points-v2: the OPP table including frequency/voltage information
>>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>> +
>> +Required properties for only parent bus device:
>>  - vdd-supply: the regulator to provide the buses with the voltage.
>>  - devfreq-events: the devfreq-event device to monitor the curret utilization
>>    of buses.
>>
>> -Optional properties for bus device:
>> +Required properties for only passive bus device:
>> +- devfreq: the parent bus device.
>> +
>> +Optional properties for only parent bus device:
>>  - exynos,saturation-ratio: the percentage value which is used to calibrate
>>                     the performance count againt total cycle count.
>>
>> @@ -33,7 +38,20 @@ Example1:
>>       power line (regulator). The MIF (Memory Interface) AXI bus is used to
>>       transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>>
>> -     - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>> +     - MIF (Memory Interface) block
>> +     : VDD_MIF |--- DMC (Dynamic Memory Controller)
>> +
>> +     - INT (Internal) block
>> +     : VDD_INT |--- LEFTBUS (parent device)
>> +               |--- PERIL
>> +               |--- MFC
>> +               |--- G3D
>> +               |--- RIGHTBUS
>> +               |--- FSYS
>> +               |--- LCD0
>> +               |--- PERIR
>> +               |--- ISP
>> +               |--- CAM
>
> This still has the same problem as before. I would expect that the bus
> hierarchy in the dts match the hierarchy here. You just have flat nodes
> in the example below. So all IP blocks affected by frequency scaling
> should be under the bus node defining the OPPs. Something like this:

The each bus of sub-block has not h/w dependency among sub-blocks
and has the owned source clock / OPP table. Just they share the same
power line. So, I think that flat nodes in the example below is not problem.

Because of using the same power line, the sub-blocks would be tied
by devfreq framework only for the behavior of bus frequency scaling .

>
> soc {
>         compatible = "simple-bus";
>         bus {
>                 compatible = "my-awesome-dvfs-bus"; /* simple-bus too if
> no setup needed first */
>                 reg = <0x0 0x0>; // Bus control registers
>                 clocks = <&ccm BUS_CLK>;
>                 operating-points-v2 = <&opp>;
>                 device@0 {
>                         compatible = "my-awesome-device-1";
>                 };
>                 device@1 {
>                         compatible = "my-awesome-device-2";
>                 };
>         };
> };

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3
  2015-12-10  6:44   ` Krzysztof Kozlowski
@ 2015-12-11  2:27     ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-11  2:27 UTC (permalink / raw)
  To: Krzysztof Kozlowski, myungjoo.ham, kgene
  Cc: kyungmin.park, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
	galak, linux, tjakobi, linux.amoon, linux-kernel, linux-pm,
	linux-samsung-soc, devicetree

On 2015년 12월 10일 15:44, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
>> exynos4412-odroidu3 board. Each PPMU dt node includes one event of
>> 'PPMU Count3'.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 40 +++++++++++++++++++++++++
>>  1 file changed, 40 insertions(+)
>>
> 
> The patch itself is good but now I see that it is duplicated with
> Rinato, Monk and Trats2. Probably for all other Exynos4 and
> one-cluster-Exynos5 boards this would be exactly the same as well.
> 
> How about making a DTSI file with common PPMU events configuration?

OK. I'll make the exynos4412-ppmu-common.dtsi.

The Exynos4 series used the PPMU firstly. That is why deciding the filename
of exynos4412-ppmu-common.dtsi.

Best Regards,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-10 15:10     ` Chanwoo Choi
@ 2015-12-11  3:24       ` Rob Herring
  2015-12-11  3:56           ` Chanwoo Choi
  0 siblings, 1 reply; 72+ messages in thread
From: Rob Herring @ 2015-12-11  3:24 UTC (permalink / raw)
  To: cw00.choi
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Pawel Moll, Mark Rutland, Ian Campbell,
	Kumar Gala, Russell King - ARM Linux, tjakobi, linux.amoon,
	linux-kernel, linux-pm, linux-samsung-soc, devicetree

On Fri, Dec 11, 2015 at 12:10:13AM +0900, Chanwoo Choi wrote:
> On Thu, Dec 10, 2015 at 11:21 PM, Rob Herring <robh@kernel.org> wrote:
> > On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote:
> >> This patch updates the documentation for passive bus devices and adds the
> >> detailed example of Exynos3250.
> >>
> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> >> ---
> >>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
> >>  1 file changed, 241 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> >> index 54a1f9c46c88..c4fdc70f8eac 100644
> >> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> >> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> >> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
> >>  in devicetree file instead of each device driver. In result, this driver
> >>  is able to support the bus frequency for all Exynos SoCs.
> >>
> >> -Required properties for bus device:
> >> +Required properties for all bus devices:
> >>  - compatible: Should be "samsung,exynos-bus".
> >>  - clock-names : the name of clock used by the bus, "bus".
> >>  - clocks : phandles for clock specified in "clock-names" property.
> >>  - #clock-cells: should be 1.
> >>  - operating-points-v2: the OPP table including frequency/voltage information
> >>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
> >> +
> >> +Required properties for only parent bus device:
> >>  - vdd-supply: the regulator to provide the buses with the voltage.
> >>  - devfreq-events: the devfreq-event device to monitor the curret utilization
> >>    of buses.
> >>
> >> -Optional properties for bus device:
> >> +Required properties for only passive bus device:
> >> +- devfreq: the parent bus device.
> >> +
> >> +Optional properties for only parent bus device:
> >>  - exynos,saturation-ratio: the percentage value which is used to calibrate
> >>                     the performance count againt total cycle count.
> >>
> >> @@ -33,7 +38,20 @@ Example1:
> >>       power line (regulator). The MIF (Memory Interface) AXI bus is used to
> >>       transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
> >>
> >> -     - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
> >> +     - MIF (Memory Interface) block
> >> +     : VDD_MIF |--- DMC (Dynamic Memory Controller)
> >> +
> >> +     - INT (Internal) block
> >> +     : VDD_INT |--- LEFTBUS (parent device)
> >> +               |--- PERIL
> >> +               |--- MFC
> >> +               |--- G3D
> >> +               |--- RIGHTBUS
> >> +               |--- FSYS
> >> +               |--- LCD0
> >> +               |--- PERIR
> >> +               |--- ISP
> >> +               |--- CAM
> >
> > This still has the same problem as before. I would expect that the bus
> > hierarchy in the dts match the hierarchy here. You just have flat nodes
> > in the example below. So all IP blocks affected by frequency scaling
> > should be under the bus node defining the OPPs. Something like this:
> 
> The each bus of sub-block has not h/w dependency among sub-blocks
> and has the owned source clock / OPP table. Just they share the same
> power line. So, I think that flat nodes in the example below is not problem.

I'm talking about the peripherals not described here. Is the ISP block 
not a child of the bus_isp node? Same for the display controller block 
and bus_lcd0. And so on.

Rob


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
  2015-12-11  3:24       ` Rob Herring
@ 2015-12-11  3:56           ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-11  3:56 UTC (permalink / raw)
  To: Rob Herring
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Pawel Moll, Mark Rutland, Ian Campbell,
	Kumar Gala, Russell King - ARM Linux, tjakobi, linux.amoon,
	linux-kernel, linux-pm, linux-samsung-soc, devicetree

On 2015년 12월 11일 12:24, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 12:10:13AM +0900, Chanwoo Choi wrote:
>> On Thu, Dec 10, 2015 at 11:21 PM, Rob Herring <robh@kernel.org> wrote:
>>> On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote:
>>>> This patch updates the documentation for passive bus devices and adds the
>>>> detailed example of Exynos3250.
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> ---
>>>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
>>>>  1 file changed, 241 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>> index 54a1f9c46c88..c4fdc70f8eac 100644
>>>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
>>>>  in devicetree file instead of each device driver. In result, this driver
>>>>  is able to support the bus frequency for all Exynos SoCs.
>>>>
>>>> -Required properties for bus device:
>>>> +Required properties for all bus devices:
>>>>  - compatible: Should be "samsung,exynos-bus".
>>>>  - clock-names : the name of clock used by the bus, "bus".
>>>>  - clocks : phandles for clock specified in "clock-names" property.
>>>>  - #clock-cells: should be 1.
>>>>  - operating-points-v2: the OPP table including frequency/voltage information
>>>>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>>>> +
>>>> +Required properties for only parent bus device:
>>>>  - vdd-supply: the regulator to provide the buses with the voltage.
>>>>  - devfreq-events: the devfreq-event device to monitor the curret utilization
>>>>    of buses.
>>>>
>>>> -Optional properties for bus device:
>>>> +Required properties for only passive bus device:
>>>> +- devfreq: the parent bus device.
>>>> +
>>>> +Optional properties for only parent bus device:
>>>>  - exynos,saturation-ratio: the percentage value which is used to calibrate
>>>>                     the performance count againt total cycle count.
>>>>
>>>> @@ -33,7 +38,20 @@ Example1:
>>>>       power line (regulator). The MIF (Memory Interface) AXI bus is used to
>>>>       transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>>>>
>>>> -     - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>>>> +     - MIF (Memory Interface) block
>>>> +     : VDD_MIF |--- DMC (Dynamic Memory Controller)
>>>> +
>>>> +     - INT (Internal) block
>>>> +     : VDD_INT |--- LEFTBUS (parent device)
>>>> +               |--- PERIL
>>>> +               |--- MFC
>>>> +               |--- G3D
>>>> +               |--- RIGHTBUS
>>>> +               |--- FSYS
>>>> +               |--- LCD0
>>>> +               |--- PERIR
>>>> +               |--- ISP
>>>> +               |--- CAM
>>>
>>> This still has the same problem as before. I would expect that the bus
>>> hierarchy in the dts match the hierarchy here. You just have flat nodes
>>> in the example below. So all IP blocks affected by frequency scaling
>>> should be under the bus node defining the OPPs. Something like this:
>>
>> The each bus of sub-block has not h/w dependency among sub-blocks
>> and has the owned source clock / OPP table. Just they share the same
>> power line. So, I think that flat nodes in the example below is not problem.
> 
> I'm talking about the peripherals not described here. Is the ISP block 
> not a child of the bus_isp node? Same for the display controller block 
> and bus_lcd0. And so on.

>From the H/W point of view, ISP block is really not included in ISP's AXI bus (bus_isp).
Just, the bus_isp connect to between ISP block and DRAM.

Thanks,
Chanwoo Choi


^ permalink raw reply	[flat|nested] 72+ messages in thread

* Re: [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices using passive governor
@ 2015-12-11  3:56           ` Chanwoo Choi
  0 siblings, 0 replies; 72+ messages in thread
From: Chanwoo Choi @ 2015-12-11  3:56 UTC (permalink / raw)
  To: Rob Herring
  Cc: myungjoo.ham, Krzysztof Kozłowski, Kukjin Kim,
	Kyungmin Park, Pawel Moll, Mark Rutland, Ian Campbell,
	Kumar Gala, Russell King - ARM Linux, tjakobi, linux.amoon,
	linux-kernel, linux-pm, linux-samsung-soc, devicetree

On 2015년 12월 11일 12:24, Rob Herring wrote:
> On Fri, Dec 11, 2015 at 12:10:13AM +0900, Chanwoo Choi wrote:
>> On Thu, Dec 10, 2015 at 11:21 PM, Rob Herring <robh@kernel.org> wrote:
>>> On Wed, Dec 09, 2015 at 01:08:01PM +0900, Chanwoo Choi wrote:
>>>> This patch updates the documentation for passive bus devices and adds the
>>>> detailed example of Exynos3250.
>>>>
>>>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>> ---
>>>>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 244 ++++++++++++++++++++-
>>>>  1 file changed, 241 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>> index 54a1f9c46c88..c4fdc70f8eac 100644
>>>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>>> @@ -13,18 +13,23 @@ SoC has the different sub-blocks. So, this difference should be specified
>>>>  in devicetree file instead of each device driver. In result, this driver
>>>>  is able to support the bus frequency for all Exynos SoCs.
>>>>
>>>> -Required properties for bus device:
>>>> +Required properties for all bus devices:
>>>>  - compatible: Should be "samsung,exynos-bus".
>>>>  - clock-names : the name of clock used by the bus, "bus".
>>>>  - clocks : phandles for clock specified in "clock-names" property.
>>>>  - #clock-cells: should be 1.
>>>>  - operating-points-v2: the OPP table including frequency/voltage information
>>>>    to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
>>>> +
>>>> +Required properties for only parent bus device:
>>>>  - vdd-supply: the regulator to provide the buses with the voltage.
>>>>  - devfreq-events: the devfreq-event device to monitor the curret utilization
>>>>    of buses.
>>>>
>>>> -Optional properties for bus device:
>>>> +Required properties for only passive bus device:
>>>> +- devfreq: the parent bus device.
>>>> +
>>>> +Optional properties for only parent bus device:
>>>>  - exynos,saturation-ratio: the percentage value which is used to calibrate
>>>>                     the performance count againt total cycle count.
>>>>
>>>> @@ -33,7 +38,20 @@ Example1:
>>>>       power line (regulator). The MIF (Memory Interface) AXI bus is used to
>>>>       transfer data between DRAM and CPU and uses the VDD_MIF regualtor.
>>>>
>>>> -     - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block
>>>> +     - MIF (Memory Interface) block
>>>> +     : VDD_MIF |--- DMC (Dynamic Memory Controller)
>>>> +
>>>> +     - INT (Internal) block
>>>> +     : VDD_INT |--- LEFTBUS (parent device)
>>>> +               |--- PERIL
>>>> +               |--- MFC
>>>> +               |--- G3D
>>>> +               |--- RIGHTBUS
>>>> +               |--- FSYS
>>>> +               |--- LCD0
>>>> +               |--- PERIR
>>>> +               |--- ISP
>>>> +               |--- CAM
>>>
>>> This still has the same problem as before. I would expect that the bus
>>> hierarchy in the dts match the hierarchy here. You just have flat nodes
>>> in the example below. So all IP blocks affected by frequency scaling
>>> should be under the bus node defining the OPPs. Something like this:
>>
>> The each bus of sub-block has not h/w dependency among sub-blocks
>> and has the owned source clock / OPP table. Just they share the same
>> power line. So, I think that flat nodes in the example below is not problem.
> 
> I'm talking about the peripherals not described here. Is the ISP block 
> not a child of the bus_isp node? Same for the display controller block 
> and bus_lcd0. And so on.

From the H/W point of view, ISP block is really not included in ISP's AXI bus (bus_isp).
Just, the bus_isp connect to between ISP block and DRAM.

Thanks,
Chanwoo Choi

^ permalink raw reply	[flat|nested] 72+ messages in thread

end of thread, other threads:[~2015-12-11  3:57 UTC | newest]

Thread overview: 72+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-09  4:07 [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Chanwoo Choi
2015-12-09  4:07 ` [PATCH v2 01/19] PM / devfreq: exynos: Add generic exynos bus frequency driver Chanwoo Choi
2015-12-09  4:07 ` [PATCH v2 02/19] PM / devfreq: exynos: Add documentation for " Chanwoo Choi
2015-12-10  0:39   ` Krzysztof Kozlowski
2015-12-10  0:49     ` Chanwoo Choi
2015-12-10  0:49       ` Chanwoo Choi
2015-12-10  1:25       ` Krzysztof Kozlowski
2015-12-10  1:33         ` Chanwoo Choi
2015-12-09  4:07 ` [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250 Chanwoo Choi
2015-12-10  0:44   ` Krzysztof Kozlowski
2015-12-10  1:09     ` Chanwoo Choi
2015-12-10  1:20       ` Krzysztof Kozlowski
2015-12-10  2:00         ` Chanwoo Choi
2015-12-10  2:04           ` Krzysztof Kozlowski
2015-12-10  2:17             ` Chanwoo Choi
2015-12-10  2:21               ` Krzysztof Kozlowski
2015-12-09  4:07 ` [PATCH v2 04/19] ARM: dts: Add DMC bus frequency for exynos3250-rinato/monk Chanwoo Choi
2015-12-10  0:53   ` Krzysztof Kozlowski
2015-12-10  0:56     ` Chanwoo Choi
2015-12-09  4:07 ` [PATCH v2 05/19] PM / devfreq: Add new passive governor Chanwoo Choi
2015-12-09  4:07 ` [PATCH v2 06/19] PM / devfreq: Add devfreq_get_devfreq_by_phandle() Chanwoo Choi
2015-12-09  4:07 ` [PATCH v2 07/19] PM / devfreq: Show the related information according to governor type Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 08/19] PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governor Chanwoo Choi
2015-12-09  4:08   ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 09/19] PM / devfreq: exynos: Update documentation for bus devices " Chanwoo Choi
2015-12-10  1:31   ` Krzysztof Kozlowski
2015-12-10  1:36     ` Chanwoo Choi
2015-12-10 14:21   ` Rob Herring
2015-12-10 15:10     ` Chanwoo Choi
2015-12-11  3:24       ` Rob Herring
2015-12-11  3:56         ` Chanwoo Choi
2015-12-11  3:56           ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 10/19] PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line Chanwoo Choi
2015-12-09  4:08   ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 11/19] PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Chanwoo Choi
2015-12-10  2:09   ` Krzysztof Kozlowski
2015-12-10  2:30     ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi
2015-12-10  3:17   ` Krzysztof Kozlowski
2015-12-10  4:21     ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT " Chanwoo Choi
2015-12-10  5:57   ` Krzysztof Kozlowski
2015-12-10  6:08     ` Chanwoo Choi
2015-12-10  6:32       ` Krzysztof Kozlowski
2015-12-10  6:43         ` Chanwoo Choi
2015-12-10  6:53           ` Krzysztof Kozlowski
2015-12-10  7:07             ` Chanwoo Choi
2015-12-10  7:12               ` Krzysztof Kozlowski
2015-12-10  7:18                 ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 15/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210 Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 16/19] ARM: dts: Add PPMU node for exynos4412-odroidu3 Chanwoo Choi
2015-12-10  6:44   ` Krzysztof Kozlowski
2015-12-11  2:27     ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 17/19] ARM: dts: Add support of bus frequency using VDD_INT for exynos3250-rinato Chanwoo Choi
2015-12-10  6:58   ` Krzysztof Kozlowski
2015-12-10  7:24     ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 18/19] ARM: dts: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 Chanwoo Choi
2015-12-10  7:02   ` Krzysztof Kozlowski
2015-12-10  7:02     ` Krzysztof Kozlowski
2015-12-10  7:19     ` Chanwoo Choi
2015-12-09  4:08 ` [PATCH v2 19/19] ARM: dts: Add support of bus frequency for exynos4412-trats/odroidu3 Chanwoo Choi
2015-12-10  7:08   ` Krzysztof Kozlowski
2015-12-10  7:23     ` Chanwoo Choi
2015-12-09 19:05 ` [PATCH v2 00/19] PM / devferq: Add generic exynos bus frequency driver and new passive governor Anand Moon
2015-12-10  0:12   ` Chanwoo Choi
2015-12-10  4:14     ` Anand Moon
2015-12-10  4:14       ` Anand Moon
2015-12-10  4:20       ` Chanwoo Choi
2015-12-10  0:57 ` Krzysztof Kozlowski
2015-12-10  1:22   ` Krzysztof Kozlowski
2015-12-10  2:16     ` Chanwoo Choi

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