From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Schocher Date: Thu, 10 Dec 2015 10:34:51 +0100 Subject: [U-Boot] [PATCH 3/3] board: atmel: siemens: clean up PLLB code In-Reply-To: <1449635383-8180-4-git-send-email-wenyou.yang@atmel.com> References: <1449635383-8180-1-git-send-email-wenyou.yang@atmel.com> <1449635383-8180-4-git-send-email-wenyou.yang@atmel.com> Message-ID: <5669473B.7050009@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Wenyou, Am 09.12.2015 um 05:29 schrieb Wenyou Yang: > Due to introducing the new PLLB clock handle functions, > use these functions to clean up the PLLB enable code. > > Signed-off-by: Wenyou Yang > --- > > board/siemens/smartweb/smartweb.c | 6 +----- > board/siemens/taurus/taurus.c | 6 +----- > 2 files changed, 2 insertions(+), 10 deletions(-) Tested on the smartweb board, see log: http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/29/steps/shell/logs/tbotlog Tested-by: Heiko Schocher bye, Heiko > > diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c > index e7ee65c..47a60a7 100644 > --- a/board/siemens/smartweb/smartweb.c > +++ b/board/siemens/smartweb/smartweb.c > @@ -115,12 +115,8 @@ static void smartweb_macb_hw_init(void) > > void at91_udp_hw_init(void) > { > - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; > - > /* Enable PLLB */ > - writel(get_pllb_init(), &pmc->pllbr); > - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) > - ; > + at91_pllb_clk_enable(get_pllb_init()); > > /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ > at91_periph_clk_enable(ATMEL_ID_UDP); > diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c > index 9374064..b0385d8 100644 > --- a/board/siemens/taurus/taurus.c > +++ b/board/siemens/taurus/taurus.c > @@ -289,12 +289,8 @@ void spi_cs_deactivate(struct spi_slave *slave) > > void at91_udp_hw_init(void) > { > - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; > - > /* Enable PLLB */ > - writel(get_pllb_init(), &pmc->pllbr); > - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) > - ; > + at91_pllb_clk_enable(get_pllb_init()); > > /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ > at91_periph_clk_enable(ATMEL_ID_UDP); > -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany