From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 15 Dec 2015 09:12:00 +0800 Subject: [U-Boot] [PATCH 5/5][v5] drivers/crypto/fsl: fix endianness issue in RNG In-Reply-To: <1449563070-5761-5-git-send-email-aneesh.bansal@freescale.com> References: <1449563070-5761-1-git-send-email-aneesh.bansal@freescale.com> <1449563070-5761-5-git-send-email-aneesh.bansal@freescale.com> Message-ID: <566F68E0.6080309@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 12/08/2015 04:24 PM, Aneesh Bansal wrote: > For Setting and clearing the bits in SEC Block registers > sec_clrbits32() and sec_setbits32() are used which work as > per endianness of CAAM block. > So these must be used with SEC register address as argument. > If the value is read in a local variable, then the functions > will not behave correctly where endianness of CAAM and core is > different. > > Signed-off-by: Aneesh Bansal > CC: Alex Porosanu > --- > Changes in v5: None > > Changes in v4: None > > Changes in v3: None > > Changes in v2: None (New Patch set created with an additional patch) Applied to fsl-qoriq master. Awaiting upstream. York