From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register Date: Tue, 15 Dec 2015 13:43:10 +0000 Message-ID: <567018EE.6000605@arm.com> References: <1450169379-12336-1-git-send-email-zhaoshenglong@huawei.com> <1450169379-12336-9-git-send-email-zhaoshenglong@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, will.deacon@arm.com, alex.bennee@linaro.org, wei@redhat.com, cov@codeaurora.org, shannon.zhao@linaro.org, peter.huangpeng@huawei.com, hangaohuai@huawei.com To: Shannon Zhao , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Return-path: Received: from foss.arm.com ([217.140.101.70]:48918 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752496AbbLONnO (ORCPT ); Tue, 15 Dec 2015 08:43:14 -0500 In-Reply-To: <1450169379-12336-9-git-send-email-zhaoshenglong@huawei.com> Sender: kvm-owner@vger.kernel.org List-ID: On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER > which is mapped to PMEVTYPERn or PMCCFILTR. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses vcpu_sys_reg() to access their values to avoid taking care > of big endian. > > When writing to these registers, create a perf_event for the selected > event type. > > Signed-off-by: Shannon Zhao > --- > arch/arm64/kvm/sys_regs.c | 154 +++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 152 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index e043224..c52ff15 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -504,6 +504,68 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) > +{ > + u64 pmcr, val; > + > + pmcr = vcpu_sys_reg(vcpu, PMCR_EL0); > + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK; > + if (idx >= val && idx != ARMV8_CYCLE_IDX) > + return false; > + > + return true; > +} > + > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 idx, reg; > + > + if (r->CRn == 9) { > + /* PMXEVTYPER_EL0 */ > + reg = 0; > + } else { > + if (!p->is_aarch32) { > + /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */ > + reg = r->reg; > + } else { > + if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) { > + reg = PMCCFILTR_EL0; > + } else { > + reg = ((r->CRm & 3) << 3) & (r->Op2 & 7); Shouldn't that be "((r->CRm & 3) << 3) | (r->Op2 & 7)"? Otherwise reg is always 0. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Tue, 15 Dec 2015 13:43:10 +0000 Subject: [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register In-Reply-To: <1450169379-12336-9-git-send-email-zhaoshenglong@huawei.com> References: <1450169379-12336-1-git-send-email-zhaoshenglong@huawei.com> <1450169379-12336-9-git-send-email-zhaoshenglong@huawei.com> Message-ID: <567018EE.6000605@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER > which is mapped to PMEVTYPERn or PMCCFILTR. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses vcpu_sys_reg() to access their values to avoid taking care > of big endian. > > When writing to these registers, create a perf_event for the selected > event type. > > Signed-off-by: Shannon Zhao > --- > arch/arm64/kvm/sys_regs.c | 154 +++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 152 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index e043224..c52ff15 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -504,6 +504,68 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > return true; > } > > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) > +{ > + u64 pmcr, val; > + > + pmcr = vcpu_sys_reg(vcpu, PMCR_EL0); > + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK; > + if (idx >= val && idx != ARMV8_CYCLE_IDX) > + return false; > + > + return true; > +} > + > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *r) > +{ > + u64 idx, reg; > + > + if (r->CRn == 9) { > + /* PMXEVTYPER_EL0 */ > + reg = 0; > + } else { > + if (!p->is_aarch32) { > + /* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */ > + reg = r->reg; > + } else { > + if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) { > + reg = PMCCFILTR_EL0; > + } else { > + reg = ((r->CRm & 3) << 3) & (r->Op2 & 7); Shouldn't that be "((r->CRm & 3) << 3) | (r->Op2 & 7)"? Otherwise reg is always 0. Thanks, M. -- Jazz is not dead. It just smells funny...