From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH v2 0/2] Support of RO MMCFG access for PVH/HVMlite dom0s Date: Fri, 18 Dec 2015 08:53:43 -0500 Message-ID: <56740FE7.60301@oracle.com> References: <1450383771-3636-1-git-send-email-boris.ostrovsky@oracle.com> <5673E9F202000078000C10EC@prv-mh.provo.novell.com> <567403D4.9070708@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <567403D4.9070708@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Andrew Cooper , Jan Beulich Cc: keir@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 12/18/2015 08:02 AM, Andrew Cooper wrote: > On 18/12/15 10:11, Jan Beulich wrote: >>>>> On 17.12.15 at 21:22, wrote: >>> * Left non-MMCFG RO accesses unhandled (we havent't encountered those accesses >>> yet with PVH dom0 and it's probably better to fault on them and investigate >>> whether they are guest's issues). >> I seriously question this being a good approach, > I concur. All accesses should be terminated somehow, even if this is > the hypervisor dropping writes and completing reads with ~0's. > > This is the expected behaviour from the x86 architecture. OK, I'll add that in. To answer Jan's question, I did try 'vga=keep' and that worked fine. (I couldn't test AMD IOMMU because we don't support PVH there and I don't have the other HW that he mentioned). -boris