From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rhyland Klein Subject: Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC Date: Fri, 18 Dec 2015 11:48:58 -0500 Message-ID: <567438FA.2030405@nvidia.com> References: <1450446328-6414-1-git-send-email-jonathanh@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1450446328-6414-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jon Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Stephen Warren , Thierry Reding , Alexandre Courbot Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On 12/18/2015 8:45 AM, Jon Hunter wrote: > The EMC clock sources for tegra210 currently incorrectly include pll_c2 > and pll_c3. However, both of these should have been pll_mb as shown in > the TRM. If tegra210 happens to be configured such that the pll_mb is the > default clock for the EMC, as configured by the bootloader, then this will > cause a system hang on boot. This is because the kernel will disable the > pll_mb when disabling unused clock as it appears to be unused when it is > not. > > Also add the additional pll_p clock source for the EMC. > > Signed-off-by: Jon Hunter > --- > drivers/clk/tegra/clk-tegra210.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index 58514c44ea83..849be30b52bf 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = { > }; > > static const char *mux_pllmcp_clkm[] = { > - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", > + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", > + "pll_p", > }; > #define mux_pllmcp_clkm_idx NULL > > Acked-by: Rhyland Klein -rhyland -- nvpublic From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933027AbbLRQtQ (ORCPT ); Fri, 18 Dec 2015 11:49:16 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6274 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932951AbbLRQtO (ORCPT ); Fri, 18 Dec 2015 11:49:14 -0500 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 18 Dec 2015 08:45:39 -0800 Subject: Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC To: Jon Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Stephen Warren , Thierry Reding , Alexandre Courbot References: <1450446328-6414-1-git-send-email-jonathanh@nvidia.com> CC: , , From: Rhyland Klein Message-ID: <567438FA.2030405@nvidia.com> Date: Fri, 18 Dec 2015 11:48:58 -0500 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <1450446328-6414-1-git-send-email-jonathanh@nvidia.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/18/2015 8:45 AM, Jon Hunter wrote: > The EMC clock sources for tegra210 currently incorrectly include pll_c2 > and pll_c3. However, both of these should have been pll_mb as shown in > the TRM. If tegra210 happens to be configured such that the pll_mb is the > default clock for the EMC, as configured by the bootloader, then this will > cause a system hang on boot. This is because the kernel will disable the > pll_mb when disabling unused clock as it appears to be unused when it is > not. > > Also add the additional pll_p clock source for the EMC. > > Signed-off-by: Jon Hunter > --- > drivers/clk/tegra/clk-tegra210.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index 58514c44ea83..849be30b52bf 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = { > }; > > static const char *mux_pllmcp_clkm[] = { > - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", > + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", > + "pll_p", > }; > #define mux_pllmcp_clkm_idx NULL > > Acked-by: Rhyland Klein -rhyland -- nvpublic