From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932692AbbLVTSN (ORCPT ); Tue, 22 Dec 2015 14:18:13 -0500 Received: from mail-bn1on0093.outbound.protection.outlook.com ([157.56.110.93]:63392 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752144AbbLVTSL (ORCPT ); Tue, 22 Dec 2015 14:18:11 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=David.Daney@caviumnetworks.com; Message-ID: <5679A1E9.3050902@caviumnetworks.com> Date: Tue, 22 Dec 2015 11:18:01 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Will Deacon CC: David Daney , , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , , , Marc Zyngier , Bjorn Helgaas , , Arnd Bergmann , David Daney Subject: Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors. References: <1450749222-15966-1-git-send-email-ddaney.cavm@gmail.com> <1450749222-15966-3-git-send-email-ddaney.cavm@gmail.com> <20151222100352.GC32623@arm.com> In-Reply-To: <20151222100352.GC32623@arm.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [64.2.3.194] X-ClientProxiedBy: SN1PR07CA0020.namprd07.prod.outlook.com (25.162.170.158) To DM3PR07MB2140.namprd07.prod.outlook.com (25.164.4.146) X-Microsoft-Exchange-Diagnostics: 1;DM3PR07MB2140;2:65IeOmLZVe+Gs6i8XKZ+RtFVnegmnGHuL3qtscYDl3uECkdvpNX4YUGhptg0x71/Tg+cew1kPEsxAb73zgZIAdcv2xXS5+x6vsczfo/fIKsXhuEQcFvzlytuxX3Z9x3bJDFnHDAep1IWCpFqbftWxg==;3:J2z22GZWjcm1N9uNyCGKGiDEUaD1mRg99ynX0JJe4AfyLlP9xQ6517xTCfZYLma5e8bnLvgYkIWbPt3H6dejzAFg5svEqWmq80Bl77CDmoHxpYplDvw7a1mIt8rnbVtv;25:686eooytzlRQkANPi32EsxU6mykVbBxKqkaM6UeHb4cl6M4jc723nDXn9lnHZyg6cQWwK9r5xuQZswDvzG5FFJdWazuS/sq5IAsJODIHXvfYgm/Uw/GEMcqxuALbmLhKq+zY0c1L1bPMh8XCUinrSLtILAwjinREyowqTagEYmW+GW8mXqdPtRDt+WF1b5e0gDvh3LUoALHqfOnojIMwrih+heGEun9fq4T3DVTcN8ebbrw29Jacyss6JJAdCqlqwAEJejY2mDxGFpFZNeLmVQ== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM3PR07MB2140; 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X-Microsoft-Exchange-Diagnostics: =?iso-8859-1?Q?1;DM3PR07MB2140;23:sRgtkSOf0cw/I6lLgVBeyNccqW2Qg98hbpF3mfZ?= =?iso-8859-1?Q?jlipzD7MK6azLBjLbfApOpXtd3jNweqw4I/RFZXC/WkD17LetNnstvyXQQ?= =?iso-8859-1?Q?cLethGHela8HRRYHbWLSCFxeiNozZtBlsihavj8P8jt2XUqzaw0XVVPwrs?= =?iso-8859-1?Q?HfytxC7SVE6TDh41ECAvfGM9Afa2zRpRcgkAPGo4Y9BTn7cWU/o2o8DvPg?= =?iso-8859-1?Q?i8RKCsDEle9pcPL+Xdd7SDWuwKruURpIVwYglgrA6MJ4xieAawWkUq+Az9?= =?iso-8859-1?Q?XeolvhvcAAGUSZkwjsJt090MDSXtKJVkRvBwsMI4aqj0I5du/N2DB6X/In?= =?iso-8859-1?Q?EmjWcROa7J/D3DVuDrs/vaadCW01lN41ltceQt9dU/mg22nYK+ZeCwxj1m?= =?iso-8859-1?Q?4T9lm6gNtIv33zQuZv//1ZNp9cwhi98tzOAklj7OC/54V0wXbznqse5r+i?= =?iso-8859-1?Q?6IlE8JPLmc2Ju+Pojg8mFxi4ymvtBQFvmBxCyF6PBgjqGIo9V1kshA20M6?= =?iso-8859-1?Q?fArE0u65kppdTZVB4BU4E3VJ4NJFcxTmsEoiQG/vc/sW2v9+EhCurUQEFX?= =?iso-8859-1?Q?J5R3e8XVoploFGC7PJ4aRO0a456OX3xa4Hwowg/+wLXMI1AsUeruWu1Imd?= =?iso-8859-1?Q?C2dq78korzpesO3l45YXIfpU5gIRaXZ7FCaZ7/I0aUnOtvs83rs2n/SBAb?= =?iso-8859-1?Q?wEJJB1iYkE+sYF69RJwRBHyJjkZaZQbGMH2+GswG8OiHC5ybBGHRtI129f?= =?iso-8859-1?Q?NbtZfWV0FMN3zZiBaqNPjT2jXb9RsMJbjAO0iCfXckdcM7F279IYbP1BMU?= =?iso-8859-1?Q?FcwZymov0TfUlVWFUN8hcn8Aqp57recSMUmOklLaEc9X8Qjy8Y8tih15ix?= =?iso-8859-1?Q?V8PtI9xRk5w25n2fA/AY/Zl9h9xBBi0dDU8cWwXwR3F8wOg14Hwv5UG6RE?= =?iso-8859-1?Q?JlPx975N5EzJvOu6p9ckCfjDwMcX30Ks83+E3Bi8AK1xiXtZy9MSK7G019?= =?iso-8859-1?Q?wA+GOCQyxBEgrKTYEIcgONDa0e5hcgzDMQURZCtN2l6Hnz3OgN1XE7YLW6?= =?iso-8859-1?Q?7eS+/OXP4ej8LR5am6Jt+/a8FRy7Q66RZ1YRTSqpb37VzwT+31c5MqNbJZ?= =?iso-8859-1?Q?0nVAFanWsiGzL9SPijcDBAIQAtQB2Wz06cU7fUsU1JMpTUNtz/kWlNLAah?= =?iso-8859-1?Q?GoXEaTFNKnGpz8EVNNtgqwl7HDSOrDIHhE2TSLi2KWJHWaNmRaZo+XhKHY?= =?iso-8859-1?Q?ipWN/jc3Z4A5IzlZ+7eMstcAw8HL589QSf7uN0XVEXCpESnCkEgHB3nYV/?= =?iso-8859-1?Q?kHbkI7mp95Ly5wCmtecW3Nr/BEaTtzELfKB9tquSQNhC9WvJGBzsxExBNn?= =?iso-8859-1?Q?2dkekOFAyLitcQIlYFhS9diqXS/pzMwfvA8pTHkD2Fg/IFZ824mA8oQlXP?= =?iso-8859-1?Q?uvVuReiPWI8d130PuiZ2gK/DXFTlaYh9oKw+xGlOKjat0NyM0AvkxHSTZw?= =?iso-8859-1?Q?t0VueT5bADaiKo0BE3Zo=3D?= X-Microsoft-Exchange-Diagnostics: 1;DM3PR07MB2140;5:sOMJdgvYBObCIbjnTbrI7B5zu84U3ZyLfeiaQSNeMrg0LXiL5BAz3mDi0HF4nW8DAG5PerQav3KoIl+jdmPFAtLOdippmNC3Ls7RIzqWCRNjmXBdSIli1IlhiRd119oMPxCaeHRIsQ5sf6jGst5Tcg==;24:WXPKI4P+DU5SdLOsGWIPTGBTeje347zJtYLKXmW1OHccxpuf2RH42fRundt8vSUGVWUhZkwfz8zrMoHDcggKzGVygaOkWMFEuN9tz7Fnm7A= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Dec 2015 19:18:06.1711 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR07MB2140 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/22/2015 02:03 AM, Will Deacon wrote: > On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote: >> From: David Daney >> >> Some Cavium ThunderX processors require quirky access methods for the >> config space of the PCIe bridge. Add a driver to provide these config >> space accessor functions. The pci-host-generic driver code is used to >> configure the PCI machinery. >> >> Signed-off-by: David Daney >> --- >> .../devicetree/bindings/pci/pcie-thunder-pem.txt | 43 ++++ >> drivers/pci/host/Kconfig | 6 + >> drivers/pci/host/Makefile | 1 + >> drivers/pci/host/pcie-thunder-pem.c | 283 +++++++++++++++++++++ >> 4 files changed, 333 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> create mode 100644 drivers/pci/host/pcie-thunder-pem.c >> >> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> new file mode 100644 >> index 0000000..66824d5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> @@ -0,0 +1,43 @@ >> +* ThunderX PEM PCIe host controller >> + >> +Firmware-initialized PCIe host controller found on some Cavium >> +ThunderX processors. >> + >> +The properties and their meanings are identical to those described in >> +host-heneric-pci.txt except as listed below. >> + >> +Properties of the host controller node that differ from >> +host-heneric-pci.txt: > > Consistently odd typo (s/heneric/generic/)! > I'm not sure how I managed to do that. I will fix these and resend. >> + >> +- compatible : Must be "cavium,pci-host-thunder-pem" >> + >> +- reg : Two entries: First the configuration space for down >> + stream devices base address and size, as accessed >> + from the parent bus. Second, the register bank of >> + the PEM device PCIe bridge. >> + >> +Example: >> + >> + pem2 { >> + compatible = "cavium,pci-host-thunder-pem"; >> + device_type = "pci"; >> + msi-parent = <&its>; >> + msi-map = <0 &its 0x10000 0x10000>; >> + bus-range = <0x8f 0xc7>; >> + #size-cells = <2>; >> + #address-cells = <3>; >> + >> + reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ >> + <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */ >> + ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ >> + <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ >> + <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ >> + <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */ >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ >> + <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ >> + <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ >> + <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ >> + }; >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig >> index f131ba9..16ed9c3 100644 >> --- a/drivers/pci/host/Kconfig >> +++ b/drivers/pci/host/Kconfig >> @@ -172,4 +172,10 @@ config PCI_HISI >> help >> Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC >> >> +config PCIE_HOST_THUNDER_PEM >> + bool "Cavium Thunder PCIe controller to off-chip devices" >> + depends on PCI_HOST_GENERIC && ARM64 > > || COMPILE_TEST ? > > (or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT) Yes, we must use writeq in the driver, I will change it to ||(COMPILE_TEST && 64BIT) Thanks, David Daney > > Will > From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Daney Subject: Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors. Date: Tue, 22 Dec 2015 11:18:01 -0800 Message-ID: <5679A1E9.3050902@caviumnetworks.com> References: <1450749222-15966-1-git-send-email-ddaney.cavm@gmail.com> <1450749222-15966-3-git-send-email-ddaney.cavm@gmail.com> <20151222100352.GC32623@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20151222100352.GC32623@arm.com> Sender: linux-pci-owner@vger.kernel.org To: Will Deacon Cc: David Daney , linux-kernel@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Marc Zyngier , Bjorn Helgaas , linux-pci@vger.kernel.org, Arnd Bergmann , David Daney List-Id: devicetree@vger.kernel.org On 12/22/2015 02:03 AM, Will Deacon wrote: > On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote: >> From: David Daney >> >> Some Cavium ThunderX processors require quirky access methods for the >> config space of the PCIe bridge. Add a driver to provide these config >> space accessor functions. The pci-host-generic driver code is used to >> configure the PCI machinery. >> >> Signed-off-by: David Daney >> --- >> .../devicetree/bindings/pci/pcie-thunder-pem.txt | 43 ++++ >> drivers/pci/host/Kconfig | 6 + >> drivers/pci/host/Makefile | 1 + >> drivers/pci/host/pcie-thunder-pem.c | 283 +++++++++++++++++++++ >> 4 files changed, 333 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> create mode 100644 drivers/pci/host/pcie-thunder-pem.c >> >> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> new file mode 100644 >> index 0000000..66824d5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> @@ -0,0 +1,43 @@ >> +* ThunderX PEM PCIe host controller >> + >> +Firmware-initialized PCIe host controller found on some Cavium >> +ThunderX processors. >> + >> +The properties and their meanings are identical to those described in >> +host-heneric-pci.txt except as listed below. >> + >> +Properties of the host controller node that differ from >> +host-heneric-pci.txt: > > Consistently odd typo (s/heneric/generic/)! > I'm not sure how I managed to do that. I will fix these and resend. >> + >> +- compatible : Must be "cavium,pci-host-thunder-pem" >> + >> +- reg : Two entries: First the configuration space for down >> + stream devices base address and size, as accessed >> + from the parent bus. Second, the register bank of >> + the PEM device PCIe bridge. >> + >> +Example: >> + >> + pem2 { >> + compatible = "cavium,pci-host-thunder-pem"; >> + device_type = "pci"; >> + msi-parent = <&its>; >> + msi-map = <0 &its 0x10000 0x10000>; >> + bus-range = <0x8f 0xc7>; >> + #size-cells = <2>; >> + #address-cells = <3>; >> + >> + reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ >> + <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */ >> + ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ >> + <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ >> + <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ >> + <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */ >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ >> + <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ >> + <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ >> + <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ >> + }; >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig >> index f131ba9..16ed9c3 100644 >> --- a/drivers/pci/host/Kconfig >> +++ b/drivers/pci/host/Kconfig >> @@ -172,4 +172,10 @@ config PCI_HISI >> help >> Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC >> >> +config PCIE_HOST_THUNDER_PEM >> + bool "Cavium Thunder PCIe controller to off-chip devices" >> + depends on PCI_HOST_GENERIC && ARM64 > > || COMPILE_TEST ? > > (or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT) Yes, we must use writeq in the driver, I will change it to ||(COMPILE_TEST && 64BIT) Thanks, David Daney > > Will > From mboxrd@z Thu Jan 1 00:00:00 1970 From: ddaney@caviumnetworks.com (David Daney) Date: Tue, 22 Dec 2015 11:18:01 -0800 Subject: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors. In-Reply-To: <20151222100352.GC32623@arm.com> References: <1450749222-15966-1-git-send-email-ddaney.cavm@gmail.com> <1450749222-15966-3-git-send-email-ddaney.cavm@gmail.com> <20151222100352.GC32623@arm.com> Message-ID: <5679A1E9.3050902@caviumnetworks.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/22/2015 02:03 AM, Will Deacon wrote: > On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote: >> From: David Daney >> >> Some Cavium ThunderX processors require quirky access methods for the >> config space of the PCIe bridge. Add a driver to provide these config >> space accessor functions. The pci-host-generic driver code is used to >> configure the PCI machinery. >> >> Signed-off-by: David Daney >> --- >> .../devicetree/bindings/pci/pcie-thunder-pem.txt | 43 ++++ >> drivers/pci/host/Kconfig | 6 + >> drivers/pci/host/Makefile | 1 + >> drivers/pci/host/pcie-thunder-pem.c | 283 +++++++++++++++++++++ >> 4 files changed, 333 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> create mode 100644 drivers/pci/host/pcie-thunder-pem.c >> >> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> new file mode 100644 >> index 0000000..66824d5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt >> @@ -0,0 +1,43 @@ >> +* ThunderX PEM PCIe host controller >> + >> +Firmware-initialized PCIe host controller found on some Cavium >> +ThunderX processors. >> + >> +The properties and their meanings are identical to those described in >> +host-heneric-pci.txt except as listed below. >> + >> +Properties of the host controller node that differ from >> +host-heneric-pci.txt: > > Consistently odd typo (s/heneric/generic/)! > I'm not sure how I managed to do that. I will fix these and resend. >> + >> +- compatible : Must be "cavium,pci-host-thunder-pem" >> + >> +- reg : Two entries: First the configuration space for down >> + stream devices base address and size, as accessed >> + from the parent bus. Second, the register bank of >> + the PEM device PCIe bridge. >> + >> +Example: >> + >> + pem2 { >> + compatible = "cavium,pci-host-thunder-pem"; >> + device_type = "pci"; >> + msi-parent = <&its>; >> + msi-map = <0 &its 0x10000 0x10000>; >> + bus-range = <0x8f 0xc7>; >> + #size-cells = <2>; >> + #address-cells = <3>; >> + >> + reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ >> + <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */ >> + ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ >> + <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ >> + <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ >> + <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */ >> + >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ >> + <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ >> + <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ >> + <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ >> + }; >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig >> index f131ba9..16ed9c3 100644 >> --- a/drivers/pci/host/Kconfig >> +++ b/drivers/pci/host/Kconfig >> @@ -172,4 +172,10 @@ config PCI_HISI >> help >> Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC >> >> +config PCIE_HOST_THUNDER_PEM >> + bool "Cavium Thunder PCIe controller to off-chip devices" >> + depends on PCI_HOST_GENERIC && ARM64 > > || COMPILE_TEST ? > > (or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT) Yes, we must use writeq in the driver, I will change it to ||(COMPILE_TEST && 64BIT) Thanks, David Daney > > Will >