From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752325AbcAGObe (ORCPT ); Thu, 7 Jan 2016 09:31:34 -0500 Received: from foss.arm.com ([217.140.101.70]:40092 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750722AbcAGObc (ORCPT ); Thu, 7 Jan 2016 09:31:32 -0500 Message-ID: <568E76BE.3010702@arm.com> Date: Thu, 07 Jan 2016 14:31:26 +0000 From: Marc Zyngier Organization: ARM Ltd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 MIME-Version: 1.0 To: Daniel Thompson , Thomas Gleixner , Jason Cooper , Russell King CC: Will Deacon , Catalin Marinas , Stephen Boyd , John Stultz , Steven Rostedt , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, Sumit Semwal , Dirk Behme , Daniel Drake , Dmitry Pervushin , Tim Sander , Petr Mladek Subject: Re: [PATCH 4.4-rc5 v22 1/4] irqchip: gic: Optimize locking in gic_raise_softirq References: <1450644757-18734-1-git-send-email-daniel.thompson@linaro.org> <1450644757-18734-2-git-send-email-daniel.thompson@linaro.org> In-Reply-To: <1450644757-18734-2-git-send-email-daniel.thompson@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/12/15 20:52, Daniel Thompson wrote: > Currently gic_raise_softirq() is locked using irq_controller_lock. > This lock is primarily used to make register read-modify-write sequences > atomic but gic_raise_softirq() uses it instead to ensure that the > big.LITTLE migration logic can figure out when it is safe to migrate > interrupts between physical cores. > > This is sub-optimal in closely related ways: > > 1. No locking at all is required on systems where the b.L switcher is > not configured. > > 2. Finer grain locking can be used on systems where the b.L switcher is > present. > > This patch resolves both of the above by introducing a separate finer > grain lock and providing conditionally compiled inlines to lock/unlock > it. > > Signed-off-by: Daniel Thompson > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Russell King > Cc: Marc Zyngier > Acked-by: Nicolas Pitre Acked-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Thu, 07 Jan 2016 14:31:26 +0000 Subject: [PATCH 4.4-rc5 v22 1/4] irqchip: gic: Optimize locking in gic_raise_softirq In-Reply-To: <1450644757-18734-2-git-send-email-daniel.thompson@linaro.org> References: <1450644757-18734-1-git-send-email-daniel.thompson@linaro.org> <1450644757-18734-2-git-send-email-daniel.thompson@linaro.org> Message-ID: <568E76BE.3010702@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 20/12/15 20:52, Daniel Thompson wrote: > Currently gic_raise_softirq() is locked using irq_controller_lock. > This lock is primarily used to make register read-modify-write sequences > atomic but gic_raise_softirq() uses it instead to ensure that the > big.LITTLE migration logic can figure out when it is safe to migrate > interrupts between physical cores. > > This is sub-optimal in closely related ways: > > 1. No locking at all is required on systems where the b.L switcher is > not configured. > > 2. Finer grain locking can be used on systems where the b.L switcher is > present. > > This patch resolves both of the above by introducing a separate finer > grain lock and providing conditionally compiled inlines to lock/unlock > it. > > Signed-off-by: Daniel Thompson > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Russell King > Cc: Marc Zyngier > Acked-by: Nicolas Pitre Acked-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny...