On 12/24/2015 06:42 PM, Damien Riegel wrote:
> Technologic Systems provides an IP compatible with the SJA1000,
> instantiated in an FPGA. Because of some bus widths issue, access to
> registers is made through a "window" that works like this:
> 
>     base + 0x0: address to read/write
>     base + 0x2: 8-bit register value

Why do you use io{read,write}16 if it's a 8 bit register?

Marc

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