All of lore.kernel.org
 help / color / mirror / Atom feed
From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Make various system registers visible to EL3
Date: Wed, 20 Jan 2016 20:22:13 +0300	[thread overview]
Message-ID: <569FC245.4030103@gmail.com> (raw)
In-Reply-To: <1453227802-9991-1-git-send-email-peter.maydell@linaro.org>

On 19.01.2016 21:23, Peter Maydell wrote:
> The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ,
> SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from
> EL3 even if the CPU has no EL2 (unlike some others which are RES0
> from EL3 in that configuration).  Move them from el2_cp_reginfo[] to
> v8_cp_reginfo[] so they are always present.

Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>

>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/helper.c | 58 ++++++++++++++++++++++++++---------------------------
>  1 file changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index e8ede3f..999c617 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3166,6 +3166,35 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>        .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
>        .access = PL2_RW, .accessfn = fpexc32_access },
> +    { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
> +      .access = PL2_RW, .resetvalue = 0,
> +      .writefn = dacr_write, .raw_writefn = raw_write,
> +      .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
> +    { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
> +      .access = PL2_RW, .resetvalue = 0,
> +      .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
> +    { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_ALIAS,
> +      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
> +      .access = PL2_RW,
> +      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
> +    { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_ALIAS,
> +      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
> +      .access = PL2_RW,
> +      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
> +    { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_ALIAS,
> +      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
> +      .access = PL2_RW,
> +      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
> +    { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_ALIAS,
> +      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
> +      .access = PL2_RW,
> +      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
>      REGINFO_SENTINEL
>  };
>  
> @@ -3293,11 +3322,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
>        .writefn = hcr_write },
> -    { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
> -      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
> -      .access = PL2_RW, .resetvalue = 0,
> -      .writefn = dacr_write, .raw_writefn = raw_write,
> -      .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
>      { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
>        .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
> @@ -3307,10 +3331,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
> -    { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
> -      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
> -      .access = PL2_RW, .resetvalue = 0,
> -      .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
>      { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
> @@ -3319,26 +3339,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
>        .access = PL2_RW,
>        .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
> -    { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_ALIAS,
> -      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
> -      .access = PL2_RW,
> -      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
> -    { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_ALIAS,
> -      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
> -      .access = PL2_RW,
> -      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
> -    { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_ALIAS,
> -      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
> -      .access = PL2_RW,
> -      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
> -    { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_ALIAS,
> -      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
> -      .access = PL2_RW,
> -      .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
>      { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .writefn = vbar_write,

      parent reply	other threads:[~2016-01-20 17:22 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-19 18:23 [Qemu-devel] [PATCH] target-arm: Make various system registers visible to EL3 Peter Maydell
2016-01-20 12:19 ` Edgar E. Iglesias
2016-01-20 17:22 ` Sergey Fedorov [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=569FC245.4030103@gmail.com \
    --to=serge.fdrv@gmail.com \
    --cc=patches@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.