From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aNnsU-0004dD-Kf for qemu-devel@nongnu.org; Mon, 25 Jan 2016 15:36:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aNnsR-0004CU-Em for qemu-devel@nongnu.org; Mon, 25 Jan 2016 15:36:46 -0500 References: <1453698952-32092-1-git-send-email-david@gibson.dropbear.id.au> <20160125111040.GH32205@voom.redhat.com> From: Alexander Graf Message-ID: <56A68758.8090805@suse.de> Date: Mon, 25 Jan 2016 21:36:40 +0100 MIME-Version: 1.0 In-Reply-To: <20160125111040.GH32205@voom.redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 00/10] Clean up page size handling for ppc 64-bit hash MMUs with TCG List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , benh@kernel.crashing.org Cc: aik@ozlabs.ru, lvivier@redhat.com, thuth@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 01/25/2016 12:10 PM, David Gibson wrote: > On Mon, Jan 25, 2016 at 04:15:42PM +1100, David Gibson wrote: >> Encoding of page sizes on 64-bit hash MMUs for Power is rather arcane, >> involving control bits in both the SLB and HPTE. At present we >> support a few of the options, but far fewer than real hardware. >> >> We're able to get away with that in practice, because guests use a >> device tree property to determine which page sizes are available and >> we are setting that to match. However, the fact that the actual code >> doesn't necessarily what we put into the table of available page sizes >> is another ugliness. >> >> This series makes a number of cleanups to the page size handling. The >> upshot is that afterwards the softmmu code operates off the same page >> size encoding table that is advertised to the guests, ensuring that >> they will be in sync. >> >> Finally, we extend the table of allowed sizes for POWER7 and POWER8 to >> include the options allowed in hardware (including MPSS). We can fix >> other hash MMU based CPUs in future if anyone cares enough. >> >> Please review, and I'll fold into ppc-for-2.6 for my next pull. > Bother, somehow missed a serious bug in here that's causing > oops-on-boot. Sorry, still tracking it down. I still have no idea where your bug is (bisect probably should get you there pretty quick), but the overall concept sounds very reasonable to me. Please benchmark performance before and after in the next cover letter also :) Reviewed-by: Alexander Graf Alex