From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965042AbcAZJ7a (ORCPT ); Tue, 26 Jan 2016 04:59:30 -0500 Received: from mail-sn1nam02on0047.outbound.protection.outlook.com ([104.47.36.47]:64810 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S964896AbcAZJ7Y (ORCPT ); Tue, 26 Jan 2016 04:59:24 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; arndb.de; dkim=none (message not signed) header.d=none;arndb.de; dmarc=bestguesspass action=none header.from=xilinx.com; Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze To: Arnd Bergmann , Bharat Kumar Gogada References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> CC: , , , , , , , , , , , , , , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri From: Michal Simek X-Enigmail-Draft-Status: N1110 Message-ID: <56A74370.4090000@xilinx.com> Date: Tue, 26 Jan 2016 10:59:12 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22090.002 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(24454002)(164054003)(189002)(199003)(54356999)(87266999)(230700001)(5001960100002)(106466001)(4001430100002)(2950100001)(1096002)(1220700001)(77096005)(6806005)(11100500001)(107886002)(50986999)(5008740100001)(65956001)(586003)(65816999)(76176999)(19580395003)(5001770100001)(33656002)(81156007)(4001350100001)(36386004)(47776003)(65806001)(189998001)(87936001)(19580405001)(2906002)(50466002)(4001450100002)(83506001)(63266004)(80316001)(4326007)(36756003)(64126003)(23746002)(86362001)(92566002)(59896002)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT162;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: a7f4f93d-d782-4843-a922-08d326375d4c X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT162;UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(520078)(5005006)(8121501046)(13023025)(13024025)(13015025)(13018025)(13017025)(3002001)(10201501046);SRVR:CY1NAM02HT162;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT162; X-Forefront-PRVS: 08331F819E X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2016 09:59:21.0202 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT162 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12.1.2016 23:27, Arnd Bergmann wrote: > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: >> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both >> Zynq and Microblaze Architectures. >> With these modifications drivers/pci/host/pcie-xilinx.c, will >> work on both Zynq and Microblaze Architectures. >> >> Signed-off-by: Bharat Kumar Gogada >> Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three > unrelated things here. > >> --- >> Changes: >> Changed Total number of MSI IRQ count logic according to both architectures. >> Updated MSI assigning functions accordingly to new count. >> Modified irq_domain_add_linear with new MSI IRQ count. >> Added #ifdef to pci_fixup_irqs which is ARM specific API. >> --- >> drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c >> index 3e3757f..1981948 100644 >> --- a/drivers/pci/host/pcie-xilinx.c >> +++ b/drivers/pci/host/pcie-xilinx.c >> @@ -92,7 +92,12 @@ >> #define ECAM_DEV_NUM_SHIFT 12 >> >> /* Number of MSI IRQs */ >> -#define XILINX_NUM_MSI_IRQS 128 >> +#define XILINX_NUM_MSI_IRQS 128 >> +#ifdef CONFIG_ARM >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS >> +#else >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) >> +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? Arnd: What was the story regarding NR_IRQS? I remember some discussion about it but just forget. Default value in include/asm-generic/irq.h is 64. Current value is 32 because microblaze primary interrupt controller is axi_intc core which has up to 32 input lines. Thanks, Michal From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Subject: Re: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 26 Jan 2016 10:59:12 +0100 Message-ID: <56A74370.4090000@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> Sender: linux-kernel-owner@vger.kernel.org To: Arnd Bergmann , Bharat Kumar Gogada Cc: bhelgaas@google.com, lorenzo.pieralisi@arm.com, paul.burton@imgtec.com, yinghai@kernel.org, wangyijing@huawei.com, robh@kernel.org, russell.joyce@york.ac.uk, sorenb@xilinx.com, jiang.liu@linux.intel.com, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bharat Kumar Gogada , Ravi Kiran Gummaluri List-Id: devicetree@vger.kernel.org On 12.1.2016 23:27, Arnd Bergmann wrote: > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: >> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both >> Zynq and Microblaze Architectures. >> With these modifications drivers/pci/host/pcie-xilinx.c, will >> work on both Zynq and Microblaze Architectures. >> >> Signed-off-by: Bharat Kumar Gogada >> Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three > unrelated things here. > >> --- >> Changes: >> Changed Total number of MSI IRQ count logic according to both architectures. >> Updated MSI assigning functions accordingly to new count. >> Modified irq_domain_add_linear with new MSI IRQ count. >> Added #ifdef to pci_fixup_irqs which is ARM specific API. >> --- >> drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c >> index 3e3757f..1981948 100644 >> --- a/drivers/pci/host/pcie-xilinx.c >> +++ b/drivers/pci/host/pcie-xilinx.c >> @@ -92,7 +92,12 @@ >> #define ECAM_DEV_NUM_SHIFT 12 >> >> /* Number of MSI IRQs */ >> -#define XILINX_NUM_MSI_IRQS 128 >> +#define XILINX_NUM_MSI_IRQS 128 >> +#ifdef CONFIG_ARM >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS >> +#else >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) >> +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? Arnd: What was the story regarding NR_IRQS? I remember some discussion about it but just forget. Default value in include/asm-generic/irq.h is 64. Current value is 32 because microblaze primary interrupt controller is axi_intc core which has up to 32 input lines. Thanks, Michal From mboxrd@z Thu Jan 1 00:00:00 1970 From: michal.simek@xilinx.com (Michal Simek) Date: Tue, 26 Jan 2016 10:59:12 +0100 Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze In-Reply-To: <4734542.KZZp0TeeeM@wuerfel> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> <1452620173-4905-4-git-send-email-bharatku@xilinx.com> <4734542.KZZp0TeeeM@wuerfel> Message-ID: <56A74370.4090000@xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12.1.2016 23:27, Arnd Bergmann wrote: > On Tuesday 12 January 2016 23:06:11 Bharat Kumar Gogada wrote: >> Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both >> Zynq and Microblaze Architectures. >> With these modifications drivers/pci/host/pcie-xilinx.c, will >> work on both Zynq and Microblaze Architectures. >> >> Signed-off-by: Bharat Kumar Gogada >> Signed-off-by: Ravi Kiran Gummaluri > > I think this patch should be split into three, as you are doing three > unrelated things here. > >> --- >> Changes: >> Changed Total number of MSI IRQ count logic according to both architectures. >> Updated MSI assigning functions accordingly to new count. >> Modified irq_domain_add_linear with new MSI IRQ count. >> Added #ifdef to pci_fixup_irqs which is ARM specific API. >> --- >> drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c >> index 3e3757f..1981948 100644 >> --- a/drivers/pci/host/pcie-xilinx.c >> +++ b/drivers/pci/host/pcie-xilinx.c >> @@ -92,7 +92,12 @@ >> #define ECAM_DEV_NUM_SHIFT 12 >> >> /* Number of MSI IRQs */ >> -#define XILINX_NUM_MSI_IRQS 128 >> +#define XILINX_NUM_MSI_IRQS 128 >> +#ifdef CONFIG_ARM >> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS >> +#else >> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) >> +#endif > > Something looks wrong here in the microblaze variant. What does NR_IRQS > have to do with it? Arnd: What was the story regarding NR_IRQS? I remember some discussion about it but just forget. Default value in include/asm-generic/irq.h is 64. Current value is 32 because microblaze primary interrupt controller is axi_intc core which has up to 32 input lines. Thanks, Michal