From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOUMo-000194-8S for qemu-devel@nongnu.org; Wed, 27 Jan 2016 12:58:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aOUMk-0002EW-8p for qemu-devel@nongnu.org; Wed, 27 Jan 2016 12:58:54 -0500 References: <1453889591-30968-1-git-send-email-david@gibson.dropbear.id.au> <1453889591-30968-8-git-send-email-david@gibson.dropbear.id.au> From: Laurent Vivier Message-ID: <56A90553.4000106@redhat.com> Date: Wed, 27 Jan 2016 18:58:43 +0100 MIME-Version: 1.0 In-Reply-To: <1453889591-30968-8-git-send-email-david@gibson.dropbear.id.au> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCHv2 07/10] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , benh@kernel.crashing.org Cc: aik@ozlabs.ru, thuth@redhat.com, qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org On 27/01/2016 11:13, David Gibson wrote: > Currently both the tlbiva instruction (used on 44x chips) and the tlbie > instruction (used on hash MMU chips) are both handled via > ppc_tlb_invalidate_one(). This is silly, because they're invoked from > different places, and do different things. > > Clean this up by separating out the tlbiva instruction into its own > handling. In fact the implementation is only a stub anyway. > > Signed-off-by: David Gibson > --- > target-ppc/helper.h | 1 + > target-ppc/mmu_helper.c | 14 ++++++++++---- > target-ppc/translate.c | 2 +- > 3 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 869be15..e5a8f7b 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -544,6 +544,7 @@ DEF_HELPER_2(74xx_tlbd, void, env, tl) > DEF_HELPER_2(74xx_tlbi, void, env, tl) > DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env) > DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl) > +DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl) > #if defined(TARGET_PPC64) > DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl) > DEF_HELPER_2(load_slb_esid, tl, env, tl) > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index 82ebe5d..e9e0edb 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1971,10 +1971,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) > ppc6xx_tlb_invalidate_virt(env, addr, 1); > } > break; > - case POWERPC_MMU_BOOKE: > - /* XXX: TODO */ > - cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); > - break; > case POWERPC_MMU_32B: > case POWERPC_MMU_601: > /* tlbie invalidate TLBs for all segments */ > @@ -2116,6 +2112,16 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr) > ppc_tlb_invalidate_one(env, addr); > } > > +void helper_tlbiva(CPUPPCState *env, target_ulong addr) > +{ > + PowerPCCPU *cpu = ppc_env_get_cpu(env); > + > + /* tlbiva instruciton only exists on BookE */ Typo here ^^ > + assert(env->mmu_model == POWERPC_MMU_BOOKE); > + /* XXX: TODO */ > + cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); > +} > + > /* Software driven TLBs management */ > /* PowerPC 602/603 software TLB load instructions helpers */ > static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code) > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 4be7eaa..a05a169 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -5904,7 +5904,7 @@ static void gen_tlbiva(DisasContext *ctx) > } > t0 = tcg_temp_new(); > gen_addr_reg_index(ctx, t0); > - gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); > + gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); > tcg_temp_free(t0); > #endif > } > Reviewed-by: Laurent Vivier