From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753791AbcBENId (ORCPT ); Fri, 5 Feb 2016 08:08:33 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:32943 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753752AbcBENI2 (ORCPT ); Fri, 5 Feb 2016 08:08:28 -0500 Subject: Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support To: Thomas Petazzoni , Fu Wei Cc: Guenter Roeck , Rob Herring , =?UTF-8?Q?Pawe=c5=82_Moll?= , Mark Rutland , Ian Campbell , Kumar Gala , Wim Van Sebroeck , Jon Corbet , Catalin Marinas , Will Deacon , Suravee Suthikulpanit , LKML , linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linaro ACPI Mailman List , rruigrok@codeaurora.org, "Abdulhamid, Harb" , Christopher Covington , Dave Young , Pratyush Anand , G Gregory , Al Stone , Hanjun Guo , Jon Masters , Arnd Bergmann , Leo Duran , Sudeep Holla References: <1454519923-25230-1-git-send-email-fu.wei@linaro.org> <1454519923-25230-6-git-send-email-fu.wei@linaro.org> <56B23883.7000501@codeaurora.org> <56B23E99.1030604@codeaurora.org> <56B2423B.1020109@codeaurora.org> <56B24642.8090105@codeaurora.org> <56B24AB5.3070001@codeaurora.org> <56B2DEE4.7060901@roeck-us.net> <20160205140259.72a33699@free-electrons.com> From: Timur Tabi Message-ID: <56B49EC7.4050306@codeaurora.org> Date: Fri, 5 Feb 2016 07:08:23 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:42.0) Gecko/20100101 Firefox/42.0 SeaMonkey/2.39 MIME-Version: 1.0 In-Reply-To: <20160205140259.72a33699@free-electrons.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thomas Petazzoni wrote: >> if panic is enabled : >> >|--------WOR-------WS0--------WOR-------WS1 >> >|------timeout------(panic)------timeout-----reset > I'm quite certainly missing something completely obvious here, but how > can you get the WS1 interrupt*after* raising a panic? Aren't all > interrupts disabled and the system fully halted once you get a panic(), > especially when raised from an interrupt handler? If that's the case, > how can the system continue to do things, such as receiving the WS1 > interrupt and resetting ? Typically, WS1 is not an interrupt. Instead, it's a hard system-level reset. The hardware is capable of generating an interrupt for both WS0 and WS1. However, the ACPI table only contains one interrupt value, and it's not clear whether that's supposed to be the WS0 interrupt or the WS1 interrupts. So this whole thing does assume a specfic watchdog configuration. -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Timur Tabi Subject: Re: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support Date: Fri, 5 Feb 2016 07:08:23 -0600 Message-ID: <56B49EC7.4050306@codeaurora.org> References: <1454519923-25230-1-git-send-email-fu.wei@linaro.org> <1454519923-25230-6-git-send-email-fu.wei@linaro.org> <56B23883.7000501@codeaurora.org> <56B23E99.1030604@codeaurora.org> <56B2423B.1020109@codeaurora.org> <56B24642.8090105@codeaurora.org> <56B24AB5.3070001@codeaurora.org> <56B2DEE4.7060901@roeck-us.net> <20160205140259.72a33699@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160205140259.72a33699@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org To: Thomas Petazzoni , Fu Wei Cc: Guenter Roeck , Rob Herring , =?UTF-8?Q?Pawe=c5=82_Moll?= , Mark Rutland , Ian Campbell , Kumar Gala , Wim Van Sebroeck , Jon Corbet , Catalin Marinas , Will Deacon , Suravee Suthikulpanit , LKML , linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linaro ACPI Mailman List , rruigrok@codeaurora.org, "Abdulhamid, Harb" , Christopher Covington , Dave Young , Pratyush Anand , G Gregory , Al List-Id: devicetree@vger.kernel.org Thomas Petazzoni wrote: >> if panic is enabled : >> >|--------WOR-------WS0--------WOR-------WS1 >> >|------timeout------(panic)------timeout-----reset > I'm quite certainly missing something completely obvious here, but how > can you get the WS1 interrupt*after* raising a panic? Aren't all > interrupts disabled and the system fully halted once you get a panic(), > especially when raised from an interrupt handler? If that's the case, > how can the system continue to do things, such as receiving the WS1 > interrupt and resetting ? Typically, WS1 is not an interrupt. Instead, it's a hard system-level reset. The hardware is capable of generating an interrupt for both WS0 and WS1. However, the ACPI table only contains one interrupt value, and it's not clear whether that's supposed to be the WS0 interrupt or the WS1 interrupts. So this whole thing does assume a specfic watchdog configuration. -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation. From mboxrd@z Thu Jan 1 00:00:00 1970 From: timur@codeaurora.org (Timur Tabi) Date: Fri, 5 Feb 2016 07:08:23 -0600 Subject: [PATCH v10 5/5] Watchdog: ARM SBSA Generic Watchdog half timeout panic support In-Reply-To: <20160205140259.72a33699@free-electrons.com> References: <1454519923-25230-1-git-send-email-fu.wei@linaro.org> <1454519923-25230-6-git-send-email-fu.wei@linaro.org> <56B23883.7000501@codeaurora.org> <56B23E99.1030604@codeaurora.org> <56B2423B.1020109@codeaurora.org> <56B24642.8090105@codeaurora.org> <56B24AB5.3070001@codeaurora.org> <56B2DEE4.7060901@roeck-us.net> <20160205140259.72a33699@free-electrons.com> Message-ID: <56B49EC7.4050306@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Thomas Petazzoni wrote: >> if panic is enabled : >> >|--------WOR-------WS0--------WOR-------WS1 >> >|------timeout------(panic)------timeout-----reset > I'm quite certainly missing something completely obvious here, but how > can you get the WS1 interrupt*after* raising a panic? Aren't all > interrupts disabled and the system fully halted once you get a panic(), > especially when raised from an interrupt handler? If that's the case, > how can the system continue to do things, such as receiving the WS1 > interrupt and resetting ? Typically, WS1 is not an interrupt. Instead, it's a hard system-level reset. The hardware is capable of generating an interrupt for both WS0 and WS1. However, the ACPI table only contains one interrupt value, and it's not clear whether that's supposed to be the WS0 interrupt or the WS1 interrupts. So this whole thing does assume a specfic watchdog configuration. -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation.