From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Subject: Re: [PATCH V8 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver. Date: Wed, 10 Feb 2016 17:17:33 +0100 Message-ID: <56BB629D.2040209@denx.de> References: <1452486886-8049-1-git-send-email-marex@denx.de> <201602060842.38290.marex@denx.de> <56B879BD.2070608@ti.com> <201602081627.57666.marex@denx.de> <56BB60F1.9070306@opensource.altera.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <56BB60F1.9070306-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Graham Moore , Vignesh R Cc: Brian Norris , Rob Herring , "linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Alan Tull , David Woodhouse , Dinh Nguyen , Yves Vandervennet , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On 02/10/2016 05:10 PM, Graham Moore wrote: > On 02/08/2016 09:27 AM, Marek Vasut wrote: >> On Monday, February 08, 2016 at 12:19:25 PM, Vignesh R wrote: >>> On 02/06/2016 01:12 PM, Marek Vasut wrote: >>>> On Thursday, February 04, 2016 at 06:30:27 PM, R, Vignesh wrote: >>>>> On 2/4/2016 4:55 PM, Marek Vasut wrote: >>> [...] >>> >>>>> Yeah, there is delay(of few ns) required between writing to >>>>> INDIRECTWR_START bit and actually writing data to flash(i.e writesl() >>>>> call). This is specific to TI K2G SoC and needs to be tied to the new >>>>> binding. >>>> >>>> Can't you somehow poll the hardware to check whether or not it's ready >>>> instead of adding some random delay ? >>> >>> There is no dedicated register to poll as such. >>> >>> According to TRM: >>> "Wait for couple of cycles of QSPI_REF_CLK(functional clock of QSPI >>> @384MHz) until CQSPI_REG_INDIRECTWR[0] bit is internally synchronized by >>> the QSPI module before writing to flash". >>> >>> So, a few ns(~6ns @384MHz) delay is needed (or accessing a QSPI module >>> register should be sufficient as it will take more than 2 clock cycles). >>> I believe this delay is specific to TI K2G SoC and maybe needs to be >>> tied to the binding. >> >> OK, got it. Dinh/Graham, can you check if this might be needed on >> SoCFPGA too >> please? >> > > I don't see any such requirement in the data sheet. It's working > without it. So I think it's not needed on SoCFPGA All right, so we will just add a special property or compat string for the TI SoC. But we need to get this driver mainlined first :) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-out.m-online.net ([212.18.0.9]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTXSp-00028G-9p for linux-mtd@lists.infradead.org; Wed, 10 Feb 2016 16:18:00 +0000 Message-ID: <56BB629D.2040209@denx.de> Date: Wed, 10 Feb 2016 17:17:33 +0100 From: Marek Vasut MIME-Version: 1.0 To: Graham Moore , Vignesh R CC: Brian Norris , Rob Herring , "linux-mtd@lists.infradead.org" , Alan Tull , David Woodhouse , Dinh Nguyen , Yves Vandervennet , "devicetree@vger.kernel.org" Subject: Re: [PATCH V8 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver. References: <1452486886-8049-1-git-send-email-marex@denx.de> <201602060842.38290.marex@denx.de> <56B879BD.2070608@ti.com> <201602081627.57666.marex@denx.de> <56BB60F1.9070306@opensource.altera.com> In-Reply-To: <56BB60F1.9070306@opensource.altera.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 02/10/2016 05:10 PM, Graham Moore wrote: > On 02/08/2016 09:27 AM, Marek Vasut wrote: >> On Monday, February 08, 2016 at 12:19:25 PM, Vignesh R wrote: >>> On 02/06/2016 01:12 PM, Marek Vasut wrote: >>>> On Thursday, February 04, 2016 at 06:30:27 PM, R, Vignesh wrote: >>>>> On 2/4/2016 4:55 PM, Marek Vasut wrote: >>> [...] >>> >>>>> Yeah, there is delay(of few ns) required between writing to >>>>> INDIRECTWR_START bit and actually writing data to flash(i.e writesl() >>>>> call). This is specific to TI K2G SoC and needs to be tied to the new >>>>> binding. >>>> >>>> Can't you somehow poll the hardware to check whether or not it's ready >>>> instead of adding some random delay ? >>> >>> There is no dedicated register to poll as such. >>> >>> According to TRM: >>> "Wait for couple of cycles of QSPI_REF_CLK(functional clock of QSPI >>> @384MHz) until CQSPI_REG_INDIRECTWR[0] bit is internally synchronized by >>> the QSPI module before writing to flash". >>> >>> So, a few ns(~6ns @384MHz) delay is needed (or accessing a QSPI module >>> register should be sufficient as it will take more than 2 clock cycles). >>> I believe this delay is specific to TI K2G SoC and maybe needs to be >>> tied to the binding. >> >> OK, got it. Dinh/Graham, can you check if this might be needed on >> SoCFPGA too >> please? >> > > I don't see any such requirement in the data sheet. It's working > without it. So I think it's not needed on SoCFPGA All right, so we will just add a special property or compat string for the TI SoC. But we need to get this driver mainlined first :)