From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH v2 17/30] x86/cpu: Common infrastructure for levelling context switching Date: Wed, 17 Feb 2016 01:15:40 -0700 Message-ID: <56C43A3C02000078000D2F0D@prv-mh.provo.novell.com> References: <1454679743-18133-1-git-send-email-andrew.cooper3@citrix.com> <1454679743-18133-18-git-send-email-andrew.cooper3@citrix.com> <56C33CFA02000078000D2AD2@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <56C33CFA02000078000D2AD2@prv-mh.provo.novell.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Andrew Cooper Cc: Xen-devel List-Id: xen-devel@lists.xenproject.org >>> On 16.02.16 at 15:15, wrote: >>>> On 05.02.16 at 14:42, wrote: >> --- a/xen/include/asm-x86/processor.h >> +++ b/xen/include/asm-x86/processor.h >> @@ -574,6 +574,34 @@ void microcode_set_module(unsigned int); >> int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void), unsigned long len); >> int microcode_resume_cpu(unsigned int cpu); >> >> +#define LCAP_faulting (1U << 0) >> +#define LCAP_1cd (3U << 1) >> +#define LCAP_e1cd (3U << 3) >> +#define LCAP_Da1 (1U << 5) >> +#define LCAP_6c (1U << 6) >> +#define LCAP_7ab0 (3U << 7) > > I guess the cases where the mask has two set bits is when two > CPUID output registers are being controlled, but I don't see > what use that pairing is going to be. But with the patch > supposedly going to make sense only in the context of the > following ones, I'll see (and I'd presumably be able to ack this > one then also only when having seen the others). Having seen patches up to and including 21, I still don't see the point of using 2-bit masks here. Jan