From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 5/5] x86: drop failsafe callback invocation from assembly Date: Wed, 17 Feb 2016 09:38:09 -0700 Message-ID: <56C4B00102000078000D34B1@prv-mh.provo.novell.com> References: <56C4AC2802000078000D3473@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartBA8D25E1.1__=" Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aW57H-00062e-5l for xen-devel@lists.xenproject.org; Wed, 17 Feb 2016 16:38:15 +0000 In-Reply-To: <56C4AC2802000078000D3473@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel Cc: Andrew Cooper , Keir Fraser List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartBA8D25E1.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Afaict this was never necessary on a 64-bit hypervisor, and was instead just blindly cloned over from 32-bit code: We don't fiddle with (and hence don't reload) any of DS, ES, FS, or GS, and an exception on IRET itself can equally well be reported to the guest as that very exception on the target of that IRET. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_64/compat/entry.S +++ b/xen/arch/x86/x86_64/compat/entry.S @@ -176,39 +176,7 @@ ENTRY(compat_restore_all_guest) ASSERT_INTERRUPTS_DISABLED RESTORE_ALL adj=3D8 compat=3D1 .Lft0: iretq - -.section .fixup,"ax" -.Lfx0: sti - SAVE_ALL - movq UREGS_error_code(%rsp),%rsi - movq %rsp,%rax - andq $~0xf,%rsp - pushq $__HYPERVISOR_DS # SS - pushq %rax # RSP - pushfq # RFLAGS - pushq $__HYPERVISOR_CS # CS - leaq .Ldf0(%rip),%rax - pushq %rax # RIP - pushq %rsi # error_code/entry_vector - jmp handle_exception -.Ldf0: GET_CURRENT(%rbx) - jmp compat_test_all_events -compat_failsafe_callback: - GET_CURRENT(%rbx) - leaq VCPU_trap_bounce(%rbx),%rdx - movl VCPU_failsafe_addr(%rbx),%eax - movl %eax,TRAPBOUNCE_eip(%rdx) - movl VCPU_failsafe_sel(%rbx),%eax - movw %ax,TRAPBOUNCE_cs(%rdx) - movb $TBF_FAILSAFE,TRAPBOUNCE_flags(%rdx) - btq $_VGCF_failsafe_disables_events,VCPU_guest_context_flags(%rb= x) - jnc 1f - orb $TBF_INTERRUPT,TRAPBOUNCE_flags(%rdx) -1: call compat_create_bounce_frame - jmp compat_test_all_events -.previous - _ASM_PRE_EXTABLE(.Lft0, .Lfx0) - _ASM_EXTABLE(.Ldf0, compat_failsafe_callback) + _ASM_PRE_EXTABLE(.Lft0, handle_exception) =20 /* %rdx: trap_bounce, %rbx: struct vcpu */ ENTRY(compat_post_handle_exception) @@ -322,17 +290,6 @@ compat_create_bounce_frame: movl TRAPBOUNCE_error_code(%rdx),%eax .Lft8: movl %eax,%fs:(%rsi) # ERROR CODE 1: - testb $TBF_FAILSAFE,%cl -UNLIKELY_START(nz, compat_bounce_failsafe) - subl $4*4,%esi - movl %gs,%eax -.Lft9: movl %eax,%fs:3*4(%rsi) # GS -.Lft10: movl %edi,%fs:2*4(%rsi) # FS - movl %es,%eax -.Lft11: movl %eax,%fs:1*4(%rsi) # ES - movl %ds,%eax -.Lft12: movl %eax,%fs:0*4(%rsi) # DS -UNLIKELY_END(compat_bounce_failsafe) /* Rewrite our stack frame and return to guest-OS mode. */ /* IA32 Ref. Vol. 3: TF, VM, RF and NT flags are cleared on trap. = */ andl $~(X86_EFLAGS_VM|X86_EFLAGS_RF|\ @@ -364,14 +321,8 @@ __UNLIKELY_END(compat_bounce_null_select _ASM_EXTABLE(.Lft6, compat_crash_page_fault_8) _ASM_EXTABLE(.Lft7, compat_crash_page_fault) _ASM_EXTABLE(.Lft8, compat_crash_page_fault) - _ASM_EXTABLE(.Lft9, compat_crash_page_fault_12) - _ASM_EXTABLE(.Lft10, compat_crash_page_fault_8) - _ASM_EXTABLE(.Lft11, compat_crash_page_fault_4) - _ASM_EXTABLE(.Lft12, compat_crash_page_fault) _ASM_EXTABLE(.Lft13, .Lfx13) =20 -compat_crash_page_fault_12: - addl $4,%esi compat_crash_page_fault_8: addl $4,%esi compat_crash_page_fault_4: --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -64,37 +64,7 @@ restore_all_guest: iret_exit_to_guest: addq $8,%rsp .Lft0: iretq - -.section .fixup,"ax" -.Lfx0: sti - SAVE_ALL - movq UREGS_error_code(%rsp),%rsi - movq %rsp,%rax - andq $~0xf,%rsp - pushq $__HYPERVISOR_DS # SS - pushq %rax # RSP - pushfq # RFLAGS - pushq $__HYPERVISOR_CS # CS - leaq .Ldf0(%rip),%rax - pushq %rax # RIP - pushq %rsi # error_code/entry_vector - jmp handle_exception -.Ldf0: GET_CURRENT(%rbx) - jmp test_all_events -failsafe_callback: - GET_CURRENT(%rbx) - leaq VCPU_trap_bounce(%rbx),%rdx - movq VCPU_failsafe_addr(%rbx),%rax - movq %rax,TRAPBOUNCE_eip(%rdx) - movb $TBF_FAILSAFE,TRAPBOUNCE_flags(%rdx) - bt $_VGCF_failsafe_disables_events,VCPU_guest_context_flags(%rb= x) - jnc 1f - orb $TBF_INTERRUPT,TRAPBOUNCE_flags(%rdx) -1: call create_bounce_frame - jmp test_all_events -.previous - _ASM_PRE_EXTABLE(.Lft0, .Lfx0) - _ASM_EXTABLE(.Ldf0, failsafe_callback) + _ASM_PRE_EXTABLE(.Lft0, handle_exception) =20 ALIGN /* No special register assumptions. */ @@ -405,18 +375,7 @@ __UNLIKELY_END(create_bounce_frame_bad_s subq $8,%rsi movl TRAPBOUNCE_error_code(%rdx),%eax .Lft7: movq %rax,(%rsi) # ERROR CODE -1: testb $TBF_FAILSAFE,%cl -UNLIKELY_START(nz, bounce_failsafe) - subq $32,%rsi - movl %gs,%eax -.Lft8: movq %rax,24(%rsi) # GS - movl %fs,%eax -.Lft9: movq %rax,16(%rsi) # FS - movl %es,%eax -.Lft10: movq %rax,8(%rsi) # ES - movl %ds,%eax -.Lft11: movq %rax,(%rsi) # DS -UNLIKELY_END(bounce_failsafe) +1: subq $16,%rsi movq UREGS_r11+8(%rsp),%rax .Lft12: movq %rax,8(%rsi) # R11 @@ -446,10 +405,6 @@ __UNLIKELY_END(create_bounce_frame_bad_b _ASM_EXTABLE(.Lft5, domain_crash_page_fault_16) _ASM_EXTABLE(.Lft6, domain_crash_page_fault) _ASM_EXTABLE(.Lft7, domain_crash_page_fault) - _ASM_EXTABLE(.Lft8, domain_crash_page_fault_24) - _ASM_EXTABLE(.Lft9, domain_crash_page_fault_16) - _ASM_EXTABLE(.Lft10, domain_crash_page_fault_8) - _ASM_EXTABLE(.Lft11, domain_crash_page_fault) _ASM_EXTABLE(.Lft12, domain_crash_page_fault_8) _ASM_EXTABLE(.Lft13, domain_crash_page_fault) =20 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -128,7 +128,6 @@ #define TBF_EXCEPTION 1 #define TBF_EXCEPTION_ERRCODE 2 #define TBF_INTERRUPT 8 -#define TBF_FAILSAFE 16 =20 /* 'arch_vcpu' flags values */ #define _TF_kernel_mode 0 --=__PartBA8D25E1.1__= Content-Type: text/plain; name="x86-no-failsafe-cb.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-no-failsafe-cb.patch" x86: drop failsafe callback invocation from assembly=0A=0AAfaict this was = never necessary on a 64-bit hypervisor, and was instead=0Ajust blindly = cloned over from 32-bit code: We don't fiddle with (and=0Ahence don't = reload) any of DS, ES, FS, or GS, and an exception on IRET=0Aitself can = equally well be reported to the guest as that very exception=0Aon the = target of that IRET.=0A=0ASigned-off-by: Jan Beulich =0A= =0A--- a/xen/arch/x86/x86_64/compat/entry.S=0A+++ b/xen/arch/x86/x86_64/com= pat/entry.S=0A@@ -176,39 +176,7 @@ ENTRY(compat_restore_all_guest)=0A = ASSERT_INTERRUPTS_DISABLED=0A RESTORE_ALL adj=3D8 compat=3D1=0A = .Lft0: iretq=0A-=0A-.section .fixup,"ax"=0A-.Lfx0: sti=0A- = SAVE_ALL=0A- movq UREGS_error_code(%rsp),%rsi=0A- movq = %rsp,%rax=0A- andq $~0xf,%rsp=0A- pushq $__HYPERVISOR_DS = # SS=0A- pushq %rax # RSP=0A- = pushfq # RFLAGS=0A- pushq $__HYPERVISOR_CS = # CS=0A- leaq .Ldf0(%rip),%rax=0A- pushq %rax = # RIP=0A- pushq %rsi # error_code/e= ntry_vector=0A- jmp handle_exception=0A-.Ldf0: GET_CURRENT(%rbx)= =0A- jmp compat_test_all_events=0A-compat_failsafe_callback:=0A- = GET_CURRENT(%rbx)=0A- leaq VCPU_trap_bounce(%rbx),%rdx=0A- = movl VCPU_failsafe_addr(%rbx),%eax=0A- movl %eax,TRAPBOUNCE_e= ip(%rdx)=0A- movl VCPU_failsafe_sel(%rbx),%eax=0A- movw = %ax,TRAPBOUNCE_cs(%rdx)=0A- movb $TBF_FAILSAFE,TRAPBOUNCE_flags(%rd= x)=0A- btq $_VGCF_failsafe_disables_events,VCPU_guest_context_flag= s(%rbx)=0A- jnc 1f=0A- orb $TBF_INTERRUPT,TRAPBOUNCE_flag= s(%rdx)=0A-1: call compat_create_bounce_frame=0A- jmp = compat_test_all_events=0A-.previous=0A- _ASM_PRE_EXTABLE(.Lft0, = .Lfx0)=0A- _ASM_EXTABLE(.Ldf0, compat_failsafe_callback)=0A+ = _ASM_PRE_EXTABLE(.Lft0, handle_exception)=0A =0A /* %rdx: trap_bounce, = %rbx: struct vcpu */=0A ENTRY(compat_post_handle_exception)=0A@@ -322,17 = +290,6 @@ compat_create_bounce_frame:=0A movl TRAPBOUNCE_error_cod= e(%rdx),%eax=0A .Lft8: movl %eax,%fs:(%rsi) # ERROR CODE=0A = 1:=0A- testb $TBF_FAILSAFE,%cl=0A-UNLIKELY_START(nz, compat_bounce_f= ailsafe)=0A- subl $4*4,%esi=0A- movl %gs,%eax=0A-.Lft9: = movl %eax,%fs:3*4(%rsi) # GS=0A-.Lft10: movl %edi,%fs:2*4(%rsi) = # FS=0A- movl %es,%eax=0A-.Lft11: movl %eax,%fs:1*4(%rsi) = # ES=0A- movl %ds,%eax=0A-.Lft12: movl %eax,%fs:0*4(%rsi) = # DS=0A-UNLIKELY_END(compat_bounce_failsafe)=0A /* Rewrite our = stack frame and return to guest-OS mode. */=0A /* IA32 Ref. Vol. = 3: TF, VM, RF and NT flags are cleared on trap. */=0A andl = $~(X86_EFLAGS_VM|X86_EFLAGS_RF|\=0A@@ -364,14 +321,8 @@ __UNLIKELY_END(comp= at_bounce_null_select=0A _ASM_EXTABLE(.Lft6, compat_crash_page_fau= lt_8)=0A _ASM_EXTABLE(.Lft7, compat_crash_page_fault)=0A = _ASM_EXTABLE(.Lft8, compat_crash_page_fault)=0A- _ASM_EXTABLE(.Lft9= , compat_crash_page_fault_12)=0A- _ASM_EXTABLE(.Lft10, compat_crash= _page_fault_8)=0A- _ASM_EXTABLE(.Lft11, compat_crash_page_fault_4)= =0A- _ASM_EXTABLE(.Lft12, compat_crash_page_fault)=0A = _ASM_EXTABLE(.Lft13, .Lfx13)=0A =0A-compat_crash_page_fault_12:=0A- = addl $4,%esi=0A compat_crash_page_fault_8:=0A addl $4,%esi=0A = compat_crash_page_fault_4:=0A--- a/xen/arch/x86/x86_64/entry.S=0A+++ = b/xen/arch/x86/x86_64/entry.S=0A@@ -64,37 +64,7 @@ restore_all_guest:=0A = iret_exit_to_guest:=0A addq $8,%rsp=0A .Lft0: iretq=0A-=0A-.secti= on .fixup,"ax"=0A-.Lfx0: sti=0A- SAVE_ALL=0A- movq = UREGS_error_code(%rsp),%rsi=0A- movq %rsp,%rax=0A- andq = $~0xf,%rsp=0A- pushq $__HYPERVISOR_DS # SS=0A- pushq = %rax # RSP=0A- pushfq # = RFLAGS=0A- pushq $__HYPERVISOR_CS # CS=0A- leaq = .Ldf0(%rip),%rax=0A- pushq %rax # RIP=0A- = pushq %rsi # error_code/entry_vector=0A- jmp = handle_exception=0A-.Ldf0: GET_CURRENT(%rbx)=0A- jmp test_all_eve= nts=0A-failsafe_callback:=0A- GET_CURRENT(%rbx)=0A- leaq = VCPU_trap_bounce(%rbx),%rdx=0A- movq VCPU_failsafe_addr(%rbx),%rax= =0A- movq %rax,TRAPBOUNCE_eip(%rdx)=0A- movb $TBF_FAILSAFE,= TRAPBOUNCE_flags(%rdx)=0A- bt $_VGCF_failsafe_disables_events,VCP= U_guest_context_flags(%rbx)=0A- jnc 1f=0A- orb $TBF_INTER= RUPT,TRAPBOUNCE_flags(%rdx)=0A-1: call create_bounce_frame=0A- = jmp test_all_events=0A-.previous=0A- _ASM_PRE_EXTABLE(.Lft0, = .Lfx0)=0A- _ASM_EXTABLE(.Ldf0, failsafe_callback)=0A+ = _ASM_PRE_EXTABLE(.Lft0, handle_exception)=0A =0A ALIGN=0A /* No = special register assumptions. */=0A@@ -405,18 +375,7 @@ __UNLIKELY_END(crea= te_bounce_frame_bad_s=0A subq $8,%rsi=0A movl TRAPBOUNCE_= error_code(%rdx),%eax=0A .Lft7: movq %rax,(%rsi) # ERROR = CODE=0A-1: testb $TBF_FAILSAFE,%cl=0A-UNLIKELY_START(nz, bounce_failsa= fe)=0A- subq $32,%rsi=0A- movl %gs,%eax=0A-.Lft8: movq = %rax,24(%rsi) # GS=0A- movl %fs,%eax=0A-.Lft9: movq = %rax,16(%rsi) # FS=0A- movl %es,%eax=0A-.Lft10: movq = %rax,8(%rsi) # ES=0A- movl %ds,%eax=0A-.Lft11: movq = %rax,(%rsi) # DS=0A-UNLIKELY_END(bounce_failsafe)=0A+1:=0A = subq $16,%rsi=0A movq UREGS_r11+8(%rsp),%rax=0A .Lft12: = movq %rax,8(%rsi) # R11=0A@@ -446,10 +405,6 @@ __UNLIKELY_END= (create_bounce_frame_bad_b=0A _ASM_EXTABLE(.Lft5, domain_crash_pag= e_fault_16)=0A _ASM_EXTABLE(.Lft6, domain_crash_page_fault)=0A = _ASM_EXTABLE(.Lft7, domain_crash_page_fault)=0A- _ASM_EXTABLE(= .Lft8, domain_crash_page_fault_24)=0A- _ASM_EXTABLE(.Lft9, = domain_crash_page_fault_16)=0A- _ASM_EXTABLE(.Lft10, domain_crash_pa= ge_fault_8)=0A- _ASM_EXTABLE(.Lft11, domain_crash_page_fault)=0A = _ASM_EXTABLE(.Lft12, domain_crash_page_fault_8)=0A _ASM_EXTABL= E(.Lft13, domain_crash_page_fault)=0A =0A--- a/xen/include/asm-x86/processo= r.h=0A+++ b/xen/include/asm-x86/processor.h=0A@@ -128,7 +128,6 @@=0A = #define TBF_EXCEPTION 1=0A #define TBF_EXCEPTION_ERRCODE 2=0A = #define TBF_INTERRUPT 8=0A-#define TBF_FAILSAFE 16=0A = =0A /* 'arch_vcpu' flags values */=0A #define _TF_kernel_mode 0=0A --=__PartBA8D25E1.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__PartBA8D25E1.1__=--