From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932813AbcBWId3 (ORCPT ); Tue, 23 Feb 2016 03:33:29 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:29091 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932672AbcBWId0 (ORCPT ); Tue, 23 Feb 2016 03:33:26 -0500 X-AuditID: cbfec7f5-f79b16d000005389-ba-56cc19532bf1 Subject: Re: [PATCH] ARM: dts: add support for gpio buttons for exynos5422-odroidxu3 To: Anand Moon , Kukjin Kim , Javier Martinez Canillas , Marek Szyprowski References: <1456214467-3344-1-git-send-email-linux.amoon@gmail.com> <56CC167A.8040303@samsung.com> Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org From: Krzysztof Kozlowski Message-id: <56CC194F.6080905@samsung.com> Date: Tue, 23 Feb 2016 17:33:19 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-version: 1.0 In-reply-to: <56CC167A.8040303@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJLMWRmVeSWpSXmKPExsVy+t/xa7rBkmfCDJbdtbGYf+Qcq8Wbt2uY LF6/MLTof/ya2WLT42usFpd3zWGzmHF+H5PFuo232C3WHrnL7sDpsXPWXXaPTas62Tw2L6n3 2NIP5PVtWcXo8XmTXABbFJdNSmpOZllqkb5dAlfGz4vbmAu2C1Rc+trA1sB4lreLkZNDQsBE 4lPPfXYIW0ziwr31bF2MXBxCAksZJVZ/usgE4TxllLjbsJYNpEpYIEzi8K8dYAkRgZWMEpuO HmYBSQgJpErcWXQTrJ1ZoJ1R4s7b2WAdbALGEpuXLwGzeQW0JKbOOs8IYrMIqEqs/HSIFcQW FYiQONzZxQ5RIyjxY/I9sKGcAtoSD74vYO5i5AAaqidx/6IWSJhZQF5i85q3zBMYBWYh6ZiF UDULSdUCRuZVjKKppckFxUnpuUZ6xYm5xaV56XrJ+bmbGCER8HUH49JjVocYBTgYlXh4PbxO hwmxJpYVV+YeYpTgYFYS4XXgOxMmxJuSWFmVWpQfX1Sak1p8iFGag0VJnHfmrvchQgLpiSWp 2ampBalFMFkmDk6pBkbtrnKnVxeFt/72X5HVZV2/922Rt5jYoS3X7l+u+NzyOXedu1r1boaT meIBcR90mha2XPfbF3/83uGSOBm1Qq6//aoyvj7/xZ8zmHs8CHYTYow8x1O1+fxrs92HgmwK OEwi1G1yePa8TlThnLcicduRBQw+7iJLorpfpbinrdydHuXVseHcPyWW4oxEQy3mouJEAPbX g2R8AgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.02.2016 17:21, Krzysztof Kozlowski wrote: > On 23.02.2016 17:01, Anand Moon wrote: >> Add support for gpio-based button on Odroid-XU3 boards >> for reboot/poweroff feature. >> >> Signed-off-by: Anand Moon >> --- >> changes rebase based on linux next-20160222. >> >> Tested on Odroid-XU4 >> >> dmesg output. >> [ 3.286068] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/power_key[0]' - status (0) >> [ 3.286206] gpio-11 (power key): gpiod_set_debounce: missing set() or set_debounce() operations >> [ 3.286600] input: gpio_keys as /devices/platform/gpio_keys/input/input0 >> --- >> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> index 1bd507b..db9770b 100644 >> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> @@ -11,6 +11,7 @@ >> */ >> >> #include >> +#include >> #include >> #include >> #include >> @@ -54,6 +55,22 @@ >> #cooling-cells = <2>; >> cooling-levels = <0 130 170 230>; >> }; >> + >> + gpio_keys { >> + compatible = "gpio-keys"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&gpio_power_key>; >> + >> + power_key { >> + interrupt-parent = <&gpx0>; >> + interrupts = <3 IRQ_TYPE_NONE>; > > Hmmm.... why you specify the interrupts? > >> + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; Please, explain it to me. The SW2 key is connected to PWRON of PMIC. However you are adding a GPIO key for external interrupt source 3 (XE.INT3)... which comes from PMIC's ONOB. It's interesting.... how does it work? The PMIC will generate ONOB interrupt on PWRON low->high change (when PWRHOLD is high)? Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 From: k.kozlowski@samsung.com (Krzysztof Kozlowski) Date: Tue, 23 Feb 2016 17:33:19 +0900 Subject: [PATCH] ARM: dts: add support for gpio buttons for exynos5422-odroidxu3 In-Reply-To: <56CC167A.8040303@samsung.com> References: <1456214467-3344-1-git-send-email-linux.amoon@gmail.com> <56CC167A.8040303@samsung.com> Message-ID: <56CC194F.6080905@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 23.02.2016 17:21, Krzysztof Kozlowski wrote: > On 23.02.2016 17:01, Anand Moon wrote: >> Add support for gpio-based button on Odroid-XU3 boards >> for reboot/poweroff feature. >> >> Signed-off-by: Anand Moon >> --- >> changes rebase based on linux next-20160222. >> >> Tested on Odroid-XU4 >> >> dmesg output. >> [ 3.286068] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/power_key[0]' - status (0) >> [ 3.286206] gpio-11 (power key): gpiod_set_debounce: missing set() or set_debounce() operations >> [ 3.286600] input: gpio_keys as /devices/platform/gpio_keys/input/input0 >> --- >> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> index 1bd507b..db9770b 100644 >> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> @@ -11,6 +11,7 @@ >> */ >> >> #include >> +#include >> #include >> #include >> #include >> @@ -54,6 +55,22 @@ >> #cooling-cells = <2>; >> cooling-levels = <0 130 170 230>; >> }; >> + >> + gpio_keys { >> + compatible = "gpio-keys"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&gpio_power_key>; >> + >> + power_key { >> + interrupt-parent = <&gpx0>; >> + interrupts = <3 IRQ_TYPE_NONE>; > > Hmmm.... why you specify the interrupts? > >> + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; Please, explain it to me. The SW2 key is connected to PWRON of PMIC. However you are adding a GPIO key for external interrupt source 3 (XE.INT3)... which comes from PMIC's ONOB. It's interesting.... how does it work? The PMIC will generate ONOB interrupt on PWRON low->high change (when PWRHOLD is high)? Best regards, Krzysztof