From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afYB5-0005ed-27 for qemu-devel@nongnu.org; Mon, 14 Mar 2016 15:29:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afYB1-0006nl-N1 for qemu-devel@nongnu.org; Mon, 14 Mar 2016 15:29:18 -0400 References: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> <1457974600-13828-6-git-send-email-clg@fr.ibm.com> From: Thomas Huth Message-ID: <56E71106.2050108@redhat.com> Date: Mon, 14 Mar 2016 20:29:10 +0100 MIME-Version: 1.0 In-Reply-To: <1457974600-13828-6-git-send-email-clg@fr.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 14.03.2016 17:56, C=C3=A9dric Le Goater wrote: > From: Benjamin Herrenschmidt >=20 > This helper is only used by the various instructions that can alter > MSR and not interrupts. Add a comment to that effect to the interrupt > code as well in case somebody wants to change this >=20 > Signed-off-by: Benjamin Herrenschmidt > Reviewed-by: David Gibson > --- > target-ppc/excp_helper.c | 8 ++++++-- > target-ppc/helper_regs.h | 4 ++-- > 2 files changed, 8 insertions(+), 4 deletions(-) >=20 > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > index c890853d861b..37d4721db63b 100644 > --- a/target-ppc/excp_helper.c > +++ b/target-ppc/excp_helper.c > @@ -666,8 +666,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, i= nt excp_model, int excp) > } > } > #endif > - /* XXX: we don't use hreg_store_msr here as already have treated > - * any special case that could occur. Just store MSR and upda= te hflags > + /* We don't use hreg_store_msr here as already have treated > + * any special case that could occur. Just store MSR and update hf= lags > + * > + * Note: We *MUST* not use hreg_store_msr() as-is anyway because i= t > + * will prevent setting of the HV bit which some exceptions might = need > + * to do. > */ > env->msr =3D new_msr & env->msr_mask; > hreg_compute_hflags(env); > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index 271fddf17f0a..844240d1a755 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -75,8 +75,8 @@ static inline int hreg_store_msr(CPUPPCState *env, ta= rget_ulong value, > excp =3D 0; > value &=3D env->msr_mask; > #if !defined(CONFIG_USER_ONLY) > - if (!alter_hv) { > - /* mtmsr cannot alter the hypervisor state */ > + /* Neither mtmsr nor guest state can alter HV */ > + if (!alter_hv || !(env->msr & MSR_HVB)) { > value &=3D ~MSR_HVB; > value |=3D env->msr & MSR_HVB; > } Reviewed-by: Thomas Huth