From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48071) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afZ4x-0007Di-Ua for qemu-devel@nongnu.org; Mon, 14 Mar 2016 16:27:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afZ4w-0004oI-MY for qemu-devel@nongnu.org; Mon, 14 Mar 2016 16:27:03 -0400 References: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> <1457974600-13828-13-git-send-email-clg@fr.ibm.com> From: Thomas Huth Message-ID: <56E71E8E.4090800@redhat.com> Date: Mon, 14 Mar 2016 21:26:54 +0100 MIME-Version: 1.0 In-Reply-To: <1457974600-13828-13-git-send-email-clg@fr.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 14.03.2016 17:56, C=C3=A9dric Le Goater wrote: > From: Benjamin Herrenschmidt >=20 > The masks weren't chosen nor applied properly. The architecture specifi= es > that writes to AMR are masked by UAMOR for PR=3D1, otherwise AMOR for H= V=3D0. >=20 > The writes to UAMOR are masked by AMOR for HV=3D0 >=20 > Signed-off-by: Benjamin Herrenschmidt > [clg: fixed gen_spr_amr() call in init_proc_book3s_64()] > Signed-off-by: C=C3=A9dric Le Goater > --- > target-ppc/translate_init.c | 78 +++++++++++++++++++++++++++++++++++--= -------- > 1 file changed, 61 insertions(+), 17 deletions(-) >=20 > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index c921d9f53984..f2eb5f041ecd 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -1070,30 +1070,72 @@ static void gen_spr_7xx (CPUPPCState *env) > =20 > #ifdef TARGET_PPC64 > #ifndef CONFIG_USER_ONLY > -static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn) > +static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) > { > - gen_load_spr(cpu_gpr[gprn], SPR_AMR); > - spr_load_dump_spr(SPR_AMR); > -} > + TCGv t0 =3D tcg_temp_new(); > + TCGv t1 =3D tcg_temp_new(); > + TCGv t2 =3D tcg_temp_new(); > =20 > -static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn) > -{ > - gen_store_spr(SPR_AMR, cpu_gpr[gprn]); > + /* Note, the HV=3D1 PR=3D0 case is handled earlier by simply using > + * spr_write_generic for HV mode in the SPR table > + */ > + > + /* Build insertion mask into t1 based on context */ > + if (ctx->pr) { > + gen_load_spr(t1, SPR_UAMOR); > + } else { > + gen_load_spr(t1, SPR_AMOR); > + } > + > + /* Mask new bits into t2 */ > + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); > + > + /* Load AMR and clear new bits in t0 */ > + gen_load_spr(t0, SPR_AMR); > + tcg_gen_andc_tl(t0, t0, t1); > + > + /* Or'in new bits and write it out */ > + tcg_gen_or_tl(t0, t0, t2); > + gen_store_spr(SPR_AMR, t0); > spr_store_dump_spr(SPR_AMR); > + > + tcg_temp_free(t0); > + tcg_temp_free(t1); > + tcg_temp_free(t2); > } > =20 > -static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn) > +static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) > { > TCGv t0 =3D tcg_temp_new(); > + TCGv t1 =3D tcg_temp_new(); > + TCGv t2 =3D tcg_temp_new(); > + > + /* Note, the HV=3D1 case is handled earlier by simply using > + * spr_write_generic for HV mode in the SPR table > + */ > =20 > + /* Build insertion mask into t1 based on context */ > + gen_load_spr(t1, SPR_AMOR); > + > + /* Mask new bits into t2 */ > + tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); > + > + /* Load AMR and clear new bits in t0 */ > gen_load_spr(t0, SPR_UAMOR); > - tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); > - gen_store_spr(SPR_AMR, t0); > - spr_store_dump_spr(SPR_AMR); > + tcg_gen_andc_tl(t0, t0, t1); > + > + /* Or'in new bits and write it out */ > + tcg_gen_or_tl(t0, t0, t2); > + gen_store_spr(SPR_UAMOR, t0); > + spr_store_dump_spr(SPR_UAMOR); > + > + tcg_temp_free(t0); > + tcg_temp_free(t1); > + tcg_temp_free(t2); > } > #endif /* CONFIG_USER_ONLY */ > =20 > -static void gen_spr_amr (CPUPPCState *env) > +static void gen_spr_amr(CPUPPCState *env, bool has_iamr) > { > #ifndef CONFIG_USER_ONLY > /* Virtual Page Class Key protection */ > @@ -1101,15 +1143,17 @@ static void gen_spr_amr (CPUPPCState *env) > * userspace accessible, 29 is privileged. So we only need to set > * the kvm ONE_REG id on one of them, we use 29 */ > spr_register(env, SPR_UAMR, "UAMR", > - &spr_read_uamr, &spr_write_uamr_pr, > - &spr_read_uamr, &spr_write_uamr, > + &spr_read_generic, &spr_write_amr, > + &spr_read_generic, &spr_write_amr, > 0); > - spr_register_kvm(env, SPR_AMR, "AMR", > + spr_register_kvm_hv(env, SPR_AMR, "AMR", > SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_amr, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_AMR, 0); > - spr_register_kvm(env, SPR_UAMOR, "UAMOR", > + spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", > SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_uamor, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_UAMOR, 0); > spr_register_hv(env, SPR_AMOR, "AMOR", > @@ -8093,7 +8137,7 @@ static void init_proc_book3s_64(CPUPPCState *env,= int version) > case BOOK3S_CPU_POWER7: > case BOOK3S_CPU_POWER8: > gen_spr_book3s_ids(env); > - gen_spr_amr(env); > + gen_spr_amr(env, version >=3D BOOK3S_CPU_POWER8); > gen_spr_book3s_purr(env); > env->ci_large_pages =3D true; > break; I think this last hunk (and thus the "has_iamr" parameter of that function) rather belong to the next patch, since it is not used here yet. Apart from that, the patch looks fine to me. Thomas