From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afk0X-0006nh-QA for qemu-devel@nongnu.org; Tue, 15 Mar 2016 04:07:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afk0U-0000mi-Fk for qemu-devel@nongnu.org; Tue, 15 Mar 2016 04:07:13 -0400 Received: from e06smtp12.uk.ibm.com ([195.75.94.108]:59199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afk0U-0000mA-6V for qemu-devel@nongnu.org; Tue, 15 Mar 2016 04:07:10 -0400 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 15 Mar 2016 08:07:09 -0000 References: <1457974600-13828-1-git-send-email-clg@fr.ibm.com> <1457974600-13828-5-git-send-email-clg@fr.ibm.com> <56E70F14.2020406@redhat.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <56E7C2A1.1000901@fr.ibm.com> Date: Tue, 15 Mar 2016 09:06:57 +0100 MIME-Version: 1.0 In-Reply-To: <56E70F14.2020406@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas Huth , David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Bharata B Rao On 03/14/2016 08:20 PM, Thomas Huth wrote: > On 14.03.2016 17:56, Cédric Le Goater wrote: >> From: Benjamin Herrenschmidt >> >> Also use it to clamp the max SMT mode and ensure that the cpu_dt_id >> are offset by that value in order to preserve consistency with the >> HW implementations. >> >> Signed-off-by: Benjamin Herrenschmidt >> --- >> target-ppc/cpu-qom.h | 1 + >> target-ppc/translate_init.c | 11 ++++++++++- >> 2 files changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h >> index 7d5e2b36a997..735981309c5b 100644 >> --- a/target-ppc/cpu-qom.h >> +++ b/target-ppc/cpu-qom.h >> @@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass { >> uint32_t flags; >> int bfd_mach; >> uint32_t l1_dcache_size, l1_icache_size; >> + uint32_t threads_per_core; >> #if defined(TARGET_PPC64) >> const struct ppc_segment_page_sizes *sps; >> #endif >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >> index 43c6e524a6bc..46dabe58783a 100644 >> --- a/target-ppc/translate_init.c >> +++ b/target-ppc/translate_init.c >> @@ -8231,6 +8231,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) >> POWERPC_FLAG_BUS_CLK; >> pcc->l1_dcache_size = 0x8000; >> pcc->l1_icache_size = 0x10000; >> + pcc->threads_per_core = 2; >> } >> >> static void powerpc_get_compat(Object *obj, Visitor *v, const char *name, >> @@ -8408,6 +8409,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) >> pcc->l1_dcache_size = 0x8000; >> pcc->l1_icache_size = 0x8000; >> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; >> + pcc->threads_per_core = 4; >> } >> >> static void init_proc_POWER8(CPUPPCState *env) >> @@ -8492,6 +8494,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) >> pcc->l1_dcache_size = 0x8000; >> pcc->l1_icache_size = 0x8000; >> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; >> + pcc->threads_per_core = 8; >> } >> #endif /* defined (TARGET_PPC64) */ >> >> @@ -9195,6 +9198,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) >> #endif >> >> #if !defined(CONFIG_USER_ONLY) >> + if (pcc->threads_per_core == 0) { >> + pcc->threads_per_core = 1; >> + } >> + if (max_smt > pcc->threads_per_core) { >> + max_smt = pcc->threads_per_core; >> + } >> if (smp_threads > max_smt) { >> error_setg(errp, "Cannot support more than %d threads on PPC with %s", >> max_smt, kvm_enabled() ? "KVM" : "TCG"); >> @@ -9215,7 +9224,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) >> } >> >> #if !defined(CONFIG_USER_ONLY) >> - cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt >> + cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core >> + (cs->cpu_index % smp_threads); >> #endif > > That looks like it could collide with Bharata's CPU hotplug series ... > Bharata, > what do you think? > > Anyway, I don't see where this is really required for the SPR > definitions ... Cédric, could you also do it without this patch > for now? Yes. Will remove. Thanks C.