From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932359AbcCWR4p (ORCPT ); Wed, 23 Mar 2016 13:56:45 -0400 Received: from vern.gendns.com ([50.115.127.205]:49058 "EHLO vern.gendns.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1756315AbcCWR4n (ORCPT ); Wed, 23 Mar 2016 13:56:43 -0400 Subject: Re: [PATCH v2 05/11] dt-bindings: Add bindings for phy-da8xx-usb To: Sekhar Nori References: <1458181615-27782-1-git-send-email-david@lechnology.com> <1458181615-27782-6-git-send-email-david@lechnology.com> <56F2CD16.9060106@ti.com> Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Kevin Hilman , Kishon Vijay Abraham I , Alan Stern , Greg Kroah-Hartman , Bin Liu , Tony Lindgren , Robert Jarzmik , =?UTF-8?Q?Andreas_F=c3=a4rber?= , Sergei Shtylyov , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org From: David Lechner Message-ID: <56F2D8D7.5070206@lechnology.com> Date: Wed, 23 Mar 2016 12:56:39 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <56F2CD16.9060106@ti.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/23/2016 12:06 PM, Sekhar Nori wrote: > On Thursday 17 March 2016 07:56 AM, David Lechner wrote: >> Device tree binding for new phy-da8xx-usb driver. >> >> Signed-off-by: David Lechner >> --- >> >> v2 changes: This is new patch in v2. >> >> >> .../devicetree/bindings/phy/phy-da8xx-usb.txt | 34 ++++++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> new file mode 100644 >> index 0000000..ed6b710 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> @@ -0,0 +1,34 @@ >> +TI DaVinci DA8XX USB PHY >> + >> +Required properties: >> + - compatible: must be "ti,da830-usbphy". >> + - #phy-cells: must be 1. >> + - reg : Address and length of the CFGCHIP2 register. > > I am not sure passing CFGCHIP2 register as reg property to the phy is > future proof. At some point, we do want to move to common clock > framework and at that point USB clocks controlled by CFGCHIP2 will be a > separate driver needing access to the same register. > > So I think the CFGCHIP2 access in USB phy driver should happen through a > syscon phandle. This needs to happen now, not later since we cannot > break DT backward-compatibility. > I think using "syscon" for the CFGCHIP registers makes sense (based on my minimal experience). Would we want one "syscon" device node that includes all of the CFGCHIP registers or one each? Something like this? cfgchip@1417C { compatible = "ti,da830-cfgchip", "syscon"; reg = <1417C 20>; } or this? cfgchip0@1417C { compatible = "ti,da830-cfgchip0", "syscon"; reg = <1417C 4>; } cfgchip1@14180 { compatible = "ti,da830-cfgchip1", "syscon"; reg = <14180 4>; } etc. -or- Would it be OK if the PHY driver registered clocks? I'm guessing this falls into the category of "not such a good idea". From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Lechner Subject: Re: [PATCH v2 05/11] dt-bindings: Add bindings for phy-da8xx-usb Date: Wed, 23 Mar 2016 12:56:39 -0500 Message-ID: <56F2D8D7.5070206@lechnology.com> References: <1458181615-27782-1-git-send-email-david@lechnology.com> <1458181615-27782-6-git-send-email-david@lechnology.com> <56F2CD16.9060106@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <56F2CD16.9060106-l0cyMroinI0@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Sekhar Nori Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Kevin Hilman , Kishon Vijay Abraham I , Alan Stern , Greg Kroah-Hartman , Bin Liu , Tony Lindgren , Robert Jarzmik , =?UTF-8?Q?Andreas_F=c3=a4rber?= , Sergei Shtylyov , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 03/23/2016 12:06 PM, Sekhar Nori wrote: > On Thursday 17 March 2016 07:56 AM, David Lechner wrote: >> Device tree binding for new phy-da8xx-usb driver. >> >> Signed-off-by: David Lechner >> --- >> >> v2 changes: This is new patch in v2. >> >> >> .../devicetree/bindings/phy/phy-da8xx-usb.txt | 34 ++++++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> new file mode 100644 >> index 0000000..ed6b710 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> @@ -0,0 +1,34 @@ >> +TI DaVinci DA8XX USB PHY >> + >> +Required properties: >> + - compatible: must be "ti,da830-usbphy". >> + - #phy-cells: must be 1. >> + - reg : Address and length of the CFGCHIP2 register. > > I am not sure passing CFGCHIP2 register as reg property to the phy is > future proof. At some point, we do want to move to common clock > framework and at that point USB clocks controlled by CFGCHIP2 will be a > separate driver needing access to the same register. > > So I think the CFGCHIP2 access in USB phy driver should happen through a > syscon phandle. This needs to happen now, not later since we cannot > break DT backward-compatibility. > I think using "syscon" for the CFGCHIP registers makes sense (based on my minimal experience). Would we want one "syscon" device node that includes all of the CFGCHIP registers or one each? Something like this? cfgchip@1417C { compatible = "ti,da830-cfgchip", "syscon"; reg = <1417C 20>; } or this? cfgchip0@1417C { compatible = "ti,da830-cfgchip0", "syscon"; reg = <1417C 4>; } cfgchip1@14180 { compatible = "ti,da830-cfgchip1", "syscon"; reg = <14180 4>; } etc. -or- Would it be OK if the PHY driver registered clocks? I'm guessing this falls into the category of "not such a good idea". -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: david@lechnology.com (David Lechner) Date: Wed, 23 Mar 2016 12:56:39 -0500 Subject: [PATCH v2 05/11] dt-bindings: Add bindings for phy-da8xx-usb In-Reply-To: <56F2CD16.9060106@ti.com> References: <1458181615-27782-1-git-send-email-david@lechnology.com> <1458181615-27782-6-git-send-email-david@lechnology.com> <56F2CD16.9060106@ti.com> Message-ID: <56F2D8D7.5070206@lechnology.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 03/23/2016 12:06 PM, Sekhar Nori wrote: > On Thursday 17 March 2016 07:56 AM, David Lechner wrote: >> Device tree binding for new phy-da8xx-usb driver. >> >> Signed-off-by: David Lechner >> --- >> >> v2 changes: This is new patch in v2. >> >> >> .../devicetree/bindings/phy/phy-da8xx-usb.txt | 34 ++++++++++++++++++++++ >> 1 file changed, 34 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> new file mode 100644 >> index 0000000..ed6b710 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-da8xx-usb.txt >> @@ -0,0 +1,34 @@ >> +TI DaVinci DA8XX USB PHY >> + >> +Required properties: >> + - compatible: must be "ti,da830-usbphy". >> + - #phy-cells: must be 1. >> + - reg : Address and length of the CFGCHIP2 register. > > I am not sure passing CFGCHIP2 register as reg property to the phy is > future proof. At some point, we do want to move to common clock > framework and at that point USB clocks controlled by CFGCHIP2 will be a > separate driver needing access to the same register. > > So I think the CFGCHIP2 access in USB phy driver should happen through a > syscon phandle. This needs to happen now, not later since we cannot > break DT backward-compatibility. > I think using "syscon" for the CFGCHIP registers makes sense (based on my minimal experience). Would we want one "syscon" device node that includes all of the CFGCHIP registers or one each? Something like this? cfgchip at 1417C { compatible = "ti,da830-cfgchip", "syscon"; reg = <1417C 20>; } or this? cfgchip0 at 1417C { compatible = "ti,da830-cfgchip0", "syscon"; reg = <1417C 4>; } cfgchip1 at 14180 { compatible = "ti,da830-cfgchip1", "syscon"; reg = <14180 4>; } etc. -or- Would it be OK if the PHY driver registered clocks? I'm guessing this falls into the category of "not such a good idea".