From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 29 Mar 2016 19:45:55 +0200 Subject: [U-Boot] Newbie SPL question for socfpga_sockit In-Reply-To: References: <56C53059.4020505@electromag.com.au> <56D662D4.40302@electromag.com.au> <56D7E389.5080308@electromag.com.au> <56DF7F80.4060602@electromag.com.au> <56E0010A.6010202@denx.de> <56EA09DA.5040504@denx.de> <56EEC7DE.7050605@opensource.altera.com> Message-ID: <56FABF53.1000705@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/29/2016 03:44 AM, George Broz wrote: > On 20 March 2016 at 08:55, Dinh Nguyen wrote: >> >> >> On 03/16/2016 08:35 PM, Marek Vasut wrote: >>>> >>>> Does this work for anybody else? >>>> Is it in anyone's experience that these (cheaper) Terasic >>>> eval boards are generally out of spec? >>>> >>>> Is there a way to relax the calibration parameters? the USB parameters? >>>> >>>> Would it help if I posted debug output? >>> >>> Sorry for the late reply, I am horribly overloaded now. I asked someone >>> in #u-boot who has the DE0-NANO-SOC board to test latest u-boot/master >>> on it and it apparently worked for him. I should get some more feedback >>> in the morning [ see http://pastebin.com/CM1QJGnh ] . >>> >>> Still, this is getting real creepy. You are the second person who is >>> complaining about misbehavior of terasic boards with mainline u-boot >>> and whatever I do, I cannot replicate this. >>> >>> I am at least CCing the Altera guys. Sorry I have no better suggestion >>> for you :( >> >> I don't have any problems with mainline U-Boot and SPL on my DE0-NANO-BOARD: >> >> U-Boot SPL 2016.03-00307-ge4fb863 (Mar 20 2016 - 10:37:13) >> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration >> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED >> drivers/ddr/altera/sequencer.c: Calibration complete >> Trying to boot from MMC >> >> >> U-Boot 2016.03-00307-ge4fb863 (Mar 20 2016 - 10:37:13 -0500) >> >> CPU: Altera SoCFPGA Platform >> FPGA: Altera Cyclone V, SE/A4 or SX/C4, version 0x0 >> BOOT: SD/MMC Internal Transceiver (3.0V) >> Watchdog enabled >> I2C: ready >> DRAM: 1 GiB >> MMC: dwmmc0 at ff704000: 0 >> In: serial >> Out: serial >> Err: serial >> Model: Terasic DE0-Nano(Atlas) >> Net: eth0: ethernet at ff702000 >> Hit any key to stop autoboot: 0 >> => >> >> Sorry, I know that doesn't help. So let's walk through my workflow. I am >> not using any Altera tools when I build. >> >> $make socfpga_de0_nano_soc_defconfig >> $make u-boot-with-spl.sfp >> $dd if=u-boot-with-spl.sfp of=/dev/sdb3 >> >> My gcc is: arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1) 4.7.3 >> >> Has the board ever worked for you at all? Can you try this image: >> >> https://rocketboards.org/foswiki/view/Documentation/AtlasSoCSdCardImage >> >> Dinh >> >> > > Hi All, > > Was away...sorry... back again. > > Dinh - my workflow is exactly as yours is above. > > I've used several toolchains - always the same result. > > The first de0_nano_soc board I bought has no problem booting from the > factory supplied image: > > SPL: U-Boot SPL 2013.01.01 (Dec 29 2014 - 15:29:15) > Image: U-Boot 2013.01.01 (Dec 30 2014 - 12:07:34) > > and it even works with some USB sticks. > > But if I build a new SPL/image with workflow above using v2016.03 > > (git clone git://git.denx.de/u-boot.git u-boot/ or git clone > http://git.denx.de/u-boot.git u-boot/) > > then I get the intermittent failing memory calibration and no USB > (dwc_otg_core_host_init: Timeout!...) > > On my sockit board the memory calibration fails every time. Are you willing to debug this stuff ? I have an idea how to do comparative debugging if you have time to spare. > So I ordered and received a _second_ de0_nano_soc board. > > The same SPL/image that was intermittently failing on the first board > works on the second board. I have not seen it fail after 20 reboots. > > Unfortunately, USB behaves the same (dwc_otg_core_host_init: Timeout!...) > > Not sure what that means... marginal boards from Terasic? Calibration > tests/parameters too stringent? Code being slightly different than what Altera ships ... ;-) > --George > -- Best regards, Marek Vasut