From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757734AbcCaSmB (ORCPT ); Thu, 31 Mar 2016 14:42:01 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12940 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757203AbcCaSl6 (ORCPT ); Thu, 31 Mar 2016 14:41:58 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 31 Mar 2016 11:40:39 -0700 Message-ID: <56FD6CF7.5080909@nvidia.com> Date: Fri, 1 Apr 2016 00:01:19 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Mark Brown CC: Bjorn Andersson , Bjorn Andersson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Liam Girdwood , "Stephen Warren" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gandhar Dighe , "Stuart Yates" Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior References: <56E81103.8010903@nvidia.com> <56ED0F58.7060005@nvidia.com> <56FBD4A3.7080208@nvidia.com> <20160330181623.GQ2350@sirena.org.uk> <56FCCC60.3080303@nvidia.com> <20160331165145.GF2350@sirena.org.uk> <56FD5A9F.5050001@nvidia.com> <20160331174741.GO2350@sirena.org.uk> <56FD62BA.3040406@nvidia.com> <20160331183130.GR2350@sirena.org.uk> In-Reply-To: <20160331183130.GR2350@sirena.org.uk> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 01 April 2016 12:01 AM, Mark Brown wrote: > * PGP Signed by an unknown key > > On Thu, Mar 31, 2016 at 11:17:38PM +0530, Laxman Dewangan wrote: > >> HW and chip team did simulation with tegra and PMIC and found that the board >> needs more capacitance then what Vendor recommended for proper signal >> conditioning on interface. So they put the difference capactitance value and >> this causes deviation in ramp delay from advertised value. In out design, we >> measured the ramp time as 50mv/us when PMIC is configured for 100mV/us. >> So for all settling time, we need to use the ramp as 50mV/us. >> From DT, I will provide regulator-ramp-delay as 50mv/us. >> But I do not have property for saying 100mv/us for PMIC configurations and >> this is what makes need of 2nd property. > So the PMIC actually has a setting for the rate you're seeing but for > some resaon you can't use it? PMIC has the different rate setting what I am seeing on platform (measured). HW team measured the ramp dealy with specific configuration of rate setting on PMIC which is not default (OTP-One time programmed from Vendor). From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laxman Dewangan Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior Date: Fri, 1 Apr 2016 00:01:19 +0530 Message-ID: <56FD6CF7.5080909@nvidia.com> References: <56E81103.8010903@nvidia.com> <56ED0F58.7060005@nvidia.com> <56FBD4A3.7080208@nvidia.com> <20160330181623.GQ2350@sirena.org.uk> <56FCCC60.3080303@nvidia.com> <20160331165145.GF2350@sirena.org.uk> <56FD5A9F.5050001@nvidia.com> <20160331174741.GO2350@sirena.org.uk> <56FD62BA.3040406@nvidia.com> <20160331183130.GR2350@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160331183130.GR2350-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Mark Brown Cc: Bjorn Andersson , Bjorn Andersson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Liam Girdwood , Stephen Warren , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Gandhar Dighe , Stuart Yates List-Id: devicetree@vger.kernel.org On Friday 01 April 2016 12:01 AM, Mark Brown wrote: > * PGP Signed by an unknown key > > On Thu, Mar 31, 2016 at 11:17:38PM +0530, Laxman Dewangan wrote: > >> HW and chip team did simulation with tegra and PMIC and found that the board >> needs more capacitance then what Vendor recommended for proper signal >> conditioning on interface. So they put the difference capactitance value and >> this causes deviation in ramp delay from advertised value. In out design, we >> measured the ramp time as 50mv/us when PMIC is configured for 100mV/us. >> So for all settling time, we need to use the ramp as 50mV/us. >> From DT, I will provide regulator-ramp-delay as 50mv/us. >> But I do not have property for saying 100mv/us for PMIC configurations and >> this is what makes need of 2nd property. > So the PMIC actually has a setting for the rate you're seeing but for > some resaon you can't use it? PMIC has the different rate setting what I am seeing on platform (measured). HW team measured the ramp dealy with specific configuration of rate setting on PMIC which is not default (OTP-One time programmed from Vendor). -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html