From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59343) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aoCNb-00054Z-Fz for qemu-devel@nongnu.org; Thu, 07 Apr 2016 12:02:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aoCNV-0004bd-If for qemu-devel@nongnu.org; Thu, 07 Apr 2016 12:01:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40734) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aoCNV-0004bX-D3 for qemu-devel@nongnu.org; Thu, 07 Apr 2016 12:01:53 -0400 References: <1460044433-19282-1-git-send-email-sergey.fedorov@linaro.org> <1460044433-19282-11-git-send-email-sergey.fedorov@linaro.org> From: Paolo Bonzini Message-ID: <5706846B.2060804@redhat.com> Date: Thu, 7 Apr 2016 18:01:47 +0200 MIME-Version: 1.0 In-Reply-To: <1460044433-19282-11-git-send-email-sergey.fedorov@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 10/11] tcg/mips: Make direct jump patching thread-safe List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov , qemu-devel@nongnu.org Cc: Sergey Fedorov , Richard Henderson , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Aurelien Jarno , Peter Crosthwaite On 07/04/2016 17:53, Sergey Fedorov wrote: > Ensure direct jump patching in MIPS is atomic by using > atomic_read()/atomic_set() for code patching. > > Signed-off-by: Sergey Fedorov > Signed-off-by: Sergey Fedorov > --- > tcg/mips/tcg-target.inc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c > index 682e19897db0..e65835d2096b 100644 > --- a/tcg/mips/tcg-target.inc.c > +++ b/tcg/mips/tcg-target.inc.c > @@ -1886,6 +1886,7 @@ static void tcg_target_init(TCGContext *s) > void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) > { > uint32_t *ptr = (uint32_t *)jmp_addr; > - *ptr = deposit32(*ptr, 0, 26, addr >> 2); > + uint32_t insn = atomic_read(ptr); > + atomic_write(ptr, deposit32(insn, 0, 26, addr >> 2)); Oops. :) Paolo > flush_icache_range(jmp_addr, jmp_addr + 4); > }