[PATCH 1/4] EDAC: add DDR4 flag

[PATCH 1/4] EDAC: add DDR4 flag

[Chrzaniuk, Hubert]

Make EDAC aware of DDR4/RDDR4 mem types.

Signed-off-by: Jim Snow <jim.m.snow@intel.com>
Signed-off-by: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
---
 include/linux/edac.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/linux/edac.h b/include/linux/edac.h
index 4fe67b8..da69648 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -237,8 +237,10 @@ enum mem_type {
 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 #define MEM_FLAG_XDR            BIT(MEM_XDR)
-#define MEM_FLAG_DDR3		 BIT(MEM_DDR3)
-#define MEM_FLAG_RDDR3		 BIT(MEM_RDDR3)
+#define MEM_FLAG_DDR3           BIT(MEM_DDR3)
+#define MEM_FLAG_RDDR3          BIT(MEM_RDDR3)
+#define MEM_FLAG_DDR4           BIT(MEM_DDR4)
+#define MEM_FLAG_RDDR4          BIT(MEM_RDDR4)
 
 /**
  * enum edac-type - Error Detection and Correction capabilities and mode
-- 
1.8.3.1

--------------------------------------------------------------------

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RE: [PATCH 1/4] EDAC: add DDR4 flag

[Luck, Tony]

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> It already has your Reviewed-by. Is it still valid?

So it does ... that was a long time ago ... but not so long that anything important changed. Yes, still valid.

-Tony
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: [PATCH 1/4] EDAC: add DDR4 flag

[Borislav Petkov]

On Thu, Dec 03, 2015 at 07:16:29PM +0000, Luck, Tony wrote:
> part4 (the actual KNL piece) seems not to break earlier (Broadwell)
> system ... but that doesn't qualify enough for Ack/Review/Tested -by.

It already has your Reviewed-by. Is it still valid?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

RE: [PATCH 1/4] EDAC: add DDR4 flag

[Luck, Tony]

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> For patch 2 and 3 I'd need an ack from Mauro/Tony. CCed.

parts 2 & 3 are OK

Acked-by: Tony Luck <tony.luck@intel.com>

part4 (the actual KNL piece) seems not to break earlier (Broadwell) system ... but that doesn't qualify enough for Ack/Review/Tested -by.


-Tony
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: [PATCH 1/4] EDAC: add DDR4 flag

[Borislav Petkov]

On Thu, Dec 03, 2015 at 10:48:51AM +0100, Hubert Chrzaniuk wrote:
> From: Jim Snow <jim.m.snow@intel.com>
> 
> Make EDAC aware of DDR4/RDDR4 mem types.
> 
> Signed-off-by: Jim Snow <jim.m.snow@intel.com>
> [hubert.chrzaniuk@intel.com: patch rebase to 4.4-rc3]
> Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
> ---
>  include/linux/edac.h | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Applied, thanks.

For patch 2 and 3 I'd need an ack from Mauro/Tony. CCed.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

[PATCH 1/4] EDAC: add DDR4 flag

[Hubert Chrzaniuk]

From: Jim Snow <jim.m.snow@intel.com>

Make EDAC aware of DDR4/RDDR4 mem types.

Signed-off-by: Jim Snow <jim.m.snow@intel.com>
[hubert.chrzaniuk@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
---
 include/linux/edac.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/linux/edac.h b/include/linux/edac.h
index 4fe67b8..da69648 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -237,8 +237,10 @@ enum mem_type {
 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 #define MEM_FLAG_XDR            BIT(MEM_XDR)
-#define MEM_FLAG_DDR3		 BIT(MEM_DDR3)
-#define MEM_FLAG_RDDR3		 BIT(MEM_RDDR3)
+#define MEM_FLAG_DDR3           BIT(MEM_DDR3)
+#define MEM_FLAG_RDDR3          BIT(MEM_RDDR3)
+#define MEM_FLAG_DDR4           BIT(MEM_DDR4)
+#define MEM_FLAG_RDDR4          BIT(MEM_RDDR4)
 
 /**
  * enum edac-type - Error Detection and Correction capabilities and mode
-- 
1.8.3.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by
others is strictly prohibited.

Re: [PATCH 1/4] EDAC: add DDR4 flag

[Borislav Petkov]

On Thu, Dec 03, 2015 at 07:51:47AM +0000, Anaczkowski, Lukasz wrote:
> Well, although it may sound strange, yeah this is exactly the case, since
> EDAC for Knights Landing has been for a while in our private branch.
> 
> Is this sort of an issue or just curiosity?

Well, the fact that I'm asking, means it is not clear who did what. Please
document that like this:

        Signed-off-by: Random J Developer <random@developer.example.org>
        [lucky@maintainer.example.org: struct foo moved from foo.c to foo.h]
        Signed-off-by: Lucky K Maintainer <lucky@maintainer.example.org>

(example is from Documentation/SubmittingPatches where the whole authorship
 tracking is explained in detail.)

Alternatively, you can put it in free text in the commit message.

Thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

RE: [PATCH 1/4] EDAC: add DDR4 flag

[Anaczkowski, Lukasz]

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-----Original Message-----
From: Borislav Petkov [mailto:bp@alien8.de] 
Sent: Wednesday, December 2, 2015 8:28 PM
To: Chrzaniuk, Hubert <hubert.chrzaniuk@intel.com>
Cc: Anaczkowski, Lukasz <lukasz.anaczkowski@intel.com>; mchehab@osg.samsung.com; dougthompson@xmission.com; linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; Snow, Jim M <jim.m.snow@intel.com>
Subject: Re: [PATCH 1/4] EDAC: add DDR4 flag

> On Wed, Dec 02, 2015 at 04:38:29PM +0100, Hubert Chrzaniuk wrote:
>> Signed-off-by: Jim Snow <jim.m.snow@intel.com>
>> Signed-off-by: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
>> Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
>
> How am I to understand this SoB chain?
>
> Jim wrote it, Lukasz did something to it and Hubert sends it?

Well, although it may sound strange, yeah this is exactly the case, since
EDAC for Knights Landing has been for a while in our private branch.

Is this sort of an issue or just curiosity?

Thanks,
Lukasz
ÿôèº{.nÇ+‰·Ÿ®‰­†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a­¢f£¢·hšïêÿ‘êçz_è®\x03(­éšŽŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨è­Ú&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥

Re: [PATCH 1/4] EDAC: add DDR4 flag

[Borislav Petkov]

On Wed, Dec 02, 2015 at 04:38:29PM +0100, Hubert Chrzaniuk wrote:
> From: Jim Snow <jim.m.snow@intel.com>
> 
> Make EDAC aware of DDR4/RDDR4 mem types.
> 
> Signed-off-by: Jim Snow <jim.m.snow@intel.com>
> Signed-off-by: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
> Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>

How am I to understand this SoB chain?

Jim wrote it, Lukasz did something to it and Hubert sends it?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

[PATCH 1/4] EDAC: add DDR4 flag

[Hubert Chrzaniuk]

From: Jim Snow <jim.m.snow@intel.com>

Make EDAC aware of DDR4/RDDR4 mem types.

Signed-off-by: Jim Snow <jim.m.snow@intel.com>
Signed-off-by: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>

---
 include/linux/edac.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/linux/edac.h b/include/linux/edac.h
index 4fe67b8..da69648 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -237,8 +237,10 @@ enum mem_type {
 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 #define MEM_FLAG_XDR            BIT(MEM_XDR)
-#define MEM_FLAG_DDR3		 BIT(MEM_DDR3)
-#define MEM_FLAG_RDDR3		 BIT(MEM_RDDR3)
+#define MEM_FLAG_DDR3           BIT(MEM_DDR3)
+#define MEM_FLAG_RDDR3          BIT(MEM_RDDR3)
+#define MEM_FLAG_DDR4           BIT(MEM_DDR4)
+#define MEM_FLAG_RDDR4          BIT(MEM_RDDR4)
 
 /**
  * enum edac-type - Error Detection and Correction capabilities and mode
-- 
1.8.3.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by
others is strictly prohibited.