From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 13 Apr 2016 14:31:54 +0200 Subject: [U-Boot] [PATCH 0/4] Add support for Cadence QSPI on K2G In-Reply-To: <1460544768-32750-1-git-send-email-vigneshr@ti.com> References: <1460544768-32750-1-git-send-email-vigneshr@ti.com> Message-ID: <570E3C3A.7090309@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 04/13/2016 12:52 PM, Vignesh R wrote: > > This series adds support for Cadence QSPI controller present on K2G SoC. > > The first patch extends AHB address to 32 bit as K2G has 32 bit AHB > address. Second patch enable QUAD mode based on DT data instead of > relying on config option. And last to patches add DT node and add > configs to enable the driver. > > Depends on [1] to enable SPI driver model support on K2G and [2] to > support different bus frequencies for two different SPI controllers > present on K2G EVM. Are you OK if I wrap the first two patches into V11 of the Cadence QSPI submission and add your SoB to the submission? > [1]https://www.mail-archive.com/u-boot at lists.denx.de/msg209556.html > [2]https://patchwork.ozlabs.org/patch/609947/ > > Vignesh R (4): > spi: cadence_qspi_apb: Support 32 bit AHB address > spi: cadence_quadspi: Enable QUAD mode based on DT data > ARM: dts: K2G: Add support for QSPI controller > defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller > > arch/arm/dts/k2g-evm.dts | 45 ++++++++++++++++++++++++++++++++++++++++++ > arch/arm/dts/k2g.dtsi | 14 +++++++++++++ > configs/k2g_evm_defconfig | 2 ++ > drivers/spi/cadence_qspi.c | 3 ++- > drivers/spi/cadence_qspi.h | 2 +- > drivers/spi/cadence_qspi_apb.c | 15 +++++++------- > include/configs/k2g_evm.h | 6 ++++++ > 7 files changed, 77 insertions(+), 10 deletions(-) > -- Best regards, Marek Vasut