From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/4] spi: cadence_qspi_apb: Support 32 bit AHB address
Date: Wed, 13 Apr 2016 15:57:40 +0200 [thread overview]
Message-ID: <570E5054.5060900@denx.de> (raw)
In-Reply-To: <1460544768-32750-2-git-send-email-vigneshr@ti.com>
On 04/13/2016 12:52 PM, Vignesh R wrote:
> AHB address can be as long as 32 bit, hence remove the
> CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
> and read as u32 value, it anyway does not make sense to mask upper bits.
>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
> drivers/spi/cadence_qspi_apb.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
Oops, I didn't realize this was for U-Boot.
On SoCFPGA SoCkit:
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Best regards,
Marek Vasut
next prev parent reply other threads:[~2016-04-13 13:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-13 10:52 [U-Boot] [PATCH 0/4] Add support for Cadence QSPI on K2G Vignesh R
2016-04-13 10:52 ` [U-Boot] [PATCH 1/4] spi: cadence_qspi_apb: Support 32 bit AHB address Vignesh R
2016-04-13 13:57 ` Marek Vasut [this message]
2016-04-13 10:52 ` [U-Boot] [PATCH 2/4] spi: cadence_quadspi: Enable QUAD mode based on DT data Vignesh R
2016-04-13 13:58 ` Marek Vasut
2016-04-13 10:52 ` [U-Boot] [PATCH 3/4] ARM: dts: K2G: Add support for QSPI controller Vignesh R
2016-04-13 19:47 ` Tom Rini
2016-04-13 10:52 ` [U-Boot] [PATCH 4/4] defconfig: k2g_evm_defconfig: Enable Cadence " Vignesh R
2016-04-13 19:47 ` Tom Rini
2016-04-13 12:31 ` [U-Boot] [PATCH 0/4] Add support for Cadence QSPI on K2G Marek Vasut
2016-05-09 14:34 ` Jagan Teki
2016-05-10 6:52 ` Vignesh R
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