From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753956AbcDNJcZ (ORCPT ); Thu, 14 Apr 2016 05:32:25 -0400 Received: from foss.arm.com ([217.140.101.70]:40772 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753718AbcDNJcU (ORCPT ); Thu, 14 Apr 2016 05:32:20 -0400 Subject: Re: [PATCH v4 2/5] ARC: clocksource: DT based probe To: Vineet Gupta , Thomas Gleixner , Jason Cooper , Daniel Lezcano References: <1460547605-26184-1-git-send-email-vgupta@synopsys.com> <1460547605-26184-3-git-send-email-vgupta@synopsys.com> <570E7263.8070108@arm.com> <570F623B.3000105@synopsys.com> Cc: linux-snps-arc@lists.infradead.org, linux-kernel@vger.kernel.org, Noam Camus From: Marc Zyngier Organization: ARM Ltd Message-ID: <570F63A1.3070904@arm.com> Date: Thu, 14 Apr 2016 10:32:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: <570F623B.3000105@synopsys.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/04/16 10:26, Vineet Gupta wrote: > On Wednesday 13 April 2016 09:52 PM, Marc Zyngier wrote: >>> -int arc_counter_setup(void) >>>> +static void __init arc_cs_setup_rtc(struct device_node *node) >>>> { >>>> - write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); >>>> - write_aux_reg(ARC_REG_TIMER1_CNT, 0); >>>> - write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); >>>> + int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc; >>>> + >>>> + if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected")) >>>> + return; >>>> + >>>> + /* Local to CPU hence not usable in SMP */ >>>> + if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP")) >>>> + return; >> Sorry if this outlines my lack of understanding of the ARC architecture, >> but what makes per-cpu timer unsuitable for SMP? I'd have thought that >> it was actually what you wanted... > > This is clocksource, not clockevent. cs needs to synchronized across all cores so > that concurrent gtod call from threads on different cores gives you similar > values. This obviously is not true for the local RTC hardware timer. Unsynchronized counters on SMP HW, who would have thought! ;-) I guess each and every architecture has to repeat the same mistakes. Thanks for shedding some light on it. M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Thu, 14 Apr 2016 10:32:17 +0100 Subject: [PATCH v4 2/5] ARC: clocksource: DT based probe In-Reply-To: <570F623B.3000105@synopsys.com> References: <1460547605-26184-1-git-send-email-vgupta@synopsys.com> <1460547605-26184-3-git-send-email-vgupta@synopsys.com> <570E7263.8070108@arm.com> <570F623B.3000105@synopsys.com> List-ID: Message-ID: <570F63A1.3070904@arm.com> To: linux-snps-arc@lists.infradead.org On 14/04/16 10:26, Vineet Gupta wrote: > On Wednesday 13 April 2016 09:52 PM, Marc Zyngier wrote: >>> -int arc_counter_setup(void) >>>> +static void __init arc_cs_setup_rtc(struct device_node *node) >>>> { >>>> - write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); >>>> - write_aux_reg(ARC_REG_TIMER1_CNT, 0); >>>> - write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); >>>> + int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc; >>>> + >>>> + if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected")) >>>> + return; >>>> + >>>> + /* Local to CPU hence not usable in SMP */ >>>> + if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP")) >>>> + return; >> Sorry if this outlines my lack of understanding of the ARC architecture, >> but what makes per-cpu timer unsuitable for SMP? I'd have thought that >> it was actually what you wanted... > > This is clocksource, not clockevent. cs needs to synchronized across all cores so > that concurrent gtod call from threads on different cores gives you similar > values. This obviously is not true for the local RTC hardware timer. Unsynchronized counters on SMP HW, who would have thought! ;-) I guess each and every architecture has to repeat the same mistakes. Thanks for shedding some light on it. M. -- Jazz is not dead. It just smells funny...