From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751638AbcDTMrQ (ORCPT ); Wed, 20 Apr 2016 08:47:16 -0400 Received: from foss.arm.com ([217.140.101.70]:47308 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750767AbcDTMrP (ORCPT ); Wed, 20 Apr 2016 08:47:15 -0400 Subject: Re: [PATCH v7 01/10] iommu: Add DOMAIN_ATTR_MSI_MAPPING attribute To: Eric Auger , eric.auger@st.com, alex.williamson@redhat.com, will.deacon@arm.com, joro@8bytes.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, christoffer.dall@linaro.org, linux-arm-kernel@lists.infradead.org References: <1461084994-2355-1-git-send-email-eric.auger@linaro.org> <1461084994-2355-2-git-send-email-eric.auger@linaro.org> Cc: patches@linaro.org, linux-kernel@vger.kernel.org, Bharat.Bhushan@freescale.com, pranav.sawargaonkar@gmail.com, p.fedin@samsung.com, iommu@lists.linux-foundation.org, Jean-Philippe.Brucker@arm.com, julien.grall@arm.com From: Robin Murphy Message-ID: <57177A4E.4090804@arm.com> Date: Wed, 20 Apr 2016 13:47:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1461084994-2355-2-git-send-email-eric.auger@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Eric, On 19/04/16 17:56, Eric Auger wrote: > Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported, > this means the MSI addresses need to be mapped in the IOMMU. > > x86 IOMMUs typically don't expose the attribute since on x86, MSI write > transaction addresses always are within the 1MB PA region [FEE0_0000h - > FEF0_000h] window which directly targets the APIC configuration space and > hence bypass the sMMU. On ARM and PowerPC however MSI transactions are > conveyed through the IOMMU. What's stopping us from simply inferring this from the domain's IOMMU not advertising interrupt remapping capabilities? Robin. > Signed-off-by: Bharat Bhushan > Signed-off-by: Eric Auger > > --- > > v4 -> v5: > - introduce the user in the next patch > > RFC v1 -> v1: > - the data field is not used > - for this attribute domain_get_attr simply returns 0 if the MSI_MAPPING > capability if needed or <0 if not. > - removed struct iommu_domain_msi_maps > --- > include/linux/iommu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 62a5eae..b3e8c5b 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -113,6 +113,7 @@ enum iommu_attr { > DOMAIN_ATTR_FSL_PAMU_ENABLE, > DOMAIN_ATTR_FSL_PAMUV1, > DOMAIN_ATTR_NESTING, /* two stages of translation */ > + DOMAIN_ATTR_MSI_MAPPING, /* Require MSIs mapping in iommu */ > DOMAIN_ATTR_MAX, > }; > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robin Murphy Subject: Re: [PATCH v7 01/10] iommu: Add DOMAIN_ATTR_MSI_MAPPING attribute Date: Wed, 20 Apr 2016 13:47:10 +0100 Message-ID: <57177A4E.4090804@arm.com> References: <1461084994-2355-1-git-send-email-eric.auger@linaro.org> <1461084994-2355-2-git-send-email-eric.auger@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1461084994-2355-2-git-send-email-eric.auger-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Eric Auger , eric.auger-qxv4g6HH51o@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org, jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org, marc.zyngier-5wv7dgnIgG8@public.gmane.org, christoffer.dall-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: julien.grall-5wv7dgnIgG8@public.gmane.org, patches-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, p.fedin-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, pranav.sawargaonkar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org List-Id: iommu@lists.linux-foundation.org Hi Eric, On 19/04/16 17:56, Eric Auger wrote: > Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported, > this means the MSI addresses need to be mapped in the IOMMU. > > x86 IOMMUs typically don't expose the attribute since on x86, MSI write > transaction addresses always are within the 1MB PA region [FEE0_0000h - > FEF0_000h] window which directly targets the APIC configuration space and > hence bypass the sMMU. On ARM and PowerPC however MSI transactions are > conveyed through the IOMMU. What's stopping us from simply inferring this from the domain's IOMMU not advertising interrupt remapping capabilities? Robin. > Signed-off-by: Bharat Bhushan > Signed-off-by: Eric Auger > > --- > > v4 -> v5: > - introduce the user in the next patch > > RFC v1 -> v1: > - the data field is not used > - for this attribute domain_get_attr simply returns 0 if the MSI_MAPPING > capability if needed or <0 if not. > - removed struct iommu_domain_msi_maps > --- > include/linux/iommu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 62a5eae..b3e8c5b 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -113,6 +113,7 @@ enum iommu_attr { > DOMAIN_ATTR_FSL_PAMU_ENABLE, > DOMAIN_ATTR_FSL_PAMUV1, > DOMAIN_ATTR_NESTING, /* two stages of translation */ > + DOMAIN_ATTR_MSI_MAPPING, /* Require MSIs mapping in iommu */ > DOMAIN_ATTR_MAX, > }; > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: robin.murphy@arm.com (Robin Murphy) Date: Wed, 20 Apr 2016 13:47:10 +0100 Subject: [PATCH v7 01/10] iommu: Add DOMAIN_ATTR_MSI_MAPPING attribute In-Reply-To: <1461084994-2355-2-git-send-email-eric.auger@linaro.org> References: <1461084994-2355-1-git-send-email-eric.auger@linaro.org> <1461084994-2355-2-git-send-email-eric.auger@linaro.org> Message-ID: <57177A4E.4090804@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Eric, On 19/04/16 17:56, Eric Auger wrote: > Introduce a new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported, > this means the MSI addresses need to be mapped in the IOMMU. > > x86 IOMMUs typically don't expose the attribute since on x86, MSI write > transaction addresses always are within the 1MB PA region [FEE0_0000h - > FEF0_000h] window which directly targets the APIC configuration space and > hence bypass the sMMU. On ARM and PowerPC however MSI transactions are > conveyed through the IOMMU. What's stopping us from simply inferring this from the domain's IOMMU not advertising interrupt remapping capabilities? Robin. > Signed-off-by: Bharat Bhushan > Signed-off-by: Eric Auger > > --- > > v4 -> v5: > - introduce the user in the next patch > > RFC v1 -> v1: > - the data field is not used > - for this attribute domain_get_attr simply returns 0 if the MSI_MAPPING > capability if needed or <0 if not. > - removed struct iommu_domain_msi_maps > --- > include/linux/iommu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 62a5eae..b3e8c5b 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -113,6 +113,7 @@ enum iommu_attr { > DOMAIN_ATTR_FSL_PAMU_ENABLE, > DOMAIN_ATTR_FSL_PAMUV1, > DOMAIN_ATTR_NESTING, /* two stages of translation */ > + DOMAIN_ATTR_MSI_MAPPING, /* Require MSIs mapping in iommu */ > DOMAIN_ATTR_MAX, > }; > >