From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753465AbcDVHnW (ORCPT ); Fri, 22 Apr 2016 03:43:22 -0400 Received: from foss.arm.com ([217.140.101.70]:59602 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751851AbcDVHnV (ORCPT ); Fri, 22 Apr 2016 03:43:21 -0400 Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support To: Leo Li References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> <20160307095021.7f9f7484@arm.com> Cc: Minghuan Lian , "linux-arm-kernel@lists.infradead.org" , lkml , Thomas Gleixner , Jason Cooper , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li , Rob Herring , Mark Rutland From: Marc Zyngier Organization: ARM Ltd Message-ID: <5719D614.1080400@arm.com> Date: Fri, 22 Apr 2016 08:43:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/04/16 06:33, Leo Li wrote: > On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote: >> On Mon, 7 Mar 2016 11:36:22 +0800 >> Minghuan Lian wrote: >> >>> Some kind of NXP Layerscape SoC provides a MSI >>> implementation which uses two SCFG registers MSIIR and >>> MSIR to support 32 MSI interrupts for each PCIe controller. >>> The patch is to support it. >>> >>> Signed-off-by: Minghuan Lian >> >> Acked-by: Marc Zyngier >> >> The DT binding still needs an Ack from the DT maintainers though (cc'd). > > Marc, > > Who will be responsible to pick this driver? I see you are also one > of the maintainers for irqchip. Can you pick up the driver? The > binding has already gotten ACKed by the device tree maintainer. Can you point me to this Ack? I can't see any trace of it in my Inbox. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Fri, 22 Apr 2016 08:43:16 +0100 Subject: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support In-Reply-To: References: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com> <20160307095021.7f9f7484@arm.com> Message-ID: <5719D614.1080400@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 22/04/16 06:33, Leo Li wrote: > On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier wrote: >> On Mon, 7 Mar 2016 11:36:22 +0800 >> Minghuan Lian wrote: >> >>> Some kind of NXP Layerscape SoC provides a MSI >>> implementation which uses two SCFG registers MSIIR and >>> MSIR to support 32 MSI interrupts for each PCIe controller. >>> The patch is to support it. >>> >>> Signed-off-by: Minghuan Lian >> >> Acked-by: Marc Zyngier >> >> The DT binding still needs an Ack from the DT maintainers though (cc'd). > > Marc, > > Who will be responsible to pick this driver? I see you are also one > of the maintainers for irqchip. Can you pick up the driver? The > binding has already gotten ACKed by the device tree maintainer. Can you point me to this Ack? I can't see any trace of it in my Inbox. Thanks, M. -- Jazz is not dead. It just smells funny...