From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752921AbcD0LVX (ORCPT ); Wed, 27 Apr 2016 07:21:23 -0400 Received: from foss.arm.com ([217.140.101.70]:34092 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752355AbcD0LVW (ORCPT ); Wed, 27 Apr 2016 07:21:22 -0400 Subject: Re: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API To: Mathieu Poirier , linux-arm-kernel@lists.infradead.org References: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> <1461708634-6327-17-git-send-email-mathieu.poirier@linaro.org> Cc: linux-kernel@vger.kernel.org From: Suzuki K Poulose Message-ID: <5720A0AF.9090107@arm.com> Date: Wed, 27 Apr 2016 12:21:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1461708634-6327-17-git-send-email-mathieu.poirier@linaro.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26/04/16 23:10, Mathieu Poirier wrote: > This patch implement the AUX area interfaces required to > use the TMC (configured as an ETF) from the Perf sub-system. > > The heuristic is heavily borrowed from the ETB10 implementation. > > Signed-off-by: Mathieu Poirier > + > + /* > + * Make sure the new size is aligned in accordance with the > + * requirement explained above. > + */ > + to_read = handle->size & mask; > + /* Move the RAM read pointer up */ > + read_ptr = (write_ptr + drvdata->size) - to_read; > + /* Make sure we are still within our limits */ > + read_ptr &= ~(drvdata->size - 1); Correct me if I am wrong, I think this will break for ETR configuration (used from the following patch 17/18). Since, for ETR, RRP/RWP will return the lower 32bit AXI address (not the queue offset). So the last step would really spoil the read_ptr. We might have to set the read_ptr by adding the appropriate offset from DBAL0. Suzuki From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suzuki.Poulose@arm.com (Suzuki K Poulose) Date: Wed, 27 Apr 2016 12:21:19 +0100 Subject: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API In-Reply-To: <1461708634-6327-17-git-send-email-mathieu.poirier@linaro.org> References: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> <1461708634-6327-17-git-send-email-mathieu.poirier@linaro.org> Message-ID: <5720A0AF.9090107@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 26/04/16 23:10, Mathieu Poirier wrote: > This patch implement the AUX area interfaces required to > use the TMC (configured as an ETF) from the Perf sub-system. > > The heuristic is heavily borrowed from the ETB10 implementation. > > Signed-off-by: Mathieu Poirier > + > + /* > + * Make sure the new size is aligned in accordance with the > + * requirement explained above. > + */ > + to_read = handle->size & mask; > + /* Move the RAM read pointer up */ > + read_ptr = (write_ptr + drvdata->size) - to_read; > + /* Make sure we are still within our limits */ > + read_ptr &= ~(drvdata->size - 1); Correct me if I am wrong, I think this will break for ETR configuration (used from the following patch 17/18). Since, for ETR, RRP/RWP will return the lower 32bit AXI address (not the queue offset). So the last step would really spoil the read_ptr. We might have to set the read_ptr by adding the appropriate offset from DBAL0. Suzuki