From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b4XwG-00006X-Qt for qemu-devel@nongnu.org; Sun, 22 May 2016 14:17:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b4XwC-0004bD-Mx for qemu-devel@nongnu.org; Sun, 22 May 2016 14:17:20 -0400 Received: from mout.web.de ([212.227.17.11]:55062) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b4XwC-0004b9-D2 for qemu-devel@nongnu.org; Sun, 22 May 2016 14:17:16 -0400 References: <1463912514-12658-1-git-send-email-davidkiarie4@gmail.com> <1463912514-12658-2-git-send-email-davidkiarie4@gmail.com> <5741F689.9040108@web.de> From: Jan Kiszka Message-ID: <5741F7A4.7060308@web.de> Date: Sun, 22 May 2016 20:17:08 +0200 MIME-Version: 1.0 In-Reply-To: <5741F689.9040108@web.de> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="nmSubFS60mR9DstXwJkeBSN1SAvJ7762m" Subject: Re: [Qemu-devel] [V11 1/4] hw/i386: Introduce AMD IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Kiarie , qemu-devel@nongnu.org Cc: mst@redhat.com, marcel@redhat.com, peterx@redhat.com, valentine.sinitsyn@gmail.com This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --nmSubFS60mR9DstXwJkeBSN1SAvJ7762m From: Jan Kiszka To: David Kiarie , qemu-devel@nongnu.org Cc: mst@redhat.com, marcel@redhat.com, peterx@redhat.com, valentine.sinitsyn@gmail.com Message-ID: <5741F7A4.7060308@web.de> Subject: Re: [V11 1/4] hw/i386: Introduce AMD IOMMU References: <1463912514-12658-1-git-send-email-davidkiarie4@gmail.com> <1463912514-12658-2-git-send-email-davidkiarie4@gmail.com> <5741F689.9040108@web.de> In-Reply-To: <5741F689.9040108@web.de> Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable On 2016-05-22 20:12, Jan Kiszka wrote: > On 2016-05-22 12:21, David Kiarie wrote: >> +static void amdvi_page_walk(AMDVIAddressSpace *as, uint64_t *dte, >> + IOMMUTLBEntry *ret, unsigned perms, >> + hwaddr addr) >> +{ >> + unsigned level, present, pte_perms, oldlevel; >> + uint64_t pte =3D dte[0], pte_addr, page_mask; >> + >> + /* make sure the DTE has TV =3D 1 */ >> + if (pte & AMDVI_DEV_TRANSLATION_VALID) { >> + level =3D get_pte_translation_mode(pte); >> + if (level >=3D 7) { >> + AMDVI_DPRINTF(MMU, "error: translation level 0x%"PRIu8 " = detected" >> + " while translating 0x%"PRIx64, level, addr= ); >> + return; >> + } >> + if (level =3D=3D 0) { >> + goto no_remap; >> + } >> + >> + /* we are at the leaf page table or page table encodes a huge= page */ >> + while (level > 0) { >> + pte_perms =3D amdvi_get_perms(pte); >> + present =3D pte & 1; >> + if (!present || perms !=3D (perms & pte_perms)) { >> + amdvi_page_fault(as->iommu_state, as->devfn, addr, pe= rms); >> + AMDVI_DPRINTF(CUSTOM, "error: page fault accessing vi= rtual " >> + "addr 0x%"PRIx64, addr); >> + return; >> + } >> + >> + /* go to the next lower level */ >> + pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; >> + /* add offset and load pte */ >> + pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; >> + pte =3D ldq_phys(&address_space_memory, pte_addr); >=20 > I think this should be address_space_ldq_le. ldq_phys is for usage by > CPUs only (and it breaks the build over master). Correction: dma_memory_read, and then you need to do the byte-swapping afterwards. Not the dma_memory_read may return an error if the address points to something invalid. You will have to enable this (like a non-present entry). See also the Intel IOMMU code. Jan --nmSubFS60mR9DstXwJkeBSN1SAvJ7762m Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAldB96UACgkQitSsb3rl5xSxZwCgthGN0LymzfoT+r7pqgshpZYz Pt0AniQ01XXxsBzI9Lg6HvzEFF0kd2fX =IXsJ -----END PGP SIGNATURE----- --nmSubFS60mR9DstXwJkeBSN1SAvJ7762m--